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[/] [qaz_libs/] [trunk/] [camera_link/] [sim/] [src/] [camera_link_clk.v] - Blame information for rev 27

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1 27 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2013 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`timescale 10ps/1ps
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module camera_link_clk
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(
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  input             clk_in,
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  output reg [3:0]  clk_7x_index,
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  output            clk_out_7x,
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  output            clock_good,
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  input             reset
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);
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  // --------------------------------------------------------------------
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  //
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  clock_mult
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    #( .MULT(7) )
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    clk_out_7x_i
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    (
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      .clock_in(clk_in),
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      .clock_out(clk_out_7x),
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      .clock_good(clock_good),
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      .reset(reset)
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    );
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  // --------------------------------------------------------------------
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  //
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  wire delayed_clk_in;
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  assign #1 delayed_clk_in = clk_in;
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  wire clk_in_rise = (delayed_clk_in == 1'b0) & (clk_in == 1'b1);
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  always @(posedge clk_out_7x)
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    begin
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      if(clk_in_rise)
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        clk_7x_index <= 5;
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      else if( clk_7x_index >= 6 )
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        clk_7x_index <= 0;
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      else
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        clk_7x_index <= clk_7x_index + 1;
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    end
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endmodule
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