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[/] [qaz_libs/] [trunk/] [coaxpress/] [cx_bit_align.v] - Blame information for rev 2

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1 2 qaztronic
//
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//
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//
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module
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  cx_bit_align
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  (
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    input               data_in,
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    output reg  [9:0]   data_out,
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    output              clock,
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    output              strobe,
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    input               data_sent_lsb,
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    input               reset
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  );
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  // using big endian as presented in US4,486,739
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  localparam K27_7_10b = 10'b110110_1000;  //  K27.7 Start of data packet indication
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  localparam K28_0_10b = 10'b001111_0100;  //  K28.0 GPIO indication
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  localparam K28_6_10b = 10'b001111_0110;  //  K28.6 I/O acknowledgement
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  localparam K28_1_10b = 10'b001111_1001;  //  K28.1 Used for alignment
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  localparam K28_2_10b = 10'b001111_0101;  //  K28.2 Rising trigger indication
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  localparam K28_3_10b = 10'b001111_0011;  //  K28.3 Stream marker  see section 7.2
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  localparam K28_4_10b = 10'b001111_0010;  //  K28.4 Falling trigger indication
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  localparam K28_5_10b = 10'b001111_1010;  //  K28.5 Used for alignment
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  localparam K28_7_10b = 10'b001111_1000;  //  K29.7 End of data packet indication
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  localparam D21_5_10b = 10'b101010_1010;
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//  wire clock_n;
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//  assign  clock = clock_n;
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  // --------------------------------------------------------------------
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  //
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  recover_clock
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    i_recover_clock
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    (
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      .in(data_in),
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      .clock(clock)
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    );
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  // --------------------------------------------------------------------
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  // four word shift register
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  reg [39:0] data_in_r;
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  always @( negedge clock )
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    if( data_sent_lsb )
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      data_in_r <= { data_in_r[38:0], data_in };
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    else
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      data_in_r <= { data_in, data_in_r[39:1] };
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  // --------------------------------------------------------------------
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  //
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  integer bit_count = 0;
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  always @( negedge clock )
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    if( bit_count == 9 )
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      bit_count <= 0;
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    else
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      bit_count <= bit_count + 1;
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  // --------------------------------------------------------------------
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  //
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  wire p3_is_D21_5_msb = (data_in_r[39:30] == D21_5_10b) | (data_in_r[39:30]  == ~D21_5_10b);
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  wire p2_is_K28_1_msb = (data_in_r[29:20] == K28_1_10b) | (data_in_r[29:20]  == ~K28_1_10b);
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  wire p1_is_K28_1_msb = (data_in_r[19:10] == K28_1_10b) | (data_in_r[19:10]  == ~K28_1_10b);
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  wire p0_is_K28_5_msb = (data_in_r[9:0]   == K28_5_10b) | (data_in_r[9:0]    == ~K28_5_10b);
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  wire p3_is_D21_5_lsb = (data_in_r[9:0]    == D21_5_10b) | (data_in_r[9:0]    == ~D21_5_10b);
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  wire p2_is_K28_1_lsb = (data_in_r[19:10]  == K28_1_10b) | (data_in_r[19:10]  == ~K28_1_10b);
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  wire p1_is_K28_1_lsb = (data_in_r[29:20]  == K28_1_10b) | (data_in_r[29:20]  == ~K28_1_10b);
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  wire p0_is_K28_5_lsb = (data_in_r[39:30]  == K28_5_10b) | (data_in_r[39:30]  == ~K28_5_10b);
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  wire found_idle_word = data_sent_lsb ?  (p0_is_K28_5_lsb & p1_is_K28_1_lsb & p2_is_K28_1_lsb & p3_is_D21_5_lsb) :
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                                          (p0_is_K28_5_msb & p1_is_K28_1_msb & p2_is_K28_1_msb & p3_is_D21_5_msb);
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  integer bit_select = 'hx;
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  always @( posedge clock )
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    if( reset )
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      bit_select <= 'hx;
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    else if( found_idle_word )
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      bit_select <= bit_count;
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  // --------------------------------------------------------------------
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  //  register parallel outputs in litle endian bit order
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  integer i;
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  always @( posedge clock )
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    if( bit_count == bit_select )
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      for( i = 0; i < 10; i = i + 1 )
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        data_out[i] <= data_in_r[9-i];
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  // --------------------------------------------------------------------
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  // debug  --  look for control codes
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`ifdef DEBUG_COAXPRESS
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  wire dbg_p0_is_K27_7 = (data_in_r[9:0]   == K27_7_10b) | (data_in_r[9:0]    == ~K27_7_10b);
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  wire dbg_p0_is_K28_0 = (data_in_r[9:0]   == K28_0_10b) | (data_in_r[9:0]    == ~K28_0_10b);
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  wire dbg_p0_is_K28_6 = (data_in_r[9:0]   == K28_6_10b) | (data_in_r[9:0]    == ~K28_6_10b);
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  wire dbg_p0_is_K28_1 = (data_in_r[9:0]   == K28_1_10b) | (data_in_r[9:0]    == ~K28_1_10b);
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  wire dbg_p0_is_K28_2 = (data_in_r[9:0]   == K28_2_10b) | (data_in_r[9:0]    == ~K28_2_10b);
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  wire dbg_p0_is_K28_3 = (data_in_r[9:0]   == K28_3_10b) | (data_in_r[9:0]    == ~K28_3_10b);
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  wire dbg_p0_is_K28_4 = (data_in_r[9:0]   == K28_4_10b) | (data_in_r[9:0]    == ~K28_4_10b);
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  wire dbg_p0_is_K28_5 = (data_in_r[9:0]   == K28_5_10b) | (data_in_r[9:0]    == ~K28_5_10b);
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  wire dbg_p0_is_K28_7 = (data_in_r[9:0]   == K28_7_10b) | (data_in_r[9:0]    == ~K28_7_10b);
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  wire dbg_p0_is_D21_5 = (data_in_r[9:0]   == D21_5_10b) | (data_in_r[9:0]    == ~D21_5_10b);
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  // debug  --  four word shift register, reverse bit order
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  reg [39:0] dbg_data_in_n_r;
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  always @( negedge clock )
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    dbg_data_in_n_r <= { data_in, dbg_data_in_n_r[39:1] };
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  wire dbg_p0_is_K27_7_n = (dbg_data_in_n_r[9:0]   == K27_7_10b) | (dbg_data_in_n_r[9:0]    == ~K27_7_10b);
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  wire dbg_p0_is_K28_0_n = (dbg_data_in_n_r[9:0]   == K28_0_10b) | (dbg_data_in_n_r[9:0]    == ~K28_0_10b);
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  wire dbg_p0_is_K28_6_n = (dbg_data_in_n_r[9:0]   == K28_6_10b) | (dbg_data_in_n_r[9:0]    == ~K28_6_10b);
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  wire dbg_p0_is_K28_1_n = (dbg_data_in_n_r[9:0]   == K28_1_10b) | (dbg_data_in_n_r[9:0]    == ~K28_1_10b);
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  wire dbg_p0_is_K28_2_n = (dbg_data_in_n_r[9:0]   == K28_2_10b) | (dbg_data_in_n_r[9:0]    == ~K28_2_10b);
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  wire dbg_p0_is_K28_3_n = (dbg_data_in_n_r[9:0]   == K28_3_10b) | (dbg_data_in_n_r[9:0]    == ~K28_3_10b);
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  wire dbg_p0_is_K28_4_n = (dbg_data_in_n_r[9:0]   == K28_4_10b) | (dbg_data_in_n_r[9:0]    == ~K28_4_10b);
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  wire dbg_p0_is_K28_5_n = (dbg_data_in_n_r[9:0]   == K28_5_10b) | (dbg_data_in_n_r[9:0]    == ~K28_5_10b);
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  wire dbg_p0_is_K28_7_n = (dbg_data_in_n_r[9:0]   == K28_7_10b) | (dbg_data_in_n_r[9:0]    == ~K28_7_10b);
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  // debug  --  assume bit select
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  reg [9:0] dbg_data_out;
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  always @( posedge clock )
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    if( bit_count == 2 )
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      dbg_data_out <= data_in_r[9:0];
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  wire dbg_data_out_K28_5 = (dbg_data_out   == K28_5_10b) | (dbg_data_out    == ~K28_5_10b);
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  wire dbg_data_out_K28_1 = (dbg_data_out   == K28_1_10b) | (dbg_data_out    == ~K28_1_10b);
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  wire dbg_data_out_D21_5 = (dbg_data_out   == D21_5_10b) | (dbg_data_out    == ~D21_5_10b);
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`endif
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  // --------------------------------------------------------------------
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  //  register parallel outputs in litle endian bit order
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  assign strobe = (bit_count === bit_select);
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endmodule
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