OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [video/] [src/] [avf_kernel_buffer.sv] - Blame information for rev 49

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 49 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
module
29
  avf_kernel_buffer #(N, U, L, AW)
30
  (
31
    axis_if axis_in,
32
    axis_if axis_out,
33
    input   aclk,
34
    input   aresetn
35
  );
36
 
37
  // --------------------------------------------------------------------
38
  axis_if #(.N(N*L), .U(U)) a_buffer(.*);
39
 
40
  avf_line_buffer #(N, U, L, AW) line_buffer_i(.axis_out(a_buffer), .*);
41
 
42
  // --------------------------------------------------------------------
43
  localparam W = N * L * 8;
44
  localparam UB = (W*L) - 1;
45
  reg [UB:0] column;
46
 
47
  always_ff @(posedge aclk)
48
    if(a_buffer.tvalid & a_buffer.tready)
49
      column <= {a_buffer.tdata, column[UB:W]};
50
 
51
  // --------------------------------------------------------------------
52
  reg [(N*8)-1:0] kernel[L][L];
53
 
54
  generate
55
    for(genvar j = 0; j < L * L; j++)
56
    begin: kernel_gen
57
      assign  kernel[j/L][j%L] = column[j*N*8 +: N*8];
58
    end
59
  endgenerate
60
 
61
  // --------------------------------------------------------------------
62
  wire sof = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[0];
63
  wire sol = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[1];
64
  wire eol = a_buffer.tvalid & a_buffer.tready & a_buffer.tlast;
65
  wire eof = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[2];
66
  wire primed;
67
 
68
  // --------------------------------------------------------------------
69
  enum reg [4:0]
70
    {
71
      PRIME       = 5'b0_0001,
72
      SOL         = 5'b0_0010,
73
      INITIALIZED = 5'b0_0100,
74
      READY       = 5'b0_1000,
75
      EOL         = 5'b1_0000
76
    } state, next_state;
77
 
78
  // --------------------------------------------------------------------
79
  always_ff @(posedge aclk)
80
    if(~aresetn)
81
      state <= PRIME;
82
    else
83
      state <= next_state;
84
 
85
  // --------------------------------------------------------------------
86
  always_comb
87
    case(state)
88
      PRIME:        if(primed)
89
                      next_state = SOL;
90
                    else
91
                      next_state = PRIME;
92
 
93
      SOL:          if(axis_out.tready)
94
                      next_state = READY;
95
                    else
96
                      next_state = SOL;
97
 
98
      READY:        if(eol)
99
                      next_state = EOL;
100
                    else
101
                      next_state = READY;
102
 
103
      EOL:          if(axis_out.tready)
104
                      next_state = PRIME;
105
                    else
106
                      next_state = EOL;
107
 
108
      default:      next_state = PRIME;
109
    endcase
110
 
111
  // --------------------------------------------------------------------
112
  reg [$clog2(L)-1:0] count;
113
  assign primed = (count >= L - 1) & a_buffer.tvalid & a_buffer.tready;
114
  wire changing_state = (next_state != state);
115
  wire reset_counter = changing_state & (state != EOL);
116
 
117
  always_ff @(posedge aclk)
118
    if(~aresetn | reset_counter)
119
      count <= 0;
120
    else if(a_buffer.tvalid & a_buffer.tready)
121
      count <= count + 1;
122
 
123
  // --------------------------------------------------------------------
124
  reg sof_r;
125
 
126
  always_ff @(posedge aclk)
127
    if(~aresetn | (state == READY))
128
      sof_r <= 0;
129
    else if(sof)
130
      sof_r <= 1;
131
 
132
  // --------------------------------------------------------------------
133
  assign a_buffer.tready = (state == PRIME) | axis_out.tready;
134
  assign axis_out.tvalid = (state != PRIME) & a_buffer.tvalid;
135
  assign axis_out.tdata = column;
136
  // assign axis_out.tlast = a_buffer.tlast;
137
  assign axis_out.tlast = (state == EOL);
138
  // assign axis_out.tuser = a_buffer.tuser;
139
  assign axis_out.tuser[0] = (state == SOL) & sof_r;
140
  assign axis_out.tuser[1] = (state == SOL);
141
  assign axis_out.tuser[2] = (state == EOL) & eof;
142
 
143
// --------------------------------------------------------------------
144
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.