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[/] [qaz_libs/] [trunk/] [video/] [src/] [avf_kernel_buffer.sv] - Blame information for rev 49

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1 49 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  avf_kernel_buffer #(N, U, L, AW)
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  (
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    axis_if axis_in,
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    axis_if axis_out,
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    input   aclk,
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    input   aresetn
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  );
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  // --------------------------------------------------------------------
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  axis_if #(.N(N*L), .U(U)) a_buffer(.*);
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  avf_line_buffer #(N, U, L, AW) line_buffer_i(.axis_out(a_buffer), .*);
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  // --------------------------------------------------------------------
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  localparam W = N * L * 8;
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  localparam UB = (W*L) - 1;
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  reg [UB:0] column;
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  always_ff @(posedge aclk)
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    if(a_buffer.tvalid & a_buffer.tready)
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      column <= {a_buffer.tdata, column[UB:W]};
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  // --------------------------------------------------------------------
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  reg [(N*8)-1:0] kernel[L][L];
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  generate
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    for(genvar j = 0; j < L * L; j++)
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    begin: kernel_gen
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      assign  kernel[j/L][j%L] = column[j*N*8 +: N*8];
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  wire sof = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[0];
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  wire sol = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[1];
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  wire eol = a_buffer.tvalid & a_buffer.tready & a_buffer.tlast;
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  wire eof = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[2];
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  wire primed;
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  // --------------------------------------------------------------------
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  enum reg [4:0]
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    {
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      PRIME       = 5'b0_0001,
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      SOL         = 5'b0_0010,
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      INITIALIZED = 5'b0_0100,
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      READY       = 5'b0_1000,
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      EOL         = 5'b1_0000
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    } state, next_state;
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  // --------------------------------------------------------------------
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  always_ff @(posedge aclk)
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    if(~aresetn)
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      state <= PRIME;
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    else
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      state <= next_state;
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  // --------------------------------------------------------------------
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  always_comb
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    case(state)
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      PRIME:        if(primed)
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                      next_state = SOL;
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                    else
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                      next_state = PRIME;
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      SOL:          if(axis_out.tready)
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                      next_state = READY;
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                    else
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                      next_state = SOL;
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      READY:        if(eol)
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                      next_state = EOL;
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                    else
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                      next_state = READY;
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      EOL:          if(axis_out.tready)
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                      next_state = PRIME;
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                    else
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                      next_state = EOL;
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      default:      next_state = PRIME;
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    endcase
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  // --------------------------------------------------------------------
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  reg [$clog2(L)-1:0] count;
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  assign primed = (count >= L - 1) & a_buffer.tvalid & a_buffer.tready;
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  wire changing_state = (next_state != state);
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  wire reset_counter = changing_state & (state != EOL);
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  always_ff @(posedge aclk)
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    if(~aresetn | reset_counter)
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      count <= 0;
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    else if(a_buffer.tvalid & a_buffer.tready)
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      count <= count + 1;
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  // --------------------------------------------------------------------
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  reg sof_r;
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  always_ff @(posedge aclk)
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    if(~aresetn | (state == READY))
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      sof_r <= 0;
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    else if(sof)
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      sof_r <= 1;
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  // --------------------------------------------------------------------
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  assign a_buffer.tready = (state == PRIME) | axis_out.tready;
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  assign axis_out.tvalid = (state != PRIME) & a_buffer.tvalid;
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  assign axis_out.tdata = column;
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  // assign axis_out.tlast = a_buffer.tlast;
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  assign axis_out.tlast = (state == EOL);
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  // assign axis_out.tuser = a_buffer.tuser;
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  assign axis_out.tuser[0] = (state == SOL) & sof_r;
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  assign axis_out.tuser[1] = (state == SOL);
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  assign axis_out.tuser[2] = (state == EOL) & eof;
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// --------------------------------------------------------------------
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endmodule

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