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//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module

  avf_line_buffer_merge #(N, U, L)

  (

    axis_if merge_in[L],

    axis_if axis_out,

    input [L-2:0] initialized,

    input   init,

    input   flush,

    input   enable,

    input   aclk,

    input   aresetn

  );

  // --------------------------------------------------------------------

  localparam W = (N*8) + U + 1; // tdata + tuser + tlast

  // --------------------------------------------------------------------

  wire int_done[L];

  assign int_done[0] = ~init;

  generate

    for(genvar j = 1; j < L; j++)

    begin: trailing_gen

      assign int_done[j] = initialized[j-1];

    end

  endgenerate

  // --------------------------------------------------------------------

  wire [L-1:0]  wr_full;

  wire          wr_en[L];

  wire [L-1:0]  rd_empty;

  wire [W-1:0]  rd_data[L];

  wire          rd_en = axis_out.tready & axis_out.tvalid;

  wire [L-1:0] valid;

  wire all_valid = &valid;

  wire all_not_full = ~(|wr_full);

  wire all_not_empty = ~(|rd_empty);

  wire tlast[L];

  wire [U-1:0] tuser[L];

  wire [(N*8)-1:0] tdata[L];

  generate

    for(genvar j = 0; j < L; j++)

    begin: row_gen

      tiny_sync_fifo #(W)

        tiny_sync_fifo_i

        (

          .wr_full(wr_full[j]),

          .wr_data({merge_in[j].tlast, merge_in[j].tuser, merge_in[j].tdata}),

          .wr_en(wr_en[j]),

          .rd_empty(rd_empty[j]),

          .rd_data(rd_data[j]),

          // .rd_en(rd_en[j]),

          .rd_en(rd_en),

          .clk(aclk),

          .reset(~aresetn),

          .*

        );

      assign wr_en[j] = ~init & ~flush & merge_in[j].tready & merge_in[j].tvalid;

      // assign merge_in[j].tready = flush | (init & ~int_done[j]) | (all_valid & all_not_full); // fixme

      assign merge_in[j].tready = (init & ~int_done[j]) | (all_valid & all_not_full);

      assign valid[j] = merge_in[j].tvalid;

      assign {tlast[j], tuser[j], tdata[j]} = rd_data[j];

    end

  endgenerate

  // --------------------------------------------------------------------

  assign axis_out.tvalid = all_not_empty;

  assign axis_out.tdata = {tdata[2], tdata[1], tdata[0]};

  assign axis_out.tlast = tlast[0];

  assign axis_out.tuser[1:0] = tuser[0][1:0];

  assign axis_out.tuser[2] = tuser[0][2];

// --------------------------------------------------------------------

endmodule