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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module
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fifo_to_avf #(AW, AH, D, B=2, T=1, N=B*T)
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(
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input [(N*8)-1:0] tdata,
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input wr_en,
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output wr_full,
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output sof,
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output sol,
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output eol,
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output eof,
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output reg [$clog2(AW)-1:0] n,
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output reg [$clog2(AH)-1:0] m,
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wire error,
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axis_if axis_out,
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input aclk,
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input aresetn
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);
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// --------------------------------------------------------------------
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// synthesis translate_off
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initial
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assert(AW % T == 0) else $fatal;
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// / \
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// | A_00 A_01 .... A_0n |
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// | A_10 A_11 .... A_1n |
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// | .... .... .... .... |
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// | A_m0 A_m1 .... A_mn |
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// \ /
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// --------------------------------------------------------------------
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localparam U = 3;
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localparam W = (N*8) + U + 1; // tdata + tuser + tlast
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// --------------------------------------------------------------------
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// tuser[0] = SOF; tuser[1] = SOL; tlast = EOL; tuser[2] = EOF;
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wire tlast = eol;
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wire [U-1:0] tuser = {eof, sol, sof};
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wire [W-1:0] wr_data = {tlast, tuser, tdata};
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wire rd_empty;
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wire [W-1:0] rd_data;
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wire rd_en;
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wire [$clog2(D):0] count;
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sync_fifo #(W, D) fifo_i(.clk(aclk), .reset(~aresetn), .*);
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// --------------------------------------------------------------------
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wire almost_eol = (n == AW - (2*T));
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always_ff @(posedge aclk)
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if(~aresetn | (wr_en & eol))
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n <= 0;
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else if(wr_en)
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n <= n + T;
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// --------------------------------------------------------------------
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wire last_pixel = (m == AH - 1);
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always_ff @(posedge aclk)
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if(~aresetn | (wr_en & eof))
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m <= 0;
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else if(wr_en & eol)
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m <= m + 1;
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// --------------------------------------------------------------------
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enum reg [2:0]
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{
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SOF = 3'b001,
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LINE = 3'b010,
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EOL = 3'b100
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} prior_state, state, next_state;
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// --------------------------------------------------------------------
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always_ff @(posedge aclk)
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if(~aresetn)
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state <= SOF;
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else
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state <= next_state;
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// --------------------------------------------------------------------
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always_ff @(posedge aclk)
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if(wr_en)
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prior_state <= state;
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// --------------------------------------------------------------------
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always_comb
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case(state)
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SOF: if(wr_en)
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next_state <= LINE;
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else
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next_state <= SOF;
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LINE: if(wr_en & almost_eol)
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next_state <= EOL;
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else
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next_state <= LINE;
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EOL: if(wr_en)
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if(last_pixel) // EOF
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next_state <= SOF;
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else
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next_state <= LINE;
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else
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next_state <= EOL;
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default: next_state <= SOF;
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endcase
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// --------------------------------------------------------------------
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assign error = (wr_en & wr_full);
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assign sof = (state == SOF);
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assign sol = (state == SOF) | ((state == LINE) & (prior_state == EOL));
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assign eof = (state == EOL) & last_pixel;
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assign eol = (state == EOL);
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// --------------------------------------------------------------------
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assign rd_en = axis_out.tvalid & axis_out.tready;
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assign axis_out.tvalid = ~rd_empty;
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assign {axis_out.tlast, axis_out.tuser[U-1:0], axis_out.tdata} = rd_data;
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// --------------------------------------------------------------------
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endmodule
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