OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [video/] [src/] [fifo_to_avf.sv] - Blame information for rev 49

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 49 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
module
29
  fifo_to_avf #(AW, AH, D, B=2, T=1, N=B*T)
30
  (
31
    input [(N*8)-1:0] tdata,
32
    input wr_en,
33
    output wr_full,
34
    output sof,
35
    output sol,
36
    output eol,
37
    output eof,
38
    output reg [$clog2(AW)-1:0] n,
39
    output reg [$clog2(AH)-1:0] m,
40
    wire    error,
41
    axis_if axis_out,
42
    input   aclk,
43
    input   aresetn
44
  );
45
// --------------------------------------------------------------------
46
// synthesis translate_off
47
  initial
48
    assert(AW % T == 0) else $fatal;
49
// synthesis translate_on
50
// --------------------------------------------------------------------
51
 
52
  // --------------------------------------------------------------------
53
  // /                     \
54
  // | A_00 A_01 .... A_0n |
55
  // | A_10 A_11 .... A_1n |
56
  // | .... .... .... .... |
57
  // | A_m0 A_m1 .... A_mn |
58
  // \                     /
59
 
60
  // --------------------------------------------------------------------
61
  localparam U = 3;
62
  localparam W = (N*8) + U + 1; // tdata + tuser + tlast
63
 
64
  // --------------------------------------------------------------------
65
  // tuser[0] = SOF; tuser[1] = SOL; tlast = EOL; tuser[2] = EOF;
66
  wire tlast = eol;
67
  wire [U-1:0] tuser = {eof, sol, sof};
68
  wire [W-1:0] wr_data = {tlast, tuser, tdata};
69
  wire         rd_empty;
70
  wire [W-1:0] rd_data;
71
  wire         rd_en;
72
  wire [$clog2(D):0] count;
73
 
74
  sync_fifo #(W, D) fifo_i(.clk(aclk), .reset(~aresetn), .*);
75
 
76
  // --------------------------------------------------------------------
77
  wire almost_eol = (n == AW - (2*T));
78
 
79
  always_ff @(posedge aclk)
80
    if(~aresetn | (wr_en & eol))
81
      n <= 0;
82
    else if(wr_en)
83
      n <= n + T;
84
 
85
  // --------------------------------------------------------------------
86
  wire last_pixel = (m == AH - 1);
87
 
88
  always_ff @(posedge aclk)
89
    if(~aresetn | (wr_en & eof))
90
      m <= 0;
91
    else if(wr_en & eol)
92
      m <= m + 1;
93
 
94
  // --------------------------------------------------------------------
95
  enum reg [2:0]
96
    {
97
      SOF   = 3'b001,
98
      LINE  = 3'b010,
99
      EOL   = 3'b100
100
    } prior_state, state, next_state;
101
 
102
  // --------------------------------------------------------------------
103
  always_ff @(posedge aclk)
104
    if(~aresetn)
105
      state <= SOF;
106
    else
107
      state <= next_state;
108
 
109
  // --------------------------------------------------------------------
110
  always_ff @(posedge aclk)
111
    if(wr_en)
112
      prior_state <= state;
113
 
114
  // --------------------------------------------------------------------
115
  always_comb
116
    case(state)
117
      SOF:      if(wr_en)
118
                  next_state <= LINE;
119
                else
120
                  next_state <= SOF;
121
 
122
      LINE:     if(wr_en & almost_eol)
123
                  next_state <= EOL;
124
                else
125
                  next_state <= LINE;
126
 
127
      EOL:      if(wr_en)
128
                  if(last_pixel) // EOF
129
                    next_state <= SOF;
130
                  else
131
                    next_state <= LINE;
132
                else
133
                  next_state <= EOL;
134
 
135
      default:  next_state <= SOF;
136
    endcase
137
 
138
  // --------------------------------------------------------------------
139
  assign error = (wr_en & wr_full);
140
  assign sof   = (state == SOF);
141
  assign sol   = (state == SOF) | ((state == LINE) & (prior_state == EOL));
142
  assign eof   = (state == EOL) & last_pixel;
143
  assign eol   = (state == EOL);
144
 
145
  // --------------------------------------------------------------------
146
  assign rd_en = axis_out.tvalid & axis_out.tready;
147
  assign axis_out.tvalid = ~rd_empty;
148
  assign {axis_out.tlast, axis_out.tuser[U-1:0], axis_out.tdata} = rd_data;
149
 
150
// --------------------------------------------------------------------
151
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.