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[/] [qaz_libs/] [trunk/] [zed_board/] [block_diagrams/] [zync_bd_16_2.tcl] - Blame information for rev 27

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Line No. Rev Author Line
1 27 qaztronic
 
2
################################################################
3
# This is a generated script based on design: zync
4
#
5
# Though there are limitations about the generated script,
6
# the main purpose of this utility is to make learning
7
# IP Integrator Tcl commands easier.
8
################################################################
9
 
10
namespace eval _tcl {
11
proc get_script_folder {} {
12
   set script_path [file normalize [info script]]
13
   set script_folder [file dirname $script_path]
14
   return $script_folder
15
}
16
}
17
variable script_folder
18
set script_folder [_tcl::get_script_folder]
19
 
20
################################################################
21
# Check if script is running in correct Vivado version.
22
################################################################
23
set scripts_vivado_version 2016.2
24
set current_vivado_version [version -short]
25
 
26
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
27
   puts ""
28
   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
29
 
30
   return 1
31
}
32
 
33
################################################################
34
# START
35
################################################################
36
 
37
# To test this script, run the following commands from Vivado Tcl console:
38
# source zync_script.tcl
39
 
40
# If there is no project opened, this script will create a
41
# project, but make sure you do not have an existing project
42
# <./myproj/project_1.xpr> in the current working folder.
43
 
44
set list_projs [get_projects -quiet]
45
if { $list_projs eq "" } {
46
   create_project project_1 myproj -part xc7z020clg484-1
47
   set_property BOARD_PART em.avnet.com:zed:part0:1.3 [current_project]
48
}
49
 
50
 
51
# CHANGE DESIGN NAME HERE
52
set design_name zync
53
 
54
# If you do not already have an existing IP Integrator design open,
55
# you can create a design using the following command:
56
#    create_bd_design $design_name
57
 
58
# Creating design if needed
59
set errMsg ""
60
set nRet 0
61
 
62
set cur_design [current_bd_design -quiet]
63
set list_cells [get_bd_cells -quiet]
64
 
65
if { ${design_name} eq "" } {
66
   # USE CASES:
67
   #    1) Design_name not set
68
 
69
   set errMsg "Please set the variable <design_name> to a non-empty value."
70
   set nRet 1
71
 
72
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
73
   # USE CASES:
74
   #    2): Current design opened AND is empty AND names same.
75
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
76
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
77
 
78
   if { $cur_design ne $design_name } {
79
      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
80
      set design_name [get_property NAME $cur_design]
81
   }
82
   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
83
 
84
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
85
   # USE CASES:
86
   #    5) Current design opened AND has components AND same names.
87
 
88
   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
89
   set nRet 1
90
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
91
   # USE CASES: 
92
   #    6) Current opened design, has components, but diff names, design_name exists in project.
93
   #    7) No opened design, design_name exists in project.
94
 
95
   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
96
   set nRet 2
97
 
98
} else {
99
   # USE CASES:
100
   #    8) No opened design, design_name not in project.
101
   #    9) Current opened design, has components, but diff names, design_name not in project.
102
 
103
   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
104
 
105
   create_bd_design $design_name
106
 
107
   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
108
   current_bd_design $design_name
109
 
110
}
111
 
112
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
113
 
114
if { $nRet != 0 } {
115
   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
116
   return $nRet
117
}
118
 
119
##################################################################
120
# DESIGN PROCs
121
##################################################################
122
 
123
 
124
 
125
# Procedure to create entire design; Provide argument to make
126
# procedure reusable. If parentCell is "", will use root.
127
proc create_root_design { parentCell } {
128
 
129
  variable script_folder
130
 
131
  if { $parentCell eq "" } {
132
     set parentCell [get_bd_cells /]
133
  }
134
 
135
  # Get object for parentCell
136
  set parentObj [get_bd_cells $parentCell]
137
  if { $parentObj == "" } {
138
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
139
     return
140
  }
141
 
142
  # Make sure parentObj is hier blk
143
  set parentType [get_property TYPE $parentObj]
144
  if { $parentType ne "hier" } {
145
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
146
     return
147
  }
148
 
149
  # Save current instance; Restore later
150
  set oldCurInst [current_bd_instance .]
151
 
152
  # Set parent object as current
153
  current_bd_instance $parentObj
154
 
155
 
156
  # Create interface ports
157
  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
158
  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
159
  set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
160
  set_property -dict [ list \
161
CONFIG.ADDR_WIDTH {32} \
162
CONFIG.DATA_WIDTH {32} \
163
CONFIG.NUM_READ_OUTSTANDING {8} \
164
CONFIG.NUM_WRITE_OUTSTANDING {8} \
165
CONFIG.PROTOCOL {AXI4LITE} \
166
 ] $M00_AXI
167
 
168
  # Create ports
169
  set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ]
170
  set_property -dict [ list \
171
CONFIG.ASSOCIATED_BUSIF {M00_AXI} \
172
 ] $FCLK_CLK0
173
  set peripheral_aresetn [ create_bd_port -dir O -from 0 -to 0 -type rst peripheral_aresetn ]
174
 
175
  # Create instance: axi_interconnect_0, and set properties
176
  set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
177
  set_property -dict [ list \
178
CONFIG.NUM_MI {1} \
179
 ] $axi_interconnect_0
180
 
181
  # Create instance: proc_sys_reset_0, and set properties
182
  set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
183
 
184
  # Create instance: processing_system7_0, and set properties
185
  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
186
  set_property -dict [ list \
187
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
188
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
189
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
190
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
191
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
192
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
193
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
194
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
195
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
196
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
197
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
198
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
199
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
200
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
201
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} \
202
CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
203
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666667} \
204
CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
205
CONFIG.PCW_CAN0_CAN0_IO {<Select>} \
206
CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
207
CONFIG.PCW_CAN0_GRP_CLK_IO {<Select>} \
208
CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
209
CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
210
CONFIG.PCW_CAN1_CAN1_IO {<Select>} \
211
CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
212
CONFIG.PCW_CAN1_GRP_CLK_IO {<Select>} \
213
CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
214
CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
215
CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
216
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
217
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
218
CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
219
CONFIG.PCW_CLK0_FREQ {100000000} \
220
CONFIG.PCW_CLK1_FREQ {10000000} \
221
CONFIG.PCW_CLK2_FREQ {10000000} \
222
CONFIG.PCW_CLK3_FREQ {10000000} \
223
CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
224
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
225
CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
226
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
227
CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
228
CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
229
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
230
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
231
CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
232
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
233
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
234
CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
235
CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
236
CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
237
CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
238
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
239
CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
240
CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
241
CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
242
CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
243
CONFIG.PCW_DDR_PRIORITY_READPORT_0 {<Select>} \
244
CONFIG.PCW_DDR_PRIORITY_READPORT_1 {<Select>} \
245
CONFIG.PCW_DDR_PRIORITY_READPORT_2 {<Select>} \
246
CONFIG.PCW_DDR_PRIORITY_READPORT_3 {<Select>} \
247
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {<Select>} \
248
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1 {<Select>} \
249
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {<Select>} \
250
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3 {<Select>} \
251
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
252
CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
253
CONFIG.PCW_ENET0_ENET0_IO {<Select>} \
254
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \
255
CONFIG.PCW_ENET0_GRP_MDIO_IO {<Select>} \
256
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
257
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
258
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
259
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \
260
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
261
CONFIG.PCW_ENET0_RESET_ENABLE {0} \
262
CONFIG.PCW_ENET0_RESET_IO {<Select>} \
263
CONFIG.PCW_ENET1_ENET1_IO {<Select>} \
264
CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
265
CONFIG.PCW_ENET1_GRP_MDIO_IO {<Select>} \
266
CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
267
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
268
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
269
CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
270
CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
271
CONFIG.PCW_ENET1_RESET_ENABLE {0} \
272
CONFIG.PCW_ENET1_RESET_IO {<Select>} \
273
CONFIG.PCW_ENET_RESET_ENABLE {0} \
274
CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
275
CONFIG.PCW_ENET_RESET_SELECT {<Select>} \
276
CONFIG.PCW_EN_4K_TIMER {0} \
277
CONFIG.PCW_EN_EMIO_TTC0 {1} \
278
CONFIG.PCW_EN_PTP_ENET0 {1} \
279
CONFIG.PCW_EN_QSPI {1} \
280
CONFIG.PCW_EN_SDIO0 {1} \
281
CONFIG.PCW_EN_TTC0 {1} \
282
CONFIG.PCW_EN_UART1 {1} \
283
CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
284
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {4} \
285
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
286
CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
287
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
288
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
289
CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
290
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
291
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
292
CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
293
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
294
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
295
CONFIG.PCW_FCLK_CLK0_BUF {true} \
296
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
297
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {150.000000} \
298
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50.000000} \
299
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
300
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
301
CONFIG.PCW_FTM_CTI_IN0 {<Select>} \
302
CONFIG.PCW_FTM_CTI_IN1 {<Select>} \
303
CONFIG.PCW_FTM_CTI_IN2 {<Select>} \
304
CONFIG.PCW_FTM_CTI_IN3 {<Select>} \
305
CONFIG.PCW_FTM_CTI_OUT0 {<Select>} \
306
CONFIG.PCW_FTM_CTI_OUT1 {<Select>} \
307
CONFIG.PCW_FTM_CTI_OUT2 {<Select>} \
308
CONFIG.PCW_FTM_CTI_OUT3 {<Select>} \
309
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
310
CONFIG.PCW_GPIO_EMIO_GPIO_IO {<Select>} \
311
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
312
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
313
CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
314
CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
315
CONFIG.PCW_I2C0_GRP_INT_IO {<Select>} \
316
CONFIG.PCW_I2C0_I2C0_IO {<Select>} \
317
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \
318
CONFIG.PCW_I2C0_RESET_ENABLE {0} \
319
CONFIG.PCW_I2C0_RESET_IO {<Select>} \
320
CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
321
CONFIG.PCW_I2C1_GRP_INT_IO {<Select>} \
322
CONFIG.PCW_I2C1_I2C1_IO {<Select>} \
323
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
324
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
325
CONFIG.PCW_I2C1_RESET_IO {<Select>} \
326
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
327
CONFIG.PCW_I2C_RESET_ENABLE {1} \
328
CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
329
CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
330
CONFIG.PCW_IOPLL_CTRL_FBDIV {48} \
331
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1600.000} \
332
CONFIG.PCW_MIO_0_DIRECTION {inout} \
333
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
334
CONFIG.PCW_MIO_0_PULLUP {disabled} \
335
CONFIG.PCW_MIO_0_SLEW {slow} \
336
CONFIG.PCW_MIO_10_DIRECTION {inout} \
337
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
338
CONFIG.PCW_MIO_10_PULLUP {disabled} \
339
CONFIG.PCW_MIO_10_SLEW {slow} \
340
CONFIG.PCW_MIO_11_DIRECTION {inout} \
341
CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
342
CONFIG.PCW_MIO_11_PULLUP {disabled} \
343
CONFIG.PCW_MIO_11_SLEW {slow} \
344
CONFIG.PCW_MIO_12_DIRECTION {inout} \
345
CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
346
CONFIG.PCW_MIO_12_PULLUP {disabled} \
347
CONFIG.PCW_MIO_12_SLEW {slow} \
348
CONFIG.PCW_MIO_13_DIRECTION {inout} \
349
CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
350
CONFIG.PCW_MIO_13_PULLUP {disabled} \
351
CONFIG.PCW_MIO_13_SLEW {slow} \
352
CONFIG.PCW_MIO_14_DIRECTION {inout} \
353
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
354
CONFIG.PCW_MIO_14_PULLUP {disabled} \
355
CONFIG.PCW_MIO_14_SLEW {slow} \
356
CONFIG.PCW_MIO_15_DIRECTION {inout} \
357
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
358
CONFIG.PCW_MIO_15_PULLUP {disabled} \
359
CONFIG.PCW_MIO_15_SLEW {slow} \
360
CONFIG.PCW_MIO_16_DIRECTION {inout} \
361
CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
362
CONFIG.PCW_MIO_16_PULLUP {disabled} \
363
CONFIG.PCW_MIO_16_SLEW {fast} \
364
CONFIG.PCW_MIO_17_DIRECTION {inout} \
365
CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
366
CONFIG.PCW_MIO_17_PULLUP {disabled} \
367
CONFIG.PCW_MIO_17_SLEW {fast} \
368
CONFIG.PCW_MIO_18_DIRECTION {inout} \
369
CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
370
CONFIG.PCW_MIO_18_PULLUP {disabled} \
371
CONFIG.PCW_MIO_18_SLEW {fast} \
372
CONFIG.PCW_MIO_19_DIRECTION {inout} \
373
CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
374
CONFIG.PCW_MIO_19_PULLUP {disabled} \
375
CONFIG.PCW_MIO_19_SLEW {fast} \
376
CONFIG.PCW_MIO_1_DIRECTION {out} \
377
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
378
CONFIG.PCW_MIO_1_PULLUP {disabled} \
379
CONFIG.PCW_MIO_1_SLEW {fast} \
380
CONFIG.PCW_MIO_20_DIRECTION {inout} \
381
CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
382
CONFIG.PCW_MIO_20_PULLUP {disabled} \
383
CONFIG.PCW_MIO_20_SLEW {fast} \
384
CONFIG.PCW_MIO_21_DIRECTION {inout} \
385
CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
386
CONFIG.PCW_MIO_21_PULLUP {disabled} \
387
CONFIG.PCW_MIO_21_SLEW {fast} \
388
CONFIG.PCW_MIO_22_DIRECTION {inout} \
389
CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
390
CONFIG.PCW_MIO_22_PULLUP {disabled} \
391
CONFIG.PCW_MIO_22_SLEW {fast} \
392
CONFIG.PCW_MIO_23_DIRECTION {inout} \
393
CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
394
CONFIG.PCW_MIO_23_PULLUP {disabled} \
395
CONFIG.PCW_MIO_23_SLEW {fast} \
396
CONFIG.PCW_MIO_24_DIRECTION {inout} \
397
CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
398
CONFIG.PCW_MIO_24_PULLUP {disabled} \
399
CONFIG.PCW_MIO_24_SLEW {fast} \
400
CONFIG.PCW_MIO_25_DIRECTION {inout} \
401
CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
402
CONFIG.PCW_MIO_25_PULLUP {disabled} \
403
CONFIG.PCW_MIO_25_SLEW {fast} \
404
CONFIG.PCW_MIO_26_DIRECTION {inout} \
405
CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
406
CONFIG.PCW_MIO_26_PULLUP {disabled} \
407
CONFIG.PCW_MIO_26_SLEW {fast} \
408
CONFIG.PCW_MIO_27_DIRECTION {inout} \
409
CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
410
CONFIG.PCW_MIO_27_PULLUP {disabled} \
411
CONFIG.PCW_MIO_27_SLEW {fast} \
412
CONFIG.PCW_MIO_28_DIRECTION {inout} \
413
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
414
CONFIG.PCW_MIO_28_PULLUP {disabled} \
415
CONFIG.PCW_MIO_28_SLEW {fast} \
416
CONFIG.PCW_MIO_29_DIRECTION {inout} \
417
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
418
CONFIG.PCW_MIO_29_PULLUP {disabled} \
419
CONFIG.PCW_MIO_29_SLEW {fast} \
420
CONFIG.PCW_MIO_2_DIRECTION {inout} \
421
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
422
CONFIG.PCW_MIO_2_PULLUP {disabled} \
423
CONFIG.PCW_MIO_2_SLEW {fast} \
424
CONFIG.PCW_MIO_30_DIRECTION {inout} \
425
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
426
CONFIG.PCW_MIO_30_PULLUP {disabled} \
427
CONFIG.PCW_MIO_30_SLEW {fast} \
428
CONFIG.PCW_MIO_31_DIRECTION {inout} \
429
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
430
CONFIG.PCW_MIO_31_PULLUP {disabled} \
431
CONFIG.PCW_MIO_31_SLEW {fast} \
432
CONFIG.PCW_MIO_32_DIRECTION {inout} \
433
CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
434
CONFIG.PCW_MIO_32_PULLUP {disabled} \
435
CONFIG.PCW_MIO_32_SLEW {fast} \
436
CONFIG.PCW_MIO_33_DIRECTION {inout} \
437
CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
438
CONFIG.PCW_MIO_33_PULLUP {disabled} \
439
CONFIG.PCW_MIO_33_SLEW {fast} \
440
CONFIG.PCW_MIO_34_DIRECTION {inout} \
441
CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
442
CONFIG.PCW_MIO_34_PULLUP {disabled} \
443
CONFIG.PCW_MIO_34_SLEW {fast} \
444
CONFIG.PCW_MIO_35_DIRECTION {inout} \
445
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
446
CONFIG.PCW_MIO_35_PULLUP {disabled} \
447
CONFIG.PCW_MIO_35_SLEW {fast} \
448
CONFIG.PCW_MIO_36_DIRECTION {inout} \
449
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
450
CONFIG.PCW_MIO_36_PULLUP {disabled} \
451
CONFIG.PCW_MIO_36_SLEW {fast} \
452
CONFIG.PCW_MIO_37_DIRECTION {inout} \
453
CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
454
CONFIG.PCW_MIO_37_PULLUP {disabled} \
455
CONFIG.PCW_MIO_37_SLEW {fast} \
456
CONFIG.PCW_MIO_38_DIRECTION {inout} \
457
CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
458
CONFIG.PCW_MIO_38_PULLUP {disabled} \
459
CONFIG.PCW_MIO_38_SLEW {fast} \
460
CONFIG.PCW_MIO_39_DIRECTION {inout} \
461
CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
462
CONFIG.PCW_MIO_39_PULLUP {disabled} \
463
CONFIG.PCW_MIO_39_SLEW {fast} \
464
CONFIG.PCW_MIO_3_DIRECTION {inout} \
465
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
466
CONFIG.PCW_MIO_3_PULLUP {disabled} \
467
CONFIG.PCW_MIO_3_SLEW {fast} \
468
CONFIG.PCW_MIO_40_DIRECTION {inout} \
469
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
470
CONFIG.PCW_MIO_40_PULLUP {disabled} \
471
CONFIG.PCW_MIO_40_SLEW {fast} \
472
CONFIG.PCW_MIO_41_DIRECTION {inout} \
473
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
474
CONFIG.PCW_MIO_41_PULLUP {disabled} \
475
CONFIG.PCW_MIO_41_SLEW {fast} \
476
CONFIG.PCW_MIO_42_DIRECTION {inout} \
477
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
478
CONFIG.PCW_MIO_42_PULLUP {disabled} \
479
CONFIG.PCW_MIO_42_SLEW {fast} \
480
CONFIG.PCW_MIO_43_DIRECTION {inout} \
481
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
482
CONFIG.PCW_MIO_43_PULLUP {disabled} \
483
CONFIG.PCW_MIO_43_SLEW {fast} \
484
CONFIG.PCW_MIO_44_DIRECTION {inout} \
485
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
486
CONFIG.PCW_MIO_44_PULLUP {disabled} \
487
CONFIG.PCW_MIO_44_SLEW {fast} \
488
CONFIG.PCW_MIO_45_DIRECTION {inout} \
489
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
490
CONFIG.PCW_MIO_45_PULLUP {disabled} \
491
CONFIG.PCW_MIO_45_SLEW {fast} \
492
CONFIG.PCW_MIO_46_DIRECTION {in} \
493
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
494
CONFIG.PCW_MIO_46_PULLUP {disabled} \
495
CONFIG.PCW_MIO_46_SLEW {slow} \
496
CONFIG.PCW_MIO_47_DIRECTION {in} \
497
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
498
CONFIG.PCW_MIO_47_PULLUP {disabled} \
499
CONFIG.PCW_MIO_47_SLEW {slow} \
500
CONFIG.PCW_MIO_48_DIRECTION {out} \
501
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
502
CONFIG.PCW_MIO_48_PULLUP {disabled} \
503
CONFIG.PCW_MIO_48_SLEW {slow} \
504
CONFIG.PCW_MIO_49_DIRECTION {in} \
505
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
506
CONFIG.PCW_MIO_49_PULLUP {disabled} \
507
CONFIG.PCW_MIO_49_SLEW {slow} \
508
CONFIG.PCW_MIO_4_DIRECTION {inout} \
509
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
510
CONFIG.PCW_MIO_4_PULLUP {disabled} \
511
CONFIG.PCW_MIO_4_SLEW {fast} \
512
CONFIG.PCW_MIO_50_DIRECTION {inout} \
513
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
514
CONFIG.PCW_MIO_50_PULLUP {disabled} \
515
CONFIG.PCW_MIO_50_SLEW {slow} \
516
CONFIG.PCW_MIO_51_DIRECTION {inout} \
517
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
518
CONFIG.PCW_MIO_51_PULLUP {disabled} \
519
CONFIG.PCW_MIO_51_SLEW {slow} \
520
CONFIG.PCW_MIO_52_DIRECTION {inout} \
521
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
522
CONFIG.PCW_MIO_52_PULLUP {disabled} \
523
CONFIG.PCW_MIO_52_SLEW {slow} \
524
CONFIG.PCW_MIO_53_DIRECTION {inout} \
525
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
526
CONFIG.PCW_MIO_53_PULLUP {disabled} \
527
CONFIG.PCW_MIO_53_SLEW {slow} \
528
CONFIG.PCW_MIO_5_DIRECTION {inout} \
529
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
530
CONFIG.PCW_MIO_5_PULLUP {disabled} \
531
CONFIG.PCW_MIO_5_SLEW {fast} \
532
CONFIG.PCW_MIO_6_DIRECTION {out} \
533
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
534
CONFIG.PCW_MIO_6_PULLUP {disabled} \
535
CONFIG.PCW_MIO_6_SLEW {fast} \
536
CONFIG.PCW_MIO_7_DIRECTION {out} \
537
CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
538
CONFIG.PCW_MIO_7_PULLUP {disabled} \
539
CONFIG.PCW_MIO_7_SLEW {slow} \
540
CONFIG.PCW_MIO_8_DIRECTION {out} \
541
CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
542
CONFIG.PCW_MIO_8_PULLUP {disabled} \
543
CONFIG.PCW_MIO_8_SLEW {fast} \
544
CONFIG.PCW_MIO_9_DIRECTION {inout} \
545
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
546
CONFIG.PCW_MIO_9_PULLUP {disabled} \
547
CONFIG.PCW_MIO_9_SLEW {slow} \
548
CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 1#UART 1#GPIO#GPIO#GPIO#GPIO} \
549
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#gpio[16]#gpio[17]#gpio[18]#gpio[19]#gpio[20]#gpio[21]#gpio[22]#gpio[23]#gpio[24]#gpio[25]#gpio[26]#gpio[27]#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#clk#cmd#data[0]#data[1]#data[2]#data[3]#wp#cd#tx#rx#gpio[50]#gpio[51]#gpio[52]#gpio[53]} \
550
CONFIG.PCW_NAND_CYCLES_T_AR {1} \
551
CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
552
CONFIG.PCW_NAND_CYCLES_T_RC {2} \
553
CONFIG.PCW_NAND_CYCLES_T_REA {1} \
554
CONFIG.PCW_NAND_CYCLES_T_RR {1} \
555
CONFIG.PCW_NAND_CYCLES_T_WC {2} \
556
CONFIG.PCW_NAND_CYCLES_T_WP {1} \
557
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
558
CONFIG.PCW_NAND_GRP_D8_IO {<Select>} \
559
CONFIG.PCW_NAND_NAND_IO {<Select>} \
560
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
561
CONFIG.PCW_NOR_CS0_T_CEOE {1} \
562
CONFIG.PCW_NOR_CS0_T_PC {1} \
563
CONFIG.PCW_NOR_CS0_T_RC {2} \
564
CONFIG.PCW_NOR_CS0_T_TR {1} \
565
CONFIG.PCW_NOR_CS0_T_WC {2} \
566
CONFIG.PCW_NOR_CS0_T_WP {1} \
567
CONFIG.PCW_NOR_CS0_WE_TIME {0} \
568
CONFIG.PCW_NOR_CS1_T_CEOE {1} \
569
CONFIG.PCW_NOR_CS1_T_PC {1} \
570
CONFIG.PCW_NOR_CS1_T_RC {2} \
571
CONFIG.PCW_NOR_CS1_T_TR {1} \
572
CONFIG.PCW_NOR_CS1_T_WC {2} \
573
CONFIG.PCW_NOR_CS1_T_WP {1} \
574
CONFIG.PCW_NOR_CS1_WE_TIME {0} \
575
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
576
CONFIG.PCW_NOR_GRP_A25_IO {<Select>} \
577
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
578
CONFIG.PCW_NOR_GRP_CS0_IO {<Select>} \
579
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
580
CONFIG.PCW_NOR_GRP_CS1_IO {<Select>} \
581
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
582
CONFIG.PCW_NOR_GRP_SRAM_CS0_IO {<Select>} \
583
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
584
CONFIG.PCW_NOR_GRP_SRAM_CS1_IO {<Select>} \
585
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
586
CONFIG.PCW_NOR_GRP_SRAM_INT_IO {<Select>} \
587
CONFIG.PCW_NOR_NOR_IO {<Select>} \
588
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
589
CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
590
CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
591
CONFIG.PCW_NOR_SRAM_CS0_T_RC {2} \
592
CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
593
CONFIG.PCW_NOR_SRAM_CS0_T_WC {2} \
594
CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
595
CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
596
CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
597
CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
598
CONFIG.PCW_NOR_SRAM_CS1_T_RC {2} \
599
CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
600
CONFIG.PCW_NOR_SRAM_CS1_T_WC {2} \
601
CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
602
CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
603
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.063} \
604
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.062} \
605
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.065} \
606
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.083} \
607
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.007} \
608
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.010} \
609
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.006} \
610
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.048} \
611
CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
612
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {8} \
613
CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
614
CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \
615
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
616
CONFIG.PCW_PJTAG_PJTAG_IO {<Select>} \
617
CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
618
CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
619
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
620
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
621
CONFIG.PCW_QSPI_GRP_FBCLK_IO {<Select>} \
622
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
623
CONFIG.PCW_QSPI_GRP_IO1_IO {<Select>} \
624
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
625
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
626
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
627
CONFIG.PCW_QSPI_GRP_SS1_IO {<Select>} \
628
CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
629
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {8} \
630
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
631
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
632
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
633
CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
634
CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
635
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
636
CONFIG.PCW_SD0_GRP_POW_IO {<Select>} \
637
CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \
638
CONFIG.PCW_SD0_GRP_WP_IO {MIO 46} \
639
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
640
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
641
CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
642
CONFIG.PCW_SD1_GRP_CD_IO {<Select>} \
643
CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
644
CONFIG.PCW_SD1_GRP_POW_IO {<Select>} \
645
CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
646
CONFIG.PCW_SD1_GRP_WP_IO {<Select>} \
647
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
648
CONFIG.PCW_SD1_SD1_IO {<Select>} \
649
CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
650
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {32} \
651
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
652
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
653
CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
654
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
655
CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
656
CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
657
CONFIG.PCW_SPI0_GRP_SS0_IO {<Select>} \
658
CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
659
CONFIG.PCW_SPI0_GRP_SS1_IO {<Select>} \
660
CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
661
CONFIG.PCW_SPI0_GRP_SS2_IO {<Select>} \
662
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
663
CONFIG.PCW_SPI0_SPI0_IO {<Select>} \
664
CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
665
CONFIG.PCW_SPI1_GRP_SS0_IO {<Select>} \
666
CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
667
CONFIG.PCW_SPI1_GRP_SS1_IO {<Select>} \
668
CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
669
CONFIG.PCW_SPI1_GRP_SS2_IO {<Select>} \
670
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
671
CONFIG.PCW_SPI1_SPI1_IO {<Select>} \
672
CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
673
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
674
CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
675
CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
676
CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
677
CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
678
CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
679
CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
680
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
681
CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
682
CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \
683
CONFIG.PCW_TRACE_GRP_16BIT_IO {<Select>} \
684
CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \
685
CONFIG.PCW_TRACE_GRP_2BIT_IO {<Select>} \
686
CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \
687
CONFIG.PCW_TRACE_GRP_32BIT_IO {<Select>} \
688
CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \
689
CONFIG.PCW_TRACE_GRP_4BIT_IO {<Select>} \
690
CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \
691
CONFIG.PCW_TRACE_GRP_8BIT_IO {<Select>} \
692
CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
693
CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
694
CONFIG.PCW_TRACE_TRACE_IO {<Select>} \
695
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
696
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
697
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
698
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
699
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
700
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
701
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
702
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
703
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
704
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
705
CONFIG.PCW_TTC0_TTC0_IO {EMIO} \
706
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
707
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
708
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
709
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
710
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
711
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
712
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
713
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
714
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
715
CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
716
CONFIG.PCW_TTC1_TTC1_IO {<Select>} \
717
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
718
CONFIG.PCW_UART0_BAUD_RATE {115200} \
719
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
720
CONFIG.PCW_UART0_GRP_FULL_IO {<Select>} \
721
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \
722
CONFIG.PCW_UART0_UART0_IO {<Select>} \
723
CONFIG.PCW_UART1_BAUD_RATE {115200} \
724
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
725
CONFIG.PCW_UART1_GRP_FULL_IO {<Select>} \
726
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
727
CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
728
CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
729
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {32} \
730
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} \
731
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
732
CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
733
CONFIG.PCW_UIPARAM_DDR_AL {0} \
734
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
735
CONFIG.PCW_UIPARAM_DDR_BL {8} \
736
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.41} \
737
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.411} \
738
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.341} \
739
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.358} \
740
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
741
CONFIG.PCW_UIPARAM_DDR_CL {7} \
742
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
743
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {61.0905} \
744
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
745
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \
746
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {61.0905} \
747
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
748
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
749
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {61.0905} \
750
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
751
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
752
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {61.0905} \
753
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
754
CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
755
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
756
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
757
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \
758
CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
759
CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {68.4725} \
760
CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
761
CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \
762
CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {71.086} \
763
CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
764
CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
765
CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {66.794} \
766
CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
767
CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
768
CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {108.7385} \
769
CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
770
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.025} \
771
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.028} \
772
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
773
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.061} \
774
CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \
775
CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {64.1705} \
776
CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
777
CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \
778
CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {63.686} \
779
CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
780
CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
781
CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {68.46} \
782
CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
783
CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
784
CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {105.4895} \
785
CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
786
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
787
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
788
CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
789
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333313} \
790
CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
791
CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
792
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} \
793
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} \
794
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
795
CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
796
CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
797
CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
798
CONFIG.PCW_UIPARAM_DDR_T_FAW {45.0} \
799
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} \
800
CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} \
801
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
802
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
803
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \
804
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
805
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
806
CONFIG.PCW_USB0_RESET_ENABLE {0} \
807
CONFIG.PCW_USB0_RESET_IO {<Select>} \
808
CONFIG.PCW_USB0_USB0_IO {<Select>} \
809
CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
810
CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
811
CONFIG.PCW_USB1_RESET_ENABLE {0} \
812
CONFIG.PCW_USB1_RESET_IO {<Select>} \
813
CONFIG.PCW_USB1_USB1_IO {<Select>} \
814
CONFIG.PCW_USB_RESET_ENABLE {1} \
815
CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
816
CONFIG.PCW_USB_RESET_SELECT {<Select>} \
817
CONFIG.PCW_USE_CROSS_TRIGGER {0} \
818
CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
819
CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
820
CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
821
CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
822
CONFIG.PCW_WDT_WDT_IO {<Select>} \
823
CONFIG.preset {ZedBoard} \
824
 ] $processing_system7_0
825
 
826
  # Need to retain value_src of defaults
827
  set_property -dict [ list \
828
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
829
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
830
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
831
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
832
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
833
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
834
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
835
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
836
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
837
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
838
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
839
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
840
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
841
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
842
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
843
CONFIG.PCW_APU_CLK_RATIO_ENABLE.VALUE_SRC {DEFAULT} \
844
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
845
CONFIG.PCW_ARMPLL_CTRL_FBDIV.VALUE_SRC {DEFAULT} \
846
CONFIG.PCW_CAN0_CAN0_IO.VALUE_SRC {DEFAULT} \
847
CONFIG.PCW_CAN0_GRP_CLK_ENABLE.VALUE_SRC {DEFAULT} \
848
CONFIG.PCW_CAN0_GRP_CLK_IO.VALUE_SRC {DEFAULT} \
849
CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
850
CONFIG.PCW_CAN0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
851
CONFIG.PCW_CAN1_CAN1_IO.VALUE_SRC {DEFAULT} \
852
CONFIG.PCW_CAN1_GRP_CLK_ENABLE.VALUE_SRC {DEFAULT} \
853
CONFIG.PCW_CAN1_GRP_CLK_IO.VALUE_SRC {DEFAULT} \
854
CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
855
CONFIG.PCW_CAN1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
856
CONFIG.PCW_CAN_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
857
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
858
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \
859
CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
860
CONFIG.PCW_CLK0_FREQ.VALUE_SRC {DEFAULT} \
861
CONFIG.PCW_CLK1_FREQ.VALUE_SRC {DEFAULT} \
862
CONFIG.PCW_CLK2_FREQ.VALUE_SRC {DEFAULT} \
863
CONFIG.PCW_CLK3_FREQ.VALUE_SRC {DEFAULT} \
864
CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE.VALUE_SRC {DEFAULT} \
865
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ.VALUE_SRC {DEFAULT} \
866
CONFIG.PCW_CPU_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
867
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
868
CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
869
CONFIG.PCW_DCI_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
870
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
871
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \
872
CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
873
CONFIG.PCW_DDRPLL_CTRL_FBDIV.VALUE_SRC {DEFAULT} \
874
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ.VALUE_SRC {DEFAULT} \
875
CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION.VALUE_SRC {DEFAULT} \
876
CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL.VALUE_SRC {DEFAULT} \
877
CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL.VALUE_SRC {DEFAULT} \
878
CONFIG.PCW_DDR_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
879
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
880
CONFIG.PCW_DDR_PORT0_HPR_ENABLE.VALUE_SRC {DEFAULT} \
881
CONFIG.PCW_DDR_PORT1_HPR_ENABLE.VALUE_SRC {DEFAULT} \
882
CONFIG.PCW_DDR_PORT2_HPR_ENABLE.VALUE_SRC {DEFAULT} \
883
CONFIG.PCW_DDR_PORT3_HPR_ENABLE.VALUE_SRC {DEFAULT} \
884
CONFIG.PCW_DDR_PRIORITY_READPORT_0.VALUE_SRC {DEFAULT} \
885
CONFIG.PCW_DDR_PRIORITY_READPORT_1.VALUE_SRC {DEFAULT} \
886
CONFIG.PCW_DDR_PRIORITY_READPORT_2.VALUE_SRC {DEFAULT} \
887
CONFIG.PCW_DDR_PRIORITY_READPORT_3.VALUE_SRC {DEFAULT} \
888
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0.VALUE_SRC {DEFAULT} \
889
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1.VALUE_SRC {DEFAULT} \
890
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2.VALUE_SRC {DEFAULT} \
891
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3.VALUE_SRC {DEFAULT} \
892
CONFIG.PCW_DDR_RAM_HIGHADDR.VALUE_SRC {DEFAULT} \
893
CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL.VALUE_SRC {DEFAULT} \
894
CONFIG.PCW_ENET0_ENET0_IO.VALUE_SRC {DEFAULT} \
895
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE.VALUE_SRC {DEFAULT} \
896
CONFIG.PCW_ENET0_GRP_MDIO_IO.VALUE_SRC {DEFAULT} \
897
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
898
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
899
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \
900
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
901
CONFIG.PCW_ENET0_RESET_ENABLE.VALUE_SRC {DEFAULT} \
902
CONFIG.PCW_ENET0_RESET_IO.VALUE_SRC {DEFAULT} \
903
CONFIG.PCW_ENET1_ENET1_IO.VALUE_SRC {DEFAULT} \
904
CONFIG.PCW_ENET1_GRP_MDIO_ENABLE.VALUE_SRC {DEFAULT} \
905
CONFIG.PCW_ENET1_GRP_MDIO_IO.VALUE_SRC {DEFAULT} \
906
CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
907
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
908
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \
909
CONFIG.PCW_ENET1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
910
CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
911
CONFIG.PCW_ENET1_RESET_ENABLE.VALUE_SRC {DEFAULT} \
912
CONFIG.PCW_ENET1_RESET_IO.VALUE_SRC {DEFAULT} \
913
CONFIG.PCW_ENET_RESET_ENABLE.VALUE_SRC {DEFAULT} \
914
CONFIG.PCW_ENET_RESET_POLARITY.VALUE_SRC {DEFAULT} \
915
CONFIG.PCW_ENET_RESET_SELECT.VALUE_SRC {DEFAULT} \
916
CONFIG.PCW_EN_4K_TIMER.VALUE_SRC {DEFAULT} \
917
CONFIG.PCW_EN_EMIO_TTC0.VALUE_SRC {DEFAULT} \
918
CONFIG.PCW_EN_PTP_ENET0.VALUE_SRC {DEFAULT} \
919
CONFIG.PCW_EN_QSPI.VALUE_SRC {DEFAULT} \
920
CONFIG.PCW_EN_SDIO0.VALUE_SRC {DEFAULT} \
921
CONFIG.PCW_EN_TTC0.VALUE_SRC {DEFAULT} \
922
CONFIG.PCW_EN_UART1.VALUE_SRC {DEFAULT} \
923
CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
924
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
925
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \
926
CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
927
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
928
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \
929
CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
930
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
931
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \
932
CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
933
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
934
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \
935
CONFIG.PCW_FCLK_CLK0_BUF.VALUE_SRC {DEFAULT} \
936
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
937
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
938
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
939
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
940
CONFIG.PCW_FPGA_FCLK0_ENABLE.VALUE_SRC {DEFAULT} \
941
CONFIG.PCW_FTM_CTI_IN0.VALUE_SRC {DEFAULT} \
942
CONFIG.PCW_FTM_CTI_IN1.VALUE_SRC {DEFAULT} \
943
CONFIG.PCW_FTM_CTI_IN2.VALUE_SRC {DEFAULT} \
944
CONFIG.PCW_FTM_CTI_IN3.VALUE_SRC {DEFAULT} \
945
CONFIG.PCW_FTM_CTI_OUT0.VALUE_SRC {DEFAULT} \
946
CONFIG.PCW_FTM_CTI_OUT1.VALUE_SRC {DEFAULT} \
947
CONFIG.PCW_FTM_CTI_OUT2.VALUE_SRC {DEFAULT} \
948
CONFIG.PCW_FTM_CTI_OUT3.VALUE_SRC {DEFAULT} \
949
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE.VALUE_SRC {DEFAULT} \
950
CONFIG.PCW_GPIO_EMIO_GPIO_IO.VALUE_SRC {DEFAULT} \
951
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE.VALUE_SRC {DEFAULT} \
952
CONFIG.PCW_GPIO_MIO_GPIO_IO.VALUE_SRC {DEFAULT} \
953
CONFIG.PCW_GPIO_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
954
CONFIG.PCW_I2C0_GRP_INT_ENABLE.VALUE_SRC {DEFAULT} \
955
CONFIG.PCW_I2C0_GRP_INT_IO.VALUE_SRC {DEFAULT} \
956
CONFIG.PCW_I2C0_I2C0_IO.VALUE_SRC {DEFAULT} \
957
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
958
CONFIG.PCW_I2C0_RESET_ENABLE.VALUE_SRC {DEFAULT} \
959
CONFIG.PCW_I2C0_RESET_IO.VALUE_SRC {DEFAULT} \
960
CONFIG.PCW_I2C1_GRP_INT_ENABLE.VALUE_SRC {DEFAULT} \
961
CONFIG.PCW_I2C1_GRP_INT_IO.VALUE_SRC {DEFAULT} \
962
CONFIG.PCW_I2C1_I2C1_IO.VALUE_SRC {DEFAULT} \
963
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
964
CONFIG.PCW_I2C1_RESET_ENABLE.VALUE_SRC {DEFAULT} \
965
CONFIG.PCW_I2C1_RESET_IO.VALUE_SRC {DEFAULT} \
966
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
967
CONFIG.PCW_I2C_RESET_ENABLE.VALUE_SRC {DEFAULT} \
968
CONFIG.PCW_I2C_RESET_POLARITY.VALUE_SRC {DEFAULT} \
969
CONFIG.PCW_I2C_RESET_SELECT.VALUE_SRC {DEFAULT} \
970
CONFIG.PCW_IOPLL_CTRL_FBDIV.VALUE_SRC {DEFAULT} \
971
CONFIG.PCW_IO_IO_PLL_FREQMHZ.VALUE_SRC {DEFAULT} \
972
CONFIG.PCW_MIO_0_DIRECTION.VALUE_SRC {DEFAULT} \
973
CONFIG.PCW_MIO_0_IOTYPE.VALUE_SRC {DEFAULT} \
974
CONFIG.PCW_MIO_0_PULLUP.VALUE_SRC {DEFAULT} \
975
CONFIG.PCW_MIO_0_SLEW.VALUE_SRC {DEFAULT} \
976
CONFIG.PCW_MIO_10_DIRECTION.VALUE_SRC {DEFAULT} \
977
CONFIG.PCW_MIO_10_IOTYPE.VALUE_SRC {DEFAULT} \
978
CONFIG.PCW_MIO_10_PULLUP.VALUE_SRC {DEFAULT} \
979
CONFIG.PCW_MIO_10_SLEW.VALUE_SRC {DEFAULT} \
980
CONFIG.PCW_MIO_11_DIRECTION.VALUE_SRC {DEFAULT} \
981
CONFIG.PCW_MIO_11_IOTYPE.VALUE_SRC {DEFAULT} \
982
CONFIG.PCW_MIO_11_PULLUP.VALUE_SRC {DEFAULT} \
983
CONFIG.PCW_MIO_11_SLEW.VALUE_SRC {DEFAULT} \
984
CONFIG.PCW_MIO_12_DIRECTION.VALUE_SRC {DEFAULT} \
985
CONFIG.PCW_MIO_12_IOTYPE.VALUE_SRC {DEFAULT} \
986
CONFIG.PCW_MIO_12_PULLUP.VALUE_SRC {DEFAULT} \
987
CONFIG.PCW_MIO_12_SLEW.VALUE_SRC {DEFAULT} \
988
CONFIG.PCW_MIO_13_DIRECTION.VALUE_SRC {DEFAULT} \
989
CONFIG.PCW_MIO_13_IOTYPE.VALUE_SRC {DEFAULT} \
990
CONFIG.PCW_MIO_13_PULLUP.VALUE_SRC {DEFAULT} \
991
CONFIG.PCW_MIO_13_SLEW.VALUE_SRC {DEFAULT} \
992
CONFIG.PCW_MIO_14_DIRECTION.VALUE_SRC {DEFAULT} \
993
CONFIG.PCW_MIO_14_IOTYPE.VALUE_SRC {DEFAULT} \
994
CONFIG.PCW_MIO_14_PULLUP.VALUE_SRC {DEFAULT} \
995
CONFIG.PCW_MIO_14_SLEW.VALUE_SRC {DEFAULT} \
996
CONFIG.PCW_MIO_15_DIRECTION.VALUE_SRC {DEFAULT} \
997
CONFIG.PCW_MIO_15_IOTYPE.VALUE_SRC {DEFAULT} \
998
CONFIG.PCW_MIO_15_PULLUP.VALUE_SRC {DEFAULT} \
999
CONFIG.PCW_MIO_15_SLEW.VALUE_SRC {DEFAULT} \
1000
CONFIG.PCW_MIO_16_DIRECTION.VALUE_SRC {DEFAULT} \
1001
CONFIG.PCW_MIO_16_IOTYPE.VALUE_SRC {DEFAULT} \
1002
CONFIG.PCW_MIO_16_PULLUP.VALUE_SRC {DEFAULT} \
1003
CONFIG.PCW_MIO_16_SLEW.VALUE_SRC {DEFAULT} \
1004
CONFIG.PCW_MIO_17_DIRECTION.VALUE_SRC {DEFAULT} \
1005
CONFIG.PCW_MIO_17_IOTYPE.VALUE_SRC {DEFAULT} \
1006
CONFIG.PCW_MIO_17_PULLUP.VALUE_SRC {DEFAULT} \
1007
CONFIG.PCW_MIO_17_SLEW.VALUE_SRC {DEFAULT} \
1008
CONFIG.PCW_MIO_18_DIRECTION.VALUE_SRC {DEFAULT} \
1009
CONFIG.PCW_MIO_18_IOTYPE.VALUE_SRC {DEFAULT} \
1010
CONFIG.PCW_MIO_18_PULLUP.VALUE_SRC {DEFAULT} \
1011
CONFIG.PCW_MIO_18_SLEW.VALUE_SRC {DEFAULT} \
1012
CONFIG.PCW_MIO_19_DIRECTION.VALUE_SRC {DEFAULT} \
1013
CONFIG.PCW_MIO_19_IOTYPE.VALUE_SRC {DEFAULT} \
1014
CONFIG.PCW_MIO_19_PULLUP.VALUE_SRC {DEFAULT} \
1015
CONFIG.PCW_MIO_19_SLEW.VALUE_SRC {DEFAULT} \
1016
CONFIG.PCW_MIO_1_DIRECTION.VALUE_SRC {DEFAULT} \
1017
CONFIG.PCW_MIO_1_IOTYPE.VALUE_SRC {DEFAULT} \
1018
CONFIG.PCW_MIO_1_PULLUP.VALUE_SRC {DEFAULT} \
1019
CONFIG.PCW_MIO_1_SLEW.VALUE_SRC {DEFAULT} \
1020
CONFIG.PCW_MIO_20_DIRECTION.VALUE_SRC {DEFAULT} \
1021
CONFIG.PCW_MIO_20_IOTYPE.VALUE_SRC {DEFAULT} \
1022
CONFIG.PCW_MIO_20_PULLUP.VALUE_SRC {DEFAULT} \
1023
CONFIG.PCW_MIO_20_SLEW.VALUE_SRC {DEFAULT} \
1024
CONFIG.PCW_MIO_21_DIRECTION.VALUE_SRC {DEFAULT} \
1025
CONFIG.PCW_MIO_21_IOTYPE.VALUE_SRC {DEFAULT} \
1026
CONFIG.PCW_MIO_21_PULLUP.VALUE_SRC {DEFAULT} \
1027
CONFIG.PCW_MIO_21_SLEW.VALUE_SRC {DEFAULT} \
1028
CONFIG.PCW_MIO_22_DIRECTION.VALUE_SRC {DEFAULT} \
1029
CONFIG.PCW_MIO_22_IOTYPE.VALUE_SRC {DEFAULT} \
1030
CONFIG.PCW_MIO_22_PULLUP.VALUE_SRC {DEFAULT} \
1031
CONFIG.PCW_MIO_22_SLEW.VALUE_SRC {DEFAULT} \
1032
CONFIG.PCW_MIO_23_DIRECTION.VALUE_SRC {DEFAULT} \
1033
CONFIG.PCW_MIO_23_IOTYPE.VALUE_SRC {DEFAULT} \
1034
CONFIG.PCW_MIO_23_PULLUP.VALUE_SRC {DEFAULT} \
1035
CONFIG.PCW_MIO_23_SLEW.VALUE_SRC {DEFAULT} \
1036
CONFIG.PCW_MIO_24_DIRECTION.VALUE_SRC {DEFAULT} \
1037
CONFIG.PCW_MIO_24_IOTYPE.VALUE_SRC {DEFAULT} \
1038
CONFIG.PCW_MIO_24_PULLUP.VALUE_SRC {DEFAULT} \
1039
CONFIG.PCW_MIO_24_SLEW.VALUE_SRC {DEFAULT} \
1040
CONFIG.PCW_MIO_25_DIRECTION.VALUE_SRC {DEFAULT} \
1041
CONFIG.PCW_MIO_25_IOTYPE.VALUE_SRC {DEFAULT} \
1042
CONFIG.PCW_MIO_25_PULLUP.VALUE_SRC {DEFAULT} \
1043
CONFIG.PCW_MIO_25_SLEW.VALUE_SRC {DEFAULT} \
1044
CONFIG.PCW_MIO_26_DIRECTION.VALUE_SRC {DEFAULT} \
1045
CONFIG.PCW_MIO_26_IOTYPE.VALUE_SRC {DEFAULT} \
1046
CONFIG.PCW_MIO_26_PULLUP.VALUE_SRC {DEFAULT} \
1047
CONFIG.PCW_MIO_26_SLEW.VALUE_SRC {DEFAULT} \
1048
CONFIG.PCW_MIO_27_DIRECTION.VALUE_SRC {DEFAULT} \
1049
CONFIG.PCW_MIO_27_IOTYPE.VALUE_SRC {DEFAULT} \
1050
CONFIG.PCW_MIO_27_PULLUP.VALUE_SRC {DEFAULT} \
1051
CONFIG.PCW_MIO_27_SLEW.VALUE_SRC {DEFAULT} \
1052
CONFIG.PCW_MIO_28_DIRECTION.VALUE_SRC {DEFAULT} \
1053
CONFIG.PCW_MIO_28_IOTYPE.VALUE_SRC {DEFAULT} \
1054
CONFIG.PCW_MIO_28_PULLUP.VALUE_SRC {DEFAULT} \
1055
CONFIG.PCW_MIO_28_SLEW.VALUE_SRC {DEFAULT} \
1056
CONFIG.PCW_MIO_29_DIRECTION.VALUE_SRC {DEFAULT} \
1057
CONFIG.PCW_MIO_29_IOTYPE.VALUE_SRC {DEFAULT} \
1058
CONFIG.PCW_MIO_29_PULLUP.VALUE_SRC {DEFAULT} \
1059
CONFIG.PCW_MIO_29_SLEW.VALUE_SRC {DEFAULT} \
1060
CONFIG.PCW_MIO_2_DIRECTION.VALUE_SRC {DEFAULT} \
1061
CONFIG.PCW_MIO_2_IOTYPE.VALUE_SRC {DEFAULT} \
1062
CONFIG.PCW_MIO_2_PULLUP.VALUE_SRC {DEFAULT} \
1063
CONFIG.PCW_MIO_2_SLEW.VALUE_SRC {DEFAULT} \
1064
CONFIG.PCW_MIO_30_DIRECTION.VALUE_SRC {DEFAULT} \
1065
CONFIG.PCW_MIO_30_IOTYPE.VALUE_SRC {DEFAULT} \
1066
CONFIG.PCW_MIO_30_PULLUP.VALUE_SRC {DEFAULT} \
1067
CONFIG.PCW_MIO_30_SLEW.VALUE_SRC {DEFAULT} \
1068
CONFIG.PCW_MIO_31_DIRECTION.VALUE_SRC {DEFAULT} \
1069
CONFIG.PCW_MIO_31_IOTYPE.VALUE_SRC {DEFAULT} \
1070
CONFIG.PCW_MIO_31_PULLUP.VALUE_SRC {DEFAULT} \
1071
CONFIG.PCW_MIO_31_SLEW.VALUE_SRC {DEFAULT} \
1072
CONFIG.PCW_MIO_32_DIRECTION.VALUE_SRC {DEFAULT} \
1073
CONFIG.PCW_MIO_32_IOTYPE.VALUE_SRC {DEFAULT} \
1074
CONFIG.PCW_MIO_32_PULLUP.VALUE_SRC {DEFAULT} \
1075
CONFIG.PCW_MIO_32_SLEW.VALUE_SRC {DEFAULT} \
1076
CONFIG.PCW_MIO_33_DIRECTION.VALUE_SRC {DEFAULT} \
1077
CONFIG.PCW_MIO_33_IOTYPE.VALUE_SRC {DEFAULT} \
1078
CONFIG.PCW_MIO_33_PULLUP.VALUE_SRC {DEFAULT} \
1079
CONFIG.PCW_MIO_33_SLEW.VALUE_SRC {DEFAULT} \
1080
CONFIG.PCW_MIO_34_DIRECTION.VALUE_SRC {DEFAULT} \
1081
CONFIG.PCW_MIO_34_IOTYPE.VALUE_SRC {DEFAULT} \
1082
CONFIG.PCW_MIO_34_PULLUP.VALUE_SRC {DEFAULT} \
1083
CONFIG.PCW_MIO_34_SLEW.VALUE_SRC {DEFAULT} \
1084
CONFIG.PCW_MIO_35_DIRECTION.VALUE_SRC {DEFAULT} \
1085
CONFIG.PCW_MIO_35_IOTYPE.VALUE_SRC {DEFAULT} \
1086
CONFIG.PCW_MIO_35_PULLUP.VALUE_SRC {DEFAULT} \
1087
CONFIG.PCW_MIO_35_SLEW.VALUE_SRC {DEFAULT} \
1088
CONFIG.PCW_MIO_36_DIRECTION.VALUE_SRC {DEFAULT} \
1089
CONFIG.PCW_MIO_36_IOTYPE.VALUE_SRC {DEFAULT} \
1090
CONFIG.PCW_MIO_36_PULLUP.VALUE_SRC {DEFAULT} \
1091
CONFIG.PCW_MIO_36_SLEW.VALUE_SRC {DEFAULT} \
1092
CONFIG.PCW_MIO_37_DIRECTION.VALUE_SRC {DEFAULT} \
1093
CONFIG.PCW_MIO_37_IOTYPE.VALUE_SRC {DEFAULT} \
1094
CONFIG.PCW_MIO_37_PULLUP.VALUE_SRC {DEFAULT} \
1095
CONFIG.PCW_MIO_37_SLEW.VALUE_SRC {DEFAULT} \
1096
CONFIG.PCW_MIO_38_DIRECTION.VALUE_SRC {DEFAULT} \
1097
CONFIG.PCW_MIO_38_IOTYPE.VALUE_SRC {DEFAULT} \
1098
CONFIG.PCW_MIO_38_PULLUP.VALUE_SRC {DEFAULT} \
1099
CONFIG.PCW_MIO_38_SLEW.VALUE_SRC {DEFAULT} \
1100
CONFIG.PCW_MIO_39_DIRECTION.VALUE_SRC {DEFAULT} \
1101
CONFIG.PCW_MIO_39_IOTYPE.VALUE_SRC {DEFAULT} \
1102
CONFIG.PCW_MIO_39_PULLUP.VALUE_SRC {DEFAULT} \
1103
CONFIG.PCW_MIO_39_SLEW.VALUE_SRC {DEFAULT} \
1104
CONFIG.PCW_MIO_3_DIRECTION.VALUE_SRC {DEFAULT} \
1105
CONFIG.PCW_MIO_3_IOTYPE.VALUE_SRC {DEFAULT} \
1106
CONFIG.PCW_MIO_3_PULLUP.VALUE_SRC {DEFAULT} \
1107
CONFIG.PCW_MIO_3_SLEW.VALUE_SRC {DEFAULT} \
1108
CONFIG.PCW_MIO_40_DIRECTION.VALUE_SRC {DEFAULT} \
1109
CONFIG.PCW_MIO_40_IOTYPE.VALUE_SRC {DEFAULT} \
1110
CONFIG.PCW_MIO_40_PULLUP.VALUE_SRC {DEFAULT} \
1111
CONFIG.PCW_MIO_40_SLEW.VALUE_SRC {DEFAULT} \
1112
CONFIG.PCW_MIO_41_DIRECTION.VALUE_SRC {DEFAULT} \
1113
CONFIG.PCW_MIO_41_IOTYPE.VALUE_SRC {DEFAULT} \
1114
CONFIG.PCW_MIO_41_PULLUP.VALUE_SRC {DEFAULT} \
1115
CONFIG.PCW_MIO_41_SLEW.VALUE_SRC {DEFAULT} \
1116
CONFIG.PCW_MIO_42_DIRECTION.VALUE_SRC {DEFAULT} \
1117
CONFIG.PCW_MIO_42_IOTYPE.VALUE_SRC {DEFAULT} \
1118
CONFIG.PCW_MIO_42_PULLUP.VALUE_SRC {DEFAULT} \
1119
CONFIG.PCW_MIO_42_SLEW.VALUE_SRC {DEFAULT} \
1120
CONFIG.PCW_MIO_43_DIRECTION.VALUE_SRC {DEFAULT} \
1121
CONFIG.PCW_MIO_43_IOTYPE.VALUE_SRC {DEFAULT} \
1122
CONFIG.PCW_MIO_43_PULLUP.VALUE_SRC {DEFAULT} \
1123
CONFIG.PCW_MIO_43_SLEW.VALUE_SRC {DEFAULT} \
1124
CONFIG.PCW_MIO_44_DIRECTION.VALUE_SRC {DEFAULT} \
1125
CONFIG.PCW_MIO_44_IOTYPE.VALUE_SRC {DEFAULT} \
1126
CONFIG.PCW_MIO_44_PULLUP.VALUE_SRC {DEFAULT} \
1127
CONFIG.PCW_MIO_44_SLEW.VALUE_SRC {DEFAULT} \
1128
CONFIG.PCW_MIO_45_DIRECTION.VALUE_SRC {DEFAULT} \
1129
CONFIG.PCW_MIO_45_IOTYPE.VALUE_SRC {DEFAULT} \
1130
CONFIG.PCW_MIO_45_PULLUP.VALUE_SRC {DEFAULT} \
1131
CONFIG.PCW_MIO_45_SLEW.VALUE_SRC {DEFAULT} \
1132
CONFIG.PCW_MIO_46_DIRECTION.VALUE_SRC {DEFAULT} \
1133
CONFIG.PCW_MIO_46_IOTYPE.VALUE_SRC {DEFAULT} \
1134
CONFIG.PCW_MIO_46_PULLUP.VALUE_SRC {DEFAULT} \
1135
CONFIG.PCW_MIO_46_SLEW.VALUE_SRC {DEFAULT} \
1136
CONFIG.PCW_MIO_47_DIRECTION.VALUE_SRC {DEFAULT} \
1137
CONFIG.PCW_MIO_47_IOTYPE.VALUE_SRC {DEFAULT} \
1138
CONFIG.PCW_MIO_47_PULLUP.VALUE_SRC {DEFAULT} \
1139
CONFIG.PCW_MIO_47_SLEW.VALUE_SRC {DEFAULT} \
1140
CONFIG.PCW_MIO_48_DIRECTION.VALUE_SRC {DEFAULT} \
1141
CONFIG.PCW_MIO_48_IOTYPE.VALUE_SRC {DEFAULT} \
1142
CONFIG.PCW_MIO_48_PULLUP.VALUE_SRC {DEFAULT} \
1143
CONFIG.PCW_MIO_48_SLEW.VALUE_SRC {DEFAULT} \
1144
CONFIG.PCW_MIO_49_DIRECTION.VALUE_SRC {DEFAULT} \
1145
CONFIG.PCW_MIO_49_IOTYPE.VALUE_SRC {DEFAULT} \
1146
CONFIG.PCW_MIO_49_PULLUP.VALUE_SRC {DEFAULT} \
1147
CONFIG.PCW_MIO_49_SLEW.VALUE_SRC {DEFAULT} \
1148
CONFIG.PCW_MIO_4_DIRECTION.VALUE_SRC {DEFAULT} \
1149
CONFIG.PCW_MIO_4_IOTYPE.VALUE_SRC {DEFAULT} \
1150
CONFIG.PCW_MIO_4_PULLUP.VALUE_SRC {DEFAULT} \
1151
CONFIG.PCW_MIO_4_SLEW.VALUE_SRC {DEFAULT} \
1152
CONFIG.PCW_MIO_50_DIRECTION.VALUE_SRC {DEFAULT} \
1153
CONFIG.PCW_MIO_50_IOTYPE.VALUE_SRC {DEFAULT} \
1154
CONFIG.PCW_MIO_50_PULLUP.VALUE_SRC {DEFAULT} \
1155
CONFIG.PCW_MIO_50_SLEW.VALUE_SRC {DEFAULT} \
1156
CONFIG.PCW_MIO_51_DIRECTION.VALUE_SRC {DEFAULT} \
1157
CONFIG.PCW_MIO_51_IOTYPE.VALUE_SRC {DEFAULT} \
1158
CONFIG.PCW_MIO_51_PULLUP.VALUE_SRC {DEFAULT} \
1159
CONFIG.PCW_MIO_51_SLEW.VALUE_SRC {DEFAULT} \
1160
CONFIG.PCW_MIO_52_DIRECTION.VALUE_SRC {DEFAULT} \
1161
CONFIG.PCW_MIO_52_IOTYPE.VALUE_SRC {DEFAULT} \
1162
CONFIG.PCW_MIO_52_PULLUP.VALUE_SRC {DEFAULT} \
1163
CONFIG.PCW_MIO_52_SLEW.VALUE_SRC {DEFAULT} \
1164
CONFIG.PCW_MIO_53_DIRECTION.VALUE_SRC {DEFAULT} \
1165
CONFIG.PCW_MIO_53_IOTYPE.VALUE_SRC {DEFAULT} \
1166
CONFIG.PCW_MIO_53_PULLUP.VALUE_SRC {DEFAULT} \
1167
CONFIG.PCW_MIO_53_SLEW.VALUE_SRC {DEFAULT} \
1168
CONFIG.PCW_MIO_5_DIRECTION.VALUE_SRC {DEFAULT} \
1169
CONFIG.PCW_MIO_5_IOTYPE.VALUE_SRC {DEFAULT} \
1170
CONFIG.PCW_MIO_5_PULLUP.VALUE_SRC {DEFAULT} \
1171
CONFIG.PCW_MIO_5_SLEW.VALUE_SRC {DEFAULT} \
1172
CONFIG.PCW_MIO_6_DIRECTION.VALUE_SRC {DEFAULT} \
1173
CONFIG.PCW_MIO_6_IOTYPE.VALUE_SRC {DEFAULT} \
1174
CONFIG.PCW_MIO_6_PULLUP.VALUE_SRC {DEFAULT} \
1175
CONFIG.PCW_MIO_6_SLEW.VALUE_SRC {DEFAULT} \
1176
CONFIG.PCW_MIO_7_DIRECTION.VALUE_SRC {DEFAULT} \
1177
CONFIG.PCW_MIO_7_IOTYPE.VALUE_SRC {DEFAULT} \
1178
CONFIG.PCW_MIO_7_PULLUP.VALUE_SRC {DEFAULT} \
1179
CONFIG.PCW_MIO_7_SLEW.VALUE_SRC {DEFAULT} \
1180
CONFIG.PCW_MIO_8_DIRECTION.VALUE_SRC {DEFAULT} \
1181
CONFIG.PCW_MIO_8_IOTYPE.VALUE_SRC {DEFAULT} \
1182
CONFIG.PCW_MIO_8_PULLUP.VALUE_SRC {DEFAULT} \
1183
CONFIG.PCW_MIO_8_SLEW.VALUE_SRC {DEFAULT} \
1184
CONFIG.PCW_MIO_9_DIRECTION.VALUE_SRC {DEFAULT} \
1185
CONFIG.PCW_MIO_9_IOTYPE.VALUE_SRC {DEFAULT} \
1186
CONFIG.PCW_MIO_9_PULLUP.VALUE_SRC {DEFAULT} \
1187
CONFIG.PCW_MIO_9_SLEW.VALUE_SRC {DEFAULT} \
1188
CONFIG.PCW_MIO_TREE_PERIPHERALS.VALUE_SRC {DEFAULT} \
1189
CONFIG.PCW_MIO_TREE_SIGNALS.VALUE_SRC {DEFAULT} \
1190
CONFIG.PCW_NAND_CYCLES_T_AR.VALUE_SRC {DEFAULT} \
1191
CONFIG.PCW_NAND_CYCLES_T_CLR.VALUE_SRC {DEFAULT} \
1192
CONFIG.PCW_NAND_CYCLES_T_RC.VALUE_SRC {DEFAULT} \
1193
CONFIG.PCW_NAND_CYCLES_T_REA.VALUE_SRC {DEFAULT} \
1194
CONFIG.PCW_NAND_CYCLES_T_RR.VALUE_SRC {DEFAULT} \
1195
CONFIG.PCW_NAND_CYCLES_T_WC.VALUE_SRC {DEFAULT} \
1196
CONFIG.PCW_NAND_CYCLES_T_WP.VALUE_SRC {DEFAULT} \
1197
CONFIG.PCW_NAND_GRP_D8_ENABLE.VALUE_SRC {DEFAULT} \
1198
CONFIG.PCW_NAND_GRP_D8_IO.VALUE_SRC {DEFAULT} \
1199
CONFIG.PCW_NAND_NAND_IO.VALUE_SRC {DEFAULT} \
1200
CONFIG.PCW_NAND_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1201
CONFIG.PCW_NOR_CS0_T_CEOE.VALUE_SRC {DEFAULT} \
1202
CONFIG.PCW_NOR_CS0_T_PC.VALUE_SRC {DEFAULT} \
1203
CONFIG.PCW_NOR_CS0_T_RC.VALUE_SRC {DEFAULT} \
1204
CONFIG.PCW_NOR_CS0_T_TR.VALUE_SRC {DEFAULT} \
1205
CONFIG.PCW_NOR_CS0_T_WC.VALUE_SRC {DEFAULT} \
1206
CONFIG.PCW_NOR_CS0_T_WP.VALUE_SRC {DEFAULT} \
1207
CONFIG.PCW_NOR_CS0_WE_TIME.VALUE_SRC {DEFAULT} \
1208
CONFIG.PCW_NOR_CS1_T_CEOE.VALUE_SRC {DEFAULT} \
1209
CONFIG.PCW_NOR_CS1_T_PC.VALUE_SRC {DEFAULT} \
1210
CONFIG.PCW_NOR_CS1_T_RC.VALUE_SRC {DEFAULT} \
1211
CONFIG.PCW_NOR_CS1_T_TR.VALUE_SRC {DEFAULT} \
1212
CONFIG.PCW_NOR_CS1_T_WC.VALUE_SRC {DEFAULT} \
1213
CONFIG.PCW_NOR_CS1_T_WP.VALUE_SRC {DEFAULT} \
1214
CONFIG.PCW_NOR_CS1_WE_TIME.VALUE_SRC {DEFAULT} \
1215
CONFIG.PCW_NOR_GRP_A25_ENABLE.VALUE_SRC {DEFAULT} \
1216
CONFIG.PCW_NOR_GRP_A25_IO.VALUE_SRC {DEFAULT} \
1217
CONFIG.PCW_NOR_GRP_CS0_ENABLE.VALUE_SRC {DEFAULT} \
1218
CONFIG.PCW_NOR_GRP_CS0_IO.VALUE_SRC {DEFAULT} \
1219
CONFIG.PCW_NOR_GRP_CS1_ENABLE.VALUE_SRC {DEFAULT} \
1220
CONFIG.PCW_NOR_GRP_CS1_IO.VALUE_SRC {DEFAULT} \
1221
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE.VALUE_SRC {DEFAULT} \
1222
CONFIG.PCW_NOR_GRP_SRAM_CS0_IO.VALUE_SRC {DEFAULT} \
1223
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE.VALUE_SRC {DEFAULT} \
1224
CONFIG.PCW_NOR_GRP_SRAM_CS1_IO.VALUE_SRC {DEFAULT} \
1225
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE.VALUE_SRC {DEFAULT} \
1226
CONFIG.PCW_NOR_GRP_SRAM_INT_IO.VALUE_SRC {DEFAULT} \
1227
CONFIG.PCW_NOR_NOR_IO.VALUE_SRC {DEFAULT} \
1228
CONFIG.PCW_NOR_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1229
CONFIG.PCW_NOR_SRAM_CS0_T_CEOE.VALUE_SRC {DEFAULT} \
1230
CONFIG.PCW_NOR_SRAM_CS0_T_PC.VALUE_SRC {DEFAULT} \
1231
CONFIG.PCW_NOR_SRAM_CS0_T_RC.VALUE_SRC {DEFAULT} \
1232
CONFIG.PCW_NOR_SRAM_CS0_T_TR.VALUE_SRC {DEFAULT} \
1233
CONFIG.PCW_NOR_SRAM_CS0_T_WC.VALUE_SRC {DEFAULT} \
1234
CONFIG.PCW_NOR_SRAM_CS0_T_WP.VALUE_SRC {DEFAULT} \
1235
CONFIG.PCW_NOR_SRAM_CS0_WE_TIME.VALUE_SRC {DEFAULT} \
1236
CONFIG.PCW_NOR_SRAM_CS1_T_CEOE.VALUE_SRC {DEFAULT} \
1237
CONFIG.PCW_NOR_SRAM_CS1_T_PC.VALUE_SRC {DEFAULT} \
1238
CONFIG.PCW_NOR_SRAM_CS1_T_RC.VALUE_SRC {DEFAULT} \
1239
CONFIG.PCW_NOR_SRAM_CS1_T_TR.VALUE_SRC {DEFAULT} \
1240
CONFIG.PCW_NOR_SRAM_CS1_T_WC.VALUE_SRC {DEFAULT} \
1241
CONFIG.PCW_NOR_SRAM_CS1_T_WP.VALUE_SRC {DEFAULT} \
1242
CONFIG.PCW_NOR_SRAM_CS1_WE_TIME.VALUE_SRC {DEFAULT} \
1243
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0.VALUE_SRC {DEFAULT} \
1244
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1.VALUE_SRC {DEFAULT} \
1245
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2.VALUE_SRC {DEFAULT} \
1246
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3.VALUE_SRC {DEFAULT} \
1247
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0.VALUE_SRC {DEFAULT} \
1248
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1.VALUE_SRC {DEFAULT} \
1249
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2.VALUE_SRC {DEFAULT} \
1250
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3.VALUE_SRC {DEFAULT} \
1251
CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1252
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1253
CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1254
CONFIG.PCW_PERIPHERAL_BOARD_PRESET.VALUE_SRC {DEFAULT} \
1255
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1256
CONFIG.PCW_PJTAG_PJTAG_IO.VALUE_SRC {DEFAULT} \
1257
CONFIG.PCW_PLL_BYPASSMODE_ENABLE.VALUE_SRC {DEFAULT} \
1258
CONFIG.PCW_PRESET_BANK0_VOLTAGE.VALUE_SRC {DEFAULT} \
1259
CONFIG.PCW_PRESET_BANK1_VOLTAGE.VALUE_SRC {DEFAULT} \
1260
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE.VALUE_SRC {DEFAULT} \
1261
CONFIG.PCW_QSPI_GRP_FBCLK_IO.VALUE_SRC {DEFAULT} \
1262
CONFIG.PCW_QSPI_GRP_IO1_ENABLE.VALUE_SRC {DEFAULT} \
1263
CONFIG.PCW_QSPI_GRP_IO1_IO.VALUE_SRC {DEFAULT} \
1264
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE.VALUE_SRC {DEFAULT} \
1265
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO.VALUE_SRC {DEFAULT} \
1266
CONFIG.PCW_QSPI_GRP_SS1_ENABLE.VALUE_SRC {DEFAULT} \
1267
CONFIG.PCW_QSPI_GRP_SS1_IO.VALUE_SRC {DEFAULT} \
1268
CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1269
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1270
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1271
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1272
CONFIG.PCW_QSPI_QSPI_IO.VALUE_SRC {DEFAULT} \
1273
CONFIG.PCW_SD0_GRP_CD_ENABLE.VALUE_SRC {DEFAULT} \
1274
CONFIG.PCW_SD0_GRP_CD_IO.VALUE_SRC {DEFAULT} \
1275
CONFIG.PCW_SD0_GRP_POW_ENABLE.VALUE_SRC {DEFAULT} \
1276
CONFIG.PCW_SD0_GRP_POW_IO.VALUE_SRC {DEFAULT} \
1277
CONFIG.PCW_SD0_GRP_WP_ENABLE.VALUE_SRC {DEFAULT} \
1278
CONFIG.PCW_SD0_GRP_WP_IO.VALUE_SRC {DEFAULT} \
1279
CONFIG.PCW_SD0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1280
CONFIG.PCW_SD0_SD0_IO.VALUE_SRC {DEFAULT} \
1281
CONFIG.PCW_SD1_GRP_CD_ENABLE.VALUE_SRC {DEFAULT} \
1282
CONFIG.PCW_SD1_GRP_CD_IO.VALUE_SRC {DEFAULT} \
1283
CONFIG.PCW_SD1_GRP_POW_ENABLE.VALUE_SRC {DEFAULT} \
1284
CONFIG.PCW_SD1_GRP_POW_IO.VALUE_SRC {DEFAULT} \
1285
CONFIG.PCW_SD1_GRP_WP_ENABLE.VALUE_SRC {DEFAULT} \
1286
CONFIG.PCW_SD1_GRP_WP_IO.VALUE_SRC {DEFAULT} \
1287
CONFIG.PCW_SD1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1288
CONFIG.PCW_SD1_SD1_IO.VALUE_SRC {DEFAULT} \
1289
CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1290
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1291
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1292
CONFIG.PCW_SDIO_PERIPHERAL_VALID.VALUE_SRC {DEFAULT} \
1293
CONFIG.PCW_SMC_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1294
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1295
CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1296
CONFIG.PCW_SPI0_GRP_SS0_ENABLE.VALUE_SRC {DEFAULT} \
1297
CONFIG.PCW_SPI0_GRP_SS0_IO.VALUE_SRC {DEFAULT} \
1298
CONFIG.PCW_SPI0_GRP_SS1_ENABLE.VALUE_SRC {DEFAULT} \
1299
CONFIG.PCW_SPI0_GRP_SS1_IO.VALUE_SRC {DEFAULT} \
1300
CONFIG.PCW_SPI0_GRP_SS2_ENABLE.VALUE_SRC {DEFAULT} \
1301
CONFIG.PCW_SPI0_GRP_SS2_IO.VALUE_SRC {DEFAULT} \
1302
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1303
CONFIG.PCW_SPI0_SPI0_IO.VALUE_SRC {DEFAULT} \
1304
CONFIG.PCW_SPI1_GRP_SS0_ENABLE.VALUE_SRC {DEFAULT} \
1305
CONFIG.PCW_SPI1_GRP_SS0_IO.VALUE_SRC {DEFAULT} \
1306
CONFIG.PCW_SPI1_GRP_SS1_ENABLE.VALUE_SRC {DEFAULT} \
1307
CONFIG.PCW_SPI1_GRP_SS1_IO.VALUE_SRC {DEFAULT} \
1308
CONFIG.PCW_SPI1_GRP_SS2_ENABLE.VALUE_SRC {DEFAULT} \
1309
CONFIG.PCW_SPI1_GRP_SS2_IO.VALUE_SRC {DEFAULT} \
1310
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1311
CONFIG.PCW_SPI1_SPI1_IO.VALUE_SRC {DEFAULT} \
1312
CONFIG.PCW_SPI_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1313
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1314
CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1315
CONFIG.PCW_S_AXI_HP0_DATA_WIDTH.VALUE_SRC {DEFAULT} \
1316
CONFIG.PCW_S_AXI_HP1_DATA_WIDTH.VALUE_SRC {DEFAULT} \
1317
CONFIG.PCW_S_AXI_HP2_DATA_WIDTH.VALUE_SRC {DEFAULT} \
1318
CONFIG.PCW_S_AXI_HP3_DATA_WIDTH.VALUE_SRC {DEFAULT} \
1319
CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1320
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1321
CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1322
CONFIG.PCW_TRACE_GRP_16BIT_ENABLE.VALUE_SRC {DEFAULT} \
1323
CONFIG.PCW_TRACE_GRP_16BIT_IO.VALUE_SRC {DEFAULT} \
1324
CONFIG.PCW_TRACE_GRP_2BIT_ENABLE.VALUE_SRC {DEFAULT} \
1325
CONFIG.PCW_TRACE_GRP_2BIT_IO.VALUE_SRC {DEFAULT} \
1326
CONFIG.PCW_TRACE_GRP_32BIT_ENABLE.VALUE_SRC {DEFAULT} \
1327
CONFIG.PCW_TRACE_GRP_32BIT_IO.VALUE_SRC {DEFAULT} \
1328
CONFIG.PCW_TRACE_GRP_4BIT_ENABLE.VALUE_SRC {DEFAULT} \
1329
CONFIG.PCW_TRACE_GRP_4BIT_IO.VALUE_SRC {DEFAULT} \
1330
CONFIG.PCW_TRACE_GRP_8BIT_ENABLE.VALUE_SRC {DEFAULT} \
1331
CONFIG.PCW_TRACE_GRP_8BIT_IO.VALUE_SRC {DEFAULT} \
1332
CONFIG.PCW_TRACE_INTERNAL_WIDTH.VALUE_SRC {DEFAULT} \
1333
CONFIG.PCW_TRACE_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1334
CONFIG.PCW_TRACE_TRACE_IO.VALUE_SRC {DEFAULT} \
1335
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1336
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1337
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1338
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1339
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1340
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1341
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1342
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1343
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1344
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1345
CONFIG.PCW_TTC0_TTC0_IO.VALUE_SRC {DEFAULT} \
1346
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1347
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1348
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1349
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1350
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1351
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1352
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1353
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1354
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1355
CONFIG.PCW_TTC1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1356
CONFIG.PCW_TTC1_TTC1_IO.VALUE_SRC {DEFAULT} \
1357
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1358
CONFIG.PCW_UART0_BAUD_RATE.VALUE_SRC {DEFAULT} \
1359
CONFIG.PCW_UART0_GRP_FULL_ENABLE.VALUE_SRC {DEFAULT} \
1360
CONFIG.PCW_UART0_GRP_FULL_IO.VALUE_SRC {DEFAULT} \
1361
CONFIG.PCW_UART0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1362
CONFIG.PCW_UART0_UART0_IO.VALUE_SRC {DEFAULT} \
1363
CONFIG.PCW_UART1_BAUD_RATE.VALUE_SRC {DEFAULT} \
1364
CONFIG.PCW_UART1_GRP_FULL_ENABLE.VALUE_SRC {DEFAULT} \
1365
CONFIG.PCW_UART1_GRP_FULL_IO.VALUE_SRC {DEFAULT} \
1366
CONFIG.PCW_UART1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1367
CONFIG.PCW_UART1_UART1_IO.VALUE_SRC {DEFAULT} \
1368
CONFIG.PCW_UART_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1369
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1370
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1371
CONFIG.PCW_UART_PERIPHERAL_VALID.VALUE_SRC {DEFAULT} \
1372
CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE.VALUE_SRC {DEFAULT} \
1373
CONFIG.PCW_UIPARAM_DDR_AL.VALUE_SRC {DEFAULT} \
1374
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT.VALUE_SRC {DEFAULT} \
1375
CONFIG.PCW_UIPARAM_DDR_BL.VALUE_SRC {DEFAULT} \
1376
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0.VALUE_SRC {DEFAULT} \
1377
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1.VALUE_SRC {DEFAULT} \
1378
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2.VALUE_SRC {DEFAULT} \
1379
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3.VALUE_SRC {DEFAULT} \
1380
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH.VALUE_SRC {DEFAULT} \
1381
CONFIG.PCW_UIPARAM_DDR_CL.VALUE_SRC {DEFAULT} \
1382
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM.VALUE_SRC {DEFAULT} \
1383
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1384
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1385
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM.VALUE_SRC {DEFAULT} \
1386
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1387
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1388
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM.VALUE_SRC {DEFAULT} \
1389
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1390
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1391
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM.VALUE_SRC {DEFAULT} \
1392
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1393
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1394
CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN.VALUE_SRC {DEFAULT} \
1395
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT.VALUE_SRC {DEFAULT} \
1396
CONFIG.PCW_UIPARAM_DDR_CWL.VALUE_SRC {DEFAULT} \
1397
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY.VALUE_SRC {DEFAULT} \
1398
CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM.VALUE_SRC {DEFAULT} \
1399
CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1400
CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1401
CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM.VALUE_SRC {DEFAULT} \
1402
CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1403
CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1404
CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM.VALUE_SRC {DEFAULT} \
1405
CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1406
CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1407
CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM.VALUE_SRC {DEFAULT} \
1408
CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1409
CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1410
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0.VALUE_SRC {DEFAULT} \
1411
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1.VALUE_SRC {DEFAULT} \
1412
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2.VALUE_SRC {DEFAULT} \
1413
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3.VALUE_SRC {DEFAULT} \
1414
CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM.VALUE_SRC {DEFAULT} \
1415
CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1416
CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1417
CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM.VALUE_SRC {DEFAULT} \
1418
CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1419
CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1420
CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM.VALUE_SRC {DEFAULT} \
1421
CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1422
CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1423
CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM.VALUE_SRC {DEFAULT} \
1424
CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
1425
CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
1426
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH.VALUE_SRC {DEFAULT} \
1427
CONFIG.PCW_UIPARAM_DDR_ECC.VALUE_SRC {DEFAULT} \
1428
CONFIG.PCW_UIPARAM_DDR_ENABLE.VALUE_SRC {DEFAULT} \
1429
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ.VALUE_SRC {DEFAULT} \
1430
CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP.VALUE_SRC {DEFAULT} \
1431
CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE.VALUE_SRC {DEFAULT} \
1432
CONFIG.PCW_UIPARAM_DDR_PARTNO.VALUE_SRC {DEFAULT} \
1433
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT.VALUE_SRC {DEFAULT} \
1434
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN.VALUE_SRC {DEFAULT} \
1435
CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE.VALUE_SRC {DEFAULT} \
1436
CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE.VALUE_SRC {DEFAULT} \
1437
CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL.VALUE_SRC {DEFAULT} \
1438
CONFIG.PCW_UIPARAM_DDR_T_FAW.VALUE_SRC {DEFAULT} \
1439
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN.VALUE_SRC {DEFAULT} \
1440
CONFIG.PCW_UIPARAM_DDR_T_RC.VALUE_SRC {DEFAULT} \
1441
CONFIG.PCW_UIPARAM_DDR_T_RCD.VALUE_SRC {DEFAULT} \
1442
CONFIG.PCW_UIPARAM_DDR_T_RP.VALUE_SRC {DEFAULT} \
1443
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF.VALUE_SRC {DEFAULT} \
1444
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1445
CONFIG.PCW_USB0_RESET_ENABLE.VALUE_SRC {DEFAULT} \
1446
CONFIG.PCW_USB0_RESET_IO.VALUE_SRC {DEFAULT} \
1447
CONFIG.PCW_USB0_USB0_IO.VALUE_SRC {DEFAULT} \
1448
CONFIG.PCW_USB1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1449
CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1450
CONFIG.PCW_USB1_RESET_ENABLE.VALUE_SRC {DEFAULT} \
1451
CONFIG.PCW_USB1_RESET_IO.VALUE_SRC {DEFAULT} \
1452
CONFIG.PCW_USB1_USB1_IO.VALUE_SRC {DEFAULT} \
1453
CONFIG.PCW_USB_RESET_ENABLE.VALUE_SRC {DEFAULT} \
1454
CONFIG.PCW_USB_RESET_POLARITY.VALUE_SRC {DEFAULT} \
1455
CONFIG.PCW_USB_RESET_SELECT.VALUE_SRC {DEFAULT} \
1456
CONFIG.PCW_USE_CROSS_TRIGGER.VALUE_SRC {DEFAULT} \
1457
CONFIG.PCW_WDT_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \
1458
CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \
1459
CONFIG.PCW_WDT_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
1460
CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
1461
CONFIG.PCW_WDT_WDT_IO.VALUE_SRC {DEFAULT} \
1462
 ] $processing_system7_0
1463
 
1464
  # Create interface connections
1465
  connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
1466
  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
1467
  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
1468
  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
1469
 
1470
  # Create port connections
1471
  connect_bd_net -net ARESETN_1 [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
1472
  connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_ports peripheral_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
1473
  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
1474
  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
1475
 
1476
  # Create address segments
1477
  create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
1478
 
1479
  # Perform GUI Layout
1480
  regenerate_bd_layout -layout_string {
1481
   guistr: "# # String gsaved with Nlview 6.5.12  2016-01-29 bk=1.3547 VDI=39 GEI=35 GUI=JA:1.6
1482
#  -string -flagsOSRD
1483
preplace port DDR -pg 1 -y 20 -defaultsOSRD
1484
preplace port FIXED_IO -pg 1 -y 60 -defaultsOSRD
1485
preplace port FCLK_CLK0 -pg 1 -y 40 -defaultsOSRD
1486
preplace port M00_AXI -pg 1 -y 80 -defaultsOSRD
1487
preplace portBus peripheral_aresetn -pg 1 -y 100 -defaultsOSRD
1488
preplace inst proc_sys_reset_0 -pg 1 -lvl 1 -y 340 -defaultsOSRD
1489
preplace inst axi_interconnect_0 -pg 1 -lvl 1 -y 120 -defaultsOSRD
1490
preplace inst processing_system7_0 -pg 1 -lvl 1 -y 580 -defaultsOSRD
1491
preplace netloc processing_system7_0_DDR 1 1 1 450
1492
preplace netloc processing_system7_0_M_AXI_GP0 1 0 2 20 450 430
1493
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 2 50 440 440
1494
preplace netloc ARESETN_1 1 0 2 40 250 430
1495
preplace netloc processing_system7_0_FIXED_IO 1 1 1 480
1496
preplace netloc axi_interconnect_0_M00_AXI 1 1 1 460
1497
preplace netloc proc_sys_reset_0_peripheral_aresetn 1 0 2 50 240 490
1498
preplace netloc processing_system7_0_FCLK_CLK0 1 0 2 30 430 470
1499
levelinfo -pg 1 0 240 510 -top 0 -bot 700
1500
",
1501
}
1502
 
1503
  # Restore current instance
1504
  current_bd_instance $oldCurInst
1505
 
1506
  save_bd_design
1507
}
1508
# End of create_root_design()
1509
 
1510
 
1511
##################################################################
1512
# MAIN FLOW
1513
##################################################################
1514
 
1515
create_root_design ""
1516
 
1517
 

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