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[/] [qaz_libs/] [trunk/] [zed_board/] [src/] [top.v] - Blame information for rev 15

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1 15 qaztronic
// --------------------------------------------------------------------
2
//
3
// --------------------------------------------------------------------
4
 
5
 
6
module
7
  top
8
  (
9
    inout [14:0]DDR_Addr,
10
    inout [2:0]DDR_BankAddr,
11
    inout DDR_CAS_n,
12
    inout DDR_Clk,
13
    inout DDR_Clk_n,
14
    inout DDR_CKE,
15
    inout DDR_CS_n,
16
    inout [3:0]DDR_DM,
17
    inout [31:0]DDR_DQ,
18
    inout [3:0]DDR_DQS,
19
    inout [3:0]DDR_DQS_n,
20
    inout DDR_ODT,
21
    inout DDR_RAS_n,
22
    inout DDR_DRSTB,
23
    inout DDR_WEB,
24
    inout DDR_VRN,
25
    inout DDR_VRP,
26
    inout [53:0]MIO,
27
    inout PS_CLK,
28
    inout PS_PORB,
29
    inout PS_SRSTB,
30
 
31
    input AC_ADR0,  // Audio Codec - Bank 13
32
    output AC_ADR1,
33
    inout AC_GPIO0,
34
    inout AC_GPIO1,
35
    inout AC_GPIO2,
36
    inout AC_GPIO3,
37
    input AC_MCLK,
38
    input AC_SCK,
39
    inout AC_SDA,
40
 
41
    input GCLK,  // Clock Source - Bank 13
42
 
43
    inout JA1,  // JA Pmod - Bank 13
44
    inout JA10,
45
    inout JA2,
46
    inout JA3,
47
    inout JA4,
48
    inout JA7,
49
    inout JA8,
50
    inout JA9,
51
 
52
    inout JB1,  // JB Pmod - Bank 13
53
    inout JB10,
54
    inout JB2,
55
    inout JB3,
56
    inout JB4,
57
    inout JB7,
58
    inout JB8,
59
    inout JB9,
60
 
61
    inout JC1_N,  // JC Pmod - Bank 13
62
    inout JC1_P,
63
    inout JC2_N,
64
    inout JC2_P,
65
    inout JC3_N,
66
    inout JC3_P,
67
    inout JC4_N,
68
    inout JC4_P,
69
 
70
    inout JD1_N,  // JA Pmod - Bank 13
71
    inout JD1_P,
72
    inout JD2_N,
73
    inout JD2_P,
74
    inout JD3_N,
75
    inout JD3_P,
76
    inout JD4_N,
77
    inout JD4_P,
78
 
79
    output OLED_DC, // OLED Display - Bank 13
80
    output OLED_RES,
81
    output OLED_SCLK,
82
    output OLED_SDIN,
83
    output OLED_VBAT,
84
    output OLED_VDD,
85
 
86
    output HD_CLK, // HDMI Output - Bank 33
87
    output HD_D0,
88
    output HD_D1,
89
    output HD_D10,
90
    output HD_D11,
91
    output HD_D12,
92
    output HD_D13,
93
    output HD_D14,
94
    output HS_D15,
95
    output HD_D2,
96
    output HD_D3,
97
    output HD_D4,
98
    output HD_D5,
99
    output HD_D6,
100
    output HD_D7,
101
    output HD_D8,
102
    output HD_D9,
103
    output HD_DE,
104
    output HD_HSYNC,
105
    output HD_INT,
106
    output HD_SCL,
107
    inout HD_SDA,
108
    output HD_SPDIF,
109
    input HD_SPDIFO,
110
    output HD_VSYNC,
111
 
112
    output LD0, // User LEDs - Bank 33
113
    output        LD1,
114
    output        LD2,
115
    output        LD3,
116
    output        LD4,
117
    output        LD5,
118
    output        LD6,
119
    output        LD7,
120
 
121
    output VGA_B1,  // VGA Output - Bank 33
122
    output VGA_B2,
123
    output VGA_B3,
124
    output VGA_B4,
125
    output VGA_G1,
126
    output VGA_G2,
127
    output VGA_G3,
128
    output VGA_G4,
129
    output VGA_HS,
130
    output VGA_R1,
131
    output VGA_R2,
132
    output VGA_R3,
133
    output VGA_R4,
134
    output VGA_VS,
135
 
136
    input BTNC, // User Push Buttons - Bank 34
137
    input BTND,
138
    input BTNL,
139
    input BTNR,
140
    input BTNU,
141
 
142
    input OTG_VBUSOC, // USB OTG Reset - Bank 34
143
 
144
    // inout XADC_GIO0,  // XADC GIO - Bank 34
145
    // inout XADC_GIO1,
146
    // inout XADC_GIO2,
147
    // inout XADC_GIO3,
148
 
149
    inout PUDC_B, // Miscellaneous - Bank 34
150
 
151
    output OTG_RESETN,  // USB OTG Reset - Bank 35
152
 
153
    input SW0,  // User DIP Switches - Bank 35
154
    input SW1,
155
    input SW2,
156
    input SW3,
157
    input SW4,
158
    input SW5,
159
    input SW6,
160
    input SW7,
161
 
162
    // input AD0N_R, // XADC AD Channels - Bank 35
163
    // input AD0P_R,
164
    // input AD8N_N,
165
    // input AD8P_R,
166
 
167
    output FMC_SCL, // FMC Expansion Connector - Bank 13
168
    inout FMC_SDA,
169
 
170
    inout FMC_PRSNT,  // FMC Expansion Connector - Bank 33
171
 
172
    input FMC_CLK0_N, // FMC Expansion Connector - Bank 34
173
    input FMC_CLK0_P,
174
    input FMC_LA00_CC_N,
175
    input FMC_LA00_CC_P,
176
    input FMC_LA01_CC_N,
177
    input FMC_LA01_CC_P,
178
    inout FMC_LA02_N,
179
    inout FMC_LA02_P,
180
    inout FMC_LA03_N,
181
    inout FMC_LA03_P,
182
    inout FMC_LA04_N,
183
    inout FMC_LA04_P,
184
    inout FMC_LA05_N,
185
    inout FMC_LA05_P,
186
    inout FMC_LA06_N,
187
    inout FMC_LA06_P,
188
    inout FMC_LA07_N,
189
    inout FMC_LA07_P,
190
    inout FMC_LA08_N,
191
    inout FMC_LA08_P,
192
    inout FMC_LA09_N,
193
    inout FMC_LA09_P,
194
    inout FMC_LA10_N,
195
    inout FMC_LA10_P,
196
    inout FMC_LA11_N,
197
    inout FMC_LA11_P,
198
    inout FMC_LA12_N,
199
    inout FMC_LA12_P,
200
    inout FMC_LA13_N,
201
    inout FMC_LA13_P,
202
    inout FMC_LA14_N,
203
    inout FMC_LA14_P,
204
    inout FMC_LA15_N,
205
    inout FMC_LA15_P,
206
    inout FMC_LA16_N,
207
    inout FMC_LA16_P,
208
 
209
    input FMC_CLK1_N, // FMC Expansion Connector - Bank 35
210
    input FMC_CLK1_P,
211
    input FMC_LA17_CC_N,
212
    input FMC_LA17_CC_P,
213
    input FMC_LA18_CC_N,
214
    input FMC_LA18_CC_P,
215
    inout FMC_LA19_N,
216
    inout FMC_LA19_P,
217
    inout FMC_LA20_N,
218
    inout FMC_LA20_P,
219
    inout FMC_LA21_N,
220
    inout FMC_LA21_P,
221
    inout FMC_LA22_N,
222
    inout FMC_LA22_P,
223
    inout FMC_LA23_N,
224
    inout FMC_LA23_P,
225
    inout FMC_LA24_N,
226
    inout FMC_LA24_P,
227
    inout FMC_LA25_N,
228
    inout FMC_LA25_P,
229
    inout FMC_LA26_N,
230
    inout FMC_LA26_P,
231
    inout FMC_LA27_N,
232
    inout FMC_LA27_P,
233
    inout FMC_LA28_N,
234
    inout FMC_LA28_P,
235
    inout FMC_LA29_N,
236
    inout FMC_LA29_P,
237
    inout FMC_LA30_N,
238
    inout FMC_LA30_P,
239
    inout FMC_LA31_N,
240
    inout FMC_LA31_P,
241
    inout FMC_LA32_N,
242
    inout FMC_LA32_P,
243
    inout FMC_LA33_N,
244
    inout FMC_LA33_P
245
  );
246
 
247
  // --------------------------------------------------------------------
248
  //
249
  // (* KEEP = "TRUE" *) wire [31:0] M00_AXI_araddr;
250
  // (* KEEP = "TRUE" *) wire [2:0]  M00_AXI_arprot;
251
  // (* KEEP = "TRUE" *) wire        M00_AXI_arready;
252
  // (* KEEP = "TRUE" *) wire        M00_AXI_arvalid;
253
  // (* KEEP = "TRUE" *) wire [31:0] M00_AXI_awaddr;
254
  // (* KEEP = "TRUE" *) wire [2:0]  M00_AXI_awprot;
255
  // (* KEEP = "TRUE" *) wire        M00_AXI_awready;
256
  // (* KEEP = "TRUE" *) wire        M00_AXI_awvalid;
257
  // (* KEEP = "TRUE" *) wire        M00_AXI_bready;
258
  // (* KEEP = "TRUE" *) wire [1:0]  M00_AXI_bresp;
259
  // (* KEEP = "TRUE" *) wire        M00_AXI_bvalid;
260
  // (* KEEP = "TRUE" *) wire [31:0] M00_AXI_rdata;
261
  // (* KEEP = "TRUE" *) wire        M00_AXI_rready;
262
  // (* KEEP = "TRUE" *) wire [1:0]  M00_AXI_rresp;
263
  // (* KEEP = "TRUE" *) wire        M00_AXI_rvalid;
264
  // (* KEEP = "TRUE" *) wire [31:0] M00_AXI_wdata;
265
  // (* KEEP = "TRUE" *) wire        M00_AXI_wready;
266
  // (* KEEP = "TRUE" *) wire [3:0]  M00_AXI_wstrb;
267
  // (* KEEP = "TRUE" *) wire        M00_AXI_wvalid;
268
 
269
  wire [31:0] M00_AXI_araddr;
270
  wire [2:0]  M00_AXI_arprot;
271
  wire        M00_AXI_arready;
272
  wire        M00_AXI_arvalid;
273
  wire [31:0] M00_AXI_awaddr;
274
  wire [2:0]  M00_AXI_awprot;
275
  wire        M00_AXI_awready;
276
  wire        M00_AXI_awvalid;
277
  wire        M00_AXI_bready;
278
  wire [1:0]  M00_AXI_bresp;
279
  wire        M00_AXI_bvalid;
280
  wire [31:0] M00_AXI_rdata;
281
  wire        M00_AXI_rready;
282
  wire [1:0]  M00_AXI_rresp;
283
  wire        M00_AXI_rvalid;
284
  wire [31:0] M00_AXI_wdata;
285
  wire        M00_AXI_wready;
286
  wire [3:0]  M00_AXI_wstrb;
287
  wire        M00_AXI_wvalid;
288
 
289
  wire FCLK_CLK0;
290
 
291
  zync
292
    zync_i
293
    (
294
      .DDR_addr(DDR_Addr),
295
      .DDR_ba(DDR_BankAddr),
296
      .DDR_cas_n(DDR_CAS_n),
297
      .DDR_ck_n(DDR_Clk_n),
298
      .DDR_ck_p(DDR_Clk),
299
      .DDR_cke(DDR_CKE),
300
      .DDR_cs_n(DDR_CS_n),
301
      .DDR_dm(DDR_DM),
302
      .DDR_dq(DDR_DQ),
303
      .DDR_dqs_n(DDR_DQS_n),
304
      .DDR_dqs_p(DDR_DQS),
305
      .DDR_odt(DDR_ODT),
306
      .DDR_ras_n(DDR_RAS_n),
307
      .DDR_reset_n(DDR_DRSTB),
308
      .DDR_we_n(DDR_WEB),
309
      .FIXED_IO_ddr_vrn(DDR_VRN),
310
      .FIXED_IO_ddr_vrp(DDR_VRP),
311
      .FIXED_IO_mio(MIO),
312
      .FIXED_IO_ps_clk(PS_CLK),
313
      .FIXED_IO_ps_porb(PS_PORB),
314
      .FIXED_IO_ps_srstb(PS_SRSTB),
315
      .FCLK_CLK0(FCLK_CLK0),
316
      .M00_AXI_araddr(M00_AXI_araddr),
317
      .M00_AXI_arprot(M00_AXI_arprot),
318
      .M00_AXI_arready(M00_AXI_arready),
319
      .M00_AXI_arvalid(M00_AXI_arvalid),
320
      .M00_AXI_awaddr(M00_AXI_awaddr),
321
      .M00_AXI_awprot(M00_AXI_awprot),
322
      .M00_AXI_awready(M00_AXI_awready),
323
      .M00_AXI_awvalid(M00_AXI_awvalid),
324
      .M00_AXI_bready(M00_AXI_bready),
325
      .M00_AXI_bresp(M00_AXI_bresp),
326
      .M00_AXI_bvalid(M00_AXI_bvalid),
327
      .M00_AXI_rdata(M00_AXI_rdata),
328
      .M00_AXI_rready(M00_AXI_rready),
329
      .M00_AXI_rresp(M00_AXI_rresp),
330
      .M00_AXI_rvalid(M00_AXI_rvalid),
331
      .M00_AXI_wdata(M00_AXI_wdata),
332
      .M00_AXI_wready(M00_AXI_wready),
333
      .M00_AXI_wstrb(M00_AXI_wstrb),
334
      .M00_AXI_wvalid(M00_AXI_wvalid),
335
      .peripheral_aresetn(peripheral_aresetn)
336
    );
337
 
338
 
339
  // --------------------------------------------------------------------
340
  //
341
  wire [31:0] slv_reg0;
342
  wire [31:0] slv_reg1;
343
  wire [31:0] slv_reg2;
344
  wire [31:0] slv_reg3;
345
 
346
  reg_file_v1_0_S00_AXI
347
  #(
348
    .C_S_AXI_DATA_WIDTH(32),
349
    .C_S_AXI_ADDR_WIDTH(4)
350
  )
351
  reg_file_v1_0_S00_AXI_inst
352
  (
353
    .S_AXI_ACLK(FCLK_CLK0),
354
    .S_AXI_ARESETN(peripheral_aresetn),
355
    .S_AXI_AWADDR(M00_AXI_awaddr[3:0]),
356
    .S_AXI_AWPROT(M00_AXI_awprot),
357
    .S_AXI_AWVALID(M00_AXI_awvalid),
358
    .S_AXI_AWREADY(M00_AXI_awready),
359
    .S_AXI_WDATA(M00_AXI_wdata),
360
    .S_AXI_WSTRB(M00_AXI_wstrb),
361
    .S_AXI_WVALID(M00_AXI_wvalid),
362
    .S_AXI_WREADY(M00_AXI_wready),
363
    .S_AXI_BRESP(M00_AXI_bresp),
364
    .S_AXI_BVALID(M00_AXI_bvalid),
365
    .S_AXI_BREADY(M00_AXI_bready),
366
    .S_AXI_ARADDR(M00_AXI_araddr[3:0]),
367
    .S_AXI_ARPROT(M00_AXI_arprot),
368
    .S_AXI_ARVALID(M00_AXI_arvalid),
369
    .S_AXI_ARREADY(M00_AXI_arready),
370
    .S_AXI_RDATA(M00_AXI_rdata),
371
    .S_AXI_RRESP(M00_AXI_rresp),
372
    .S_AXI_RVALID(M00_AXI_rvalid),
373
    .S_AXI_RREADY(M00_AXI_rready),
374
 
375
    .slv_reg0(slv_reg0),
376
    .slv_reg1(slv_reg1),
377
    .slv_reg2(slv_reg2),
378
    .slv_reg3(slv_reg3)
379
 
380
  );
381
 
382
 
383
  // --------------------------------------------------------------------
384
  //  outputs
385
  assign LD0 = slv_reg0[0];
386
  assign LD1 = slv_reg0[1];
387
  assign LD2 = slv_reg0[2];
388
  assign LD3 = slv_reg0[3];
389
  assign LD4 = slv_reg0[4];
390
  assign LD5 = slv_reg0[5];
391
  assign LD6 = slv_reg0[6];
392
  assign LD7 = slv_reg0[7];
393
 
394
  assign AC_ADR1 = 0;
395
  assign AC_GPIO0 = 'bz;
396
  assign AC_GPIO1 = 'bz;
397
  assign AC_GPIO2 = 'bz;
398
  assign AC_GPIO3 = 'bz;
399
  assign AC_SDA = 'bz;
400
 
401
  assign JA1 = 'bz;  // JA Pmod - Bank 13
402
  assign JA10 = 'bz;
403
  assign JA2 = 'bz;
404
  assign JA3 = 'bz;
405
  assign JA4 = 'bz;
406
  assign JA7 = 'bz;
407
  assign JA8 = 'bz;
408
  assign JA9 = 'bz;
409
 
410
  assign JB1 = 'bz;  // JB Pmod - Bank 13
411
  assign JB10 = 'bz;
412
  assign JB2 = 'bz;
413
  assign JB3 = 'bz;
414
  assign JB4 = 'bz;
415
  assign JB7 = 'bz;
416
  assign JB8 = 'bz;
417
  assign JB9 = 'bz;
418
 
419
  assign JC1_N = 'bz;  // JC Pmod - Bank 13
420
  assign JC1_P = 'bz;
421
  assign JC2_N = 'bz;
422
  assign JC2_P = 'bz;
423
  assign JC3_N = 'bz;
424
  assign JC3_P = 'bz;
425
  assign JC4_N = 'bz;
426
  assign JC4_P = 'bz;
427
 
428
  assign JD1_N = 'bz;  // JA Pmod - Bank 13
429
  assign JD1_P = 'bz;
430
  assign JD2_N = 'bz;
431
  assign JD2_P = 'bz;
432
  assign JD3_N = 'bz;
433
  assign JD3_P = 'bz;
434
  assign JD4_N = 'bz;
435
  assign JD4_P = 'bz;
436
 
437
  assign OLED_DC = 0; // OLED Display - Bank 13
438
  assign OLED_RES = 0;
439
  assign OLED_SCLK = 0;
440
  assign OLED_SDIN = 0;
441
  assign OLED_VBAT = 0;
442
  assign OLED_VDD = 0;
443
 
444
  assign HD_CLK = 0; // HDMI assign - = 0;Bank 33
445
  assign HD_D0 = 0;
446
  assign HD_D1 = 0;
447
  assign HD_D10 = 0;
448
  assign HD_D11 = 0;
449
  assign HD_D12 = 0;
450
  assign HD_D13 = 0;
451
  assign HD_D14 = 0;
452
  assign HS_D15 = 0;
453
  assign HD_D2 = 0;
454
  assign HD_D3 = 0;
455
  assign HD_D4 = 0;
456
  assign HD_D5 = 0;
457
  assign HD_D6 = 0;
458
  assign HD_D7 = 0;
459
  assign HD_D8 = 0;
460
  assign HD_D9 = 0;
461
  assign HD_DE = 0;
462
  assign HD_HSYNC = 0;
463
  assign HD_INT = 0;
464
  assign HD_SCL = 0;
465
  assign HD_SDA = 'bz;
466
  assign HD_SPDIF = 0;
467
  assign HD_VSYNC = 0;
468
 
469
  assign VGA_B1 = 0;  // VGA assign - = 0;Bank 33
470
  assign VGA_B2 = 0;
471
  assign VGA_B3 = 0;
472
  assign VGA_B4 = 0;
473
  assign VGA_G1 = 0;
474
  assign VGA_G2 = 0;
475
  assign VGA_G3 = 0;
476
  assign VGA_G4 = 0;
477
  assign VGA_HS = 0;
478
  assign VGA_R1 = 0;
479
  assign VGA_R2 = 0;
480
  assign VGA_R3 = 0;
481
  assign VGA_R4 = 0;
482
  assign VGA_VS = 0;
483
 
484
  // assign XADC_GIO0 = 'bz;  // XADC GIO - Bank 34
485
  // assign XADC_GIO1 = 'bz;
486
  // assign XADC_GIO2 = 'bz;
487
  // assign XADC_GIO3 = 'bz;
488
 
489
  assign PUDC_B = 'bz; // Miscellaneous - Bank 34
490
 
491
  assign OTG_RESETN = 0;  // USB OTG Reset - Bank 35
492
 
493
  assign FMC_SCL = 0; // FMC Expansion Connector - Bank 13
494
  assign FMC_SDA = 'bz;
495
 
496
  assign FMC_PRSNT = 'bz;  // FMC Expansion Connector - Bank 33
497
 
498
  assign FMC_LA02_N = 'bz;
499
  assign FMC_LA02_P = 'bz;
500
  assign FMC_LA03_N = 'bz;
501
  assign FMC_LA03_P = 'bz;
502
  assign FMC_LA04_N = 'bz;
503
  assign FMC_LA04_P = 'bz;
504
  assign FMC_LA05_N = 'bz;
505
  assign FMC_LA05_P = 'bz;
506
  assign FMC_LA06_N = 'bz;
507
  assign FMC_LA06_P = 'bz;
508
  assign FMC_LA07_N = 'bz;
509
  assign FMC_LA07_P = 'bz;
510
  assign FMC_LA08_N = 'bz;
511
  assign FMC_LA08_P = 'bz;
512
  assign FMC_LA09_N = 'bz;
513
  assign FMC_LA09_P = 'bz;
514
  assign FMC_LA10_N = 'bz;
515
  assign FMC_LA10_P = 'bz;
516
  assign FMC_LA11_N = 'bz;
517
  assign FMC_LA11_P = 'bz;
518
  assign FMC_LA12_N = 'bz;
519
  assign FMC_LA12_P = 'bz;
520
  assign FMC_LA13_N = 'bz;
521
  assign FMC_LA13_P = 'bz;
522
  assign FMC_LA14_N = 'bz;
523
  assign FMC_LA14_P = 'bz;
524
  assign FMC_LA15_N = 'bz;
525
  assign FMC_LA15_P = 'bz;
526
  assign FMC_LA16_N = 'bz;
527
  assign FMC_LA16_P = 'bz;
528
 
529
  assign FMC_LA19_N = 'bz;
530
  assign FMC_LA19_P = 'bz;
531
  assign FMC_LA20_N = 'bz;
532
  assign FMC_LA20_P = 'bz;
533
  assign FMC_LA21_N = 'bz;
534
  assign FMC_LA21_P = 'bz;
535
  assign FMC_LA22_N = 'bz;
536
  assign FMC_LA22_P = 'bz;
537
  assign FMC_LA23_N = 'bz;
538
  assign FMC_LA23_P = 'bz;
539
  assign FMC_LA24_N = 'bz;
540
  assign FMC_LA24_P = 'bz;
541
  assign FMC_LA25_N = 'bz;
542
  assign FMC_LA25_P = 'bz;
543
  assign FMC_LA26_N = 'bz;
544
  assign FMC_LA26_P = 'bz;
545
  assign FMC_LA27_N = 'bz;
546
  assign FMC_LA27_P = 'bz;
547
  assign FMC_LA28_N = 'bz;
548
  assign FMC_LA28_P = 'bz;
549
  assign FMC_LA29_N = 'bz;
550
  assign FMC_LA29_P = 'bz;
551
  assign FMC_LA30_N = 'bz;
552
  assign FMC_LA30_P = 'bz;
553
  assign FMC_LA31_N = 'bz;
554
  assign FMC_LA31_P = 'bz;
555
  assign FMC_LA32_N = 'bz;
556
  assign FMC_LA32_P = 'bz;
557
  assign FMC_LA33_N = 'bz;
558
  assign FMC_LA33_P = 'bz;
559
 
560
 
561
endmodule
562
 
563
 
564
 

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