OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [zed_board/] [syn/] [vivado_16_2/] [vivado_16_2.srcs/] [sources_1/] [bd/] [zync/] [zync.bd] - Blame information for rev 27

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 qaztronic 

2
3 
 
4
5 
    xilinx.com
6 
    BlockDiagram
7 
    zync
8 
    1.00.a
9
10
11 
        isTop
12 
        true
13
14
15
16
17 
        DDR
18
19
20
21
22
23 
            TIMEPERIOD_PS
24 
            1250
25
26
27
28
29
30
31
32 
            MEMORY_TYPE
33 
            COMPONENTS
34
35
36
37
38
39
40
41 
            DATA_WIDTH
42 
            8
43
44
45
46
47
48
49
50 
            CS_ENABLED
51 
            true
52
53
54
55
56
57
58
59 
            DATA_MASK_ENABLED
60 
            true
61
62
63
64
65
66
67
68 
            SLOT
69 
            Single
70
71
72
73
74
75
76
77 
            MEM_ADDR_MAP
78 
            ROW_COLUMN_BANK
79
80
81
82
83
84
85
86 
            BURST_LENGTH
87 
            8
88
89
90
91
92
93
94
95 
            AXI_ARBITRATION_SCHEME
96 
            TDM
97
98
99
100
101
102
103
104 
            CAS_LATENCY
105 
            11
106
107
108
109
110
111
112
113 
            CAS_WRITE_LATENCY
114 
            11
115
116
117
118
119
120
121
122
123
124 
        FIXED_IO
125
126
127
128
129
130 
        M00_AXI
131
132
133
134
135
136 
            DATA_WIDTH
137 
            32
138
139
140
141
142
143
144
145 
            PROTOCOL
146 
            AXI4LITE
147
148
149
150
151
152
153
154 
            FREQ_HZ
155 
            100000000
156
157
158
159
160
161
162
163 
            ID_WIDTH
164 
            0
165
166
167
168
169
170
171
172 
            ADDR_WIDTH
173 
            32
174
175
176
177
178
179
180
181 
            AWUSER_WIDTH
182 
            0
183
184
185
186
187
188
189
190 
            ARUSER_WIDTH
191 
            0
192
193
194
195
196
197
198
199 
            WUSER_WIDTH
200 
            0
201
202
203
204
205
206
207
208 
            RUSER_WIDTH
209 
            0
210
211
212
213
214
215
216
217 
            BUSER_WIDTH
218 
            0
219
220
221
222
223
224
225
226 
            READ_WRITE_MODE
227 
            READ_WRITE
228
229
230
231
232
233
234
235 
            HAS_BURST
236 
            1
237
238
239
240
241
242
243
244 
            HAS_LOCK
245 
            1
246
247
248
249
250
251
252
253 
            HAS_PROT
254 
            1
255
256
257
258
259
260
261
262 
            HAS_CACHE
263 
            1
264
265
266
267
268
269
270
271 
            HAS_QOS
272 
            1
273
274
275
276
277
278
279
280 
            HAS_REGION
281 
            0
282
283
284
285
286
287
288
289 
            HAS_WSTRB
290 
            1
291
292
293
294
295
296
297
298 
            HAS_BRESP
299 
            1
300
301
302
303
304
305
306
307 
            HAS_RRESP
308 
            1
309
310
311
312
313
314
315
316 
            SUPPORTS_NARROW_BURST
317 
            0
318
319
320
321
322
323
324
325 
            NUM_READ_OUTSTANDING
326 
            8
327
328
329
330
331
332
333
334 
            NUM_WRITE_OUTSTANDING
335 
            8
336
337
338
339
340
341
342
343 
            MAX_BURST_LENGTH
344 
            1
345
346
347
348
349
350
351
352 
            PHASE
353 
            0.000
354
355
356
357
358
359
360
361 
            CLK_DOMAIN
362 
            zync_processing_system7_0_0_FCLK_CLK0
363
364
365
366
367
368
369
370
371
372 
        CLK.FCLK_CLK0
373 
        Clk
374 
        Clock
375
376
377
378
379
380
381 
              CLK
382
383
384 
              FCLK_CLK0
385
386
387
388
389
390 
            FREQ_HZ
391 
            100000000
392
393
394
395
396
397
398
399 
            PHASE
400 
            0.000
401
402
403
404
405
406
407
408 
            CLK_DOMAIN
409 
            zync_processing_system7_0_0_FCLK_CLK0
410
411
412
413
414
415
416
417 
            ASSOCIATED_BUSIF
418 
            M00_AXI
419
420
421
422
423
424
425
426
427
428 
        RST.PERIPHERAL_ARESETN
429 
        Reset
430 
        Reset
431
432
433
434
435
436
437 
              RST
438
439
440 
              peripheral_aresetn
441
442
443
444
445
446 
            POLARITY
447 
            ACTIVE_LOW
448
449
450
451
452
453
454
455
456
457
458
459
460 
          BlockDiagram
461 
          :vivado.xilinx.com:
462
463
464
465
466
467 
          FCLK_CLK0
468
469 
            out
470
471
472
473 
          peripheral_aresetn
474
475 
            out
476
477 
              0
478 
              0
479
480
481
482
483
484
485
486 
        M00_AXI
487
488 
          Reg
489 
          0
490 
          64K
491 
          32
492 
          register
493
494
495
496
497 
 
498
499 
    xilinx.com
500 
    BlockDiagram
501 
    zync_imp
502 
    1.00.a
503
504
505 
        axi_interconnect_0
506
507
508 
          zync_axi_interconnect_0_0
509 
          1
510 
          xilinx.com:ip:axi_interconnect:2.1
511
512
513
514 
        proc_sys_reset_0
515
516
517 
          zync_proc_sys_reset_0_0
518
519
520
521 
        processing_system7_0
522
523
524 
          zync_processing_system7_0_0
525 
          0
526 
          0
527 
          ZedBoard
528
529
530
531
532
533 
        processing_system7_0_M_AXI_GP0
534
535
536
537
538
539
540 
        ARESETN_1
541
542
543
544
545 
        proc_sys_reset_0_peripheral_aresetn
546
547
548
549
550
551
552 
        processing_system7_0_FCLK_CLK0
553
554
555
556
557
558
559
560
561
562 
        processing_system7_0_FCLK_RESET0_N
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579 
 
580
581 
    xilinx.com
582 
    BlockDiagram/zync_imp
583 
    axi_interconnect_0
584 
    1.00.a
585
586
587 
        S00_AXI
588
589
590
591
592
593 
        M00_AXI
594
595
596
597
598
599 
        CLK.ACLK
600 
        Clk
601 
        Clock
602
603
604
605
606
607
608 
              CLK
609
610
611 
              ACLK
612
613
614
615
616
617 
        RST.ARESETN
618 
        Reset
619 
        Reset
620
621
622
623
624
625
626 
              RST
627
628
629 
              ARESETN
630
631
632
633
634
635 
        CLK.S00_ACLK
636 
        Clk
637 
        Clock
638
639
640
641
642
643
644 
              CLK
645
646
647 
              S00_ACLK
648
649
650
651
652
653 
            ASSOCIATED_BUSIF
654 
            S00_AXI
655
656
657
658
659
660
661
662 
            ASSOCIATED_RESET
663 
            S00_ARESETN
664
665
666
667
668
669
670
671
672
673 
        RST.S00_ARESETN
674 
        Reset
675 
        Reset
676
677
678
679
680
681
682 
              RST
683
684
685 
              S00_ARESETN
686
687
688
689
690
691 
        CLK.M00_ACLK
692 
        Clk
693 
        Clock
694
695
696
697
698
699
700 
              CLK
701
702
703 
              M00_ACLK
704
705
706
707
708
709 
            ASSOCIATED_BUSIF
710 
            M00_AXI
711
712
713
714
715
716
717
718 
            ASSOCIATED_RESET
719 
            M00_ARESETN
720
721
722
723
724
725
726
727
728
729 
        RST.M00_ARESETN
730 
        Reset
731 
        Reset
732
733
734
735
736
737
738 
              RST
739
740
741 
              M00_ARESETN
742
743
744
745
746
747
748
749
750 
          BlockDiagram
751 
          :vivado.xilinx.com:
752
753
754
755
756
757 
          ACLK
758
759 
            in
760
761
762
763 
          ARESETN
764
765 
            in
766
767 
              0
768 
              0
769
770
771
772
773 
          S00_ACLK
774
775 
            in
776
777
778
779 
          S00_ARESETN
780
781 
            in
782
783 
              0
784 
              0
785
786
787
788
789 
          M00_ACLK
790
791 
            in
792
793
794
795 
          M00_ARESETN
796
797 
            in
798
799 
              0
800 
              0
801
802
803
804
805
806
807 
 
808
809 
    xilinx.com
810 
    BlockDiagram/zync_imp
811 
    axi_interconnect_0_imp
812 
    1.00.a
813
814
815 
        s00_couplers
816
817
818
819
820
821
822 
        axi_interconnect_0_ACLK_net
823
824
825
826
827 
        axi_interconnect_0_ARESETN_net
828
829
830
831
832 
        S00_ACLK_1
833
834
835
836
837 
        S00_ARESETN_1
838
839
840
841
842
843
844
845
846
847
848
849
850
851 
 
852
853 
    xilinx.com
854 
    BlockDiagram/zync_imp/axi_interconnect_0_imp
855 
    s00_couplers
856 
    1.00.a
857
858
859 
        M_AXI
860
861
862
863
864
865 
        S_AXI
866
867
868
869
870
871 
        CLK.M_ACLK
872 
        Clk
873 
        Clock
874
875
876
877
878
879
880 
              CLK
881
882
883 
              M_ACLK
884
885
886
887
888
889 
            ASSOCIATED_BUSIF
890 
            M_AXI
891
892
893
894
895
896
897
898 
            ASSOCIATED_RESET
899 
            M_ARESETN
900
901
902
903
904
905
906
907
908
909 
        RST.M_ARESETN
910 
        Reset
911 
        Reset
912
913
914
915
916
917
918 
              RST
919
920
921 
              M_ARESETN
922
923
924
925
926
927 
        CLK.S_ACLK
928 
        Clk
929 
        Clock
930
931
932
933
934
935
936 
              CLK
937
938
939 
              S_ACLK
940
941
942
943
944
945 
            ASSOCIATED_BUSIF
946 
            S_AXI
947
948
949
950
951
952
953
954 
            ASSOCIATED_RESET
955 
            S_ARESETN
956
957
958
959
960
961
962
963
964
965 
        RST.S_ARESETN
966 
        Reset
967 
        Reset
968
969
970
971
972
973
974 
              RST
975
976
977 
              S_ARESETN
978
979
980
981
982
983
984
985
986 
          BlockDiagram
987 
          :vivado.xilinx.com:
988
989
990
991
992
993 
          M_ACLK
994
995 
            in
996
997
998
999 
          M_ARESETN
1000
1001 
            in
1002
1003 
              0
1004 
              0
1005
1006
1007
1008
1009 
          S_ACLK
1010
1011 
            in
1012
1013
1014
1015 
          S_ARESETN
1016
1017 
            in
1018
1019 
              0
1020 
              0
1021
1022
1023
1024
1025
1026
1027 
 
1028
1029 
    xilinx.com
1030 
    BlockDiagram/zync_imp/axi_interconnect_0_imp
1031 
    s00_couplers_imp
1032 
    1.00.a
1033
1034
1035 
        auto_pc
1036
1037
1038 
          zync_auto_pc_0
1039 
          AXI3
1040 
          AXI4LITE
1041
1042
1043
1044
1045
1046
1047 
        S_ACLK_1
1048
1049
1050
1051
1052 
        S_ARESETN_1
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066 
 
1067
1068 
    xilinx.com
1069 
    Addressing/processing_system7_0
1070 
    processing_system7
1071 
    5.5
1072
1073
1074 
        Data
1075 
        4G
1076 
        32
1077
1078
1079 
            SEG_M00_AXI_Reg
1080 
            /M00_AXI/Reg
1081 
            0x43C00000
1082 
            64K
1083
1084
1085
1086
1087
1088 
 
1089

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.