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[/] [qrisc32/] [trunk/] [Readme.txt] - Blame information for rev 2
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vinogradov |
Project Qrisc32 is risc cpu implementation, purpose is studying
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"Digital System Design" course at Kyoung Hee University during my PhD earning.
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Testbench runs 3 different sorting algorithms on qrisc32 and shows cycles for
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each turn. For observing instruction set , please refer to "risc_report.pdf" file.
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For running simulation you should use qrisc32_TB.do in Modelsim.
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Copyright (C) 2010 Vinogradov Viacheslav.
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