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//////////////////////////////////////////////////////////////////////////////////////////////
//    Project Qrisc32 is risc cpu implementation, purpose is studying
//    Digital System Design course at Kyoung Hee University during my PhD earning
//    Copyright (C) 2010  Vinogradov Viacheslav
//
//    This library is free software; you can redistribute it and/or
//   modify it under the terms of the GNU Lesser General Public
//    License as published by the Free Software Foundation; either
//    version 2.1 of the License, or (at your option) any later version.
//
//    This library is distributed in the hope that it will be useful,
//    but WITHOUT ANY WARRANTY; without even the implied warranty of
//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
//    Lesser General Public License for more details.
//
//    You should have received a copy of the GNU Lesser General Public
//    License along with this library; if not, write to the Free Software
//    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//
//////////////////////////////////////////////////////////////////////////////////////////////
 
 
`ifdef RISC_PACK_DEF
`else
`define RISC_PACK_DEF
 
interface       avalon_port;
logic[31:0] address_r;//address
logic[31:0] data_r;//data is read
logic[31:0] data_w;//data to write
logic           rd,wr,wait_req;//read, write and wait request signals
endinterface
 
package risc_pack;
        typedef struct packed{
                bit[31:0]               val_r1;//value of register src1
                bit[31:0]               val_r2;//value of register src2
                bit[31:0]               val_dst;//value of register dst
 
                bit[4:0]                src_r2;//indicate number of src2 register
                bit[4:0]                src_r1;//indicate number of src1 register
                bit[4:0]                dst_r;//indicate number of dest register
 
                //add to src2
                bit[3:0]                incr_r2;//0 +1 or -1, +2,-2, +4, -4
                bit                             incr_r2_enable;//
 
                //
                bit                             write_reg;//indicate write to RF(addres in dst_r, value in dst_v)
                //load store operations, if both bit is zero then bypass MEM stage
                bit                             read_mem;//indicate read from memory(addres in src1+src2)
                bit                             write_mem;//indicate write to memory(addres in src1+src2, value in dst)
                //
 
                //if alu and shift operations are  zeros then bypass EX stage
                //alu operations
                bit                             and_op;//AND
                bit                             or_op;// OR
                bit                             xor_op;//XOR
                bit                             add_op;//+
                bit                             mul_op;//
                bit                             cmp_op;//compare operation
 
                bit                             ldrf_op;//conditional load
                //shifter operations
                bit                             shl_op;//shift left
                bit                             shr_op;//shift  right
                //jmp operations
                //old pc in  value in   val_r1
                //offset to  pc  value in       val_r2
                //new pc value in       val_dst
                //types of jump
                //indicate to calc new address of PC
                bit                             jmpunc;
                bit                             jmpz;
                bit                             jmpnz;
                bit                             jmpc;
                bit                             jmpnc;
 
        }pipe_struct;
 
//typedef enum logic[3:0]{
        //operations
parameter[3:0]  LDR=4'd0;//,//LDR Rdst,[Rsrc1],-+Rsrc2
                //[31:28]LDR_op
        //[27:26] type of LDR op
        //0- Rdst= Rsrc1
        //1-Rdst[31:16] = code[20:5]  LDRH Rx,0x1234
        //2-Rdst[15:0] = code[20:5]    LDRL Rx,0x5678
        //3- Rdst=[Rsrc1+offset]
        //[25]
        //0 - offset = code[24:10](signed)
        //1 - offset = Rsrc2(signed)
        //[24:22]
        //000  Rsrc2=Rsrc2
        //001  Rsrc2=Rsrc2+1
        //010  Rsrc2=Rsrc2+2
        //011  Rsrc2=Rsrc2+4
        //100  Rsrc2=Rsrc2
        //101  Rsrc2=Rsrc2-1
        //110  Rsrc2=Rsrc2-2
        //111  Rsrc2=Rsrc2-4
        //[14:10] src2
        //[9:5]src1
        //[4:0]dst
parameter[3:0]
        STR=4'd1;//,//STR Rdst,[Rsrc1],-+Rsrc2
                //[31:28]STR_op
        //[27:26] type of STORE op
        //3- [Rsrc1+offset]=Rdst
        //[25]
        //0 - offset = code[24:10](signed)
        //1 - offset = Rsrc2(signed)
        //[24:23]
        //000  Rsrc2=Rsrc2
        //001  Rsrc2=Rsrc2+1
        //010  Rsrc2=Rsrc2+2
        //011  Rsrc2=Rsrc2+4
        //100  Rsrc2=Rsrc2
        //101  Rsrc2=Rsrc2-1
        //110  Rsrc2=Rsrc2-2
        //111  Rsrc2=Rsrc2-4
        //[14:10] src2
        //[9:5]src1
        //[4:0]dst
parameter[3:0]
        JMPUNC=4'd2;//,//unconditional jump
        //[31:28]  jump
        //[27:26] type of jumps
        //0 - jmp       pc[25:0]=code[25:0]
        //1 - jmp       pc=pc+offset(relaitive jump)    jmpr    R2(jmpr R2+4)
        //2 - call      pc=pc+offset, Rdst=pc           callr   R0,0xXXXXXXX,R1+4  or callr R0,R1+4
        //3 - ret       pc=Rdst                         ret     Rx or ret Rx,Ry+-0,1,2,4
        //[25]
        //0 - offset = code[24:10](signed)
        //1 - offset = Rsrc2(signed)
        //[24:23]
        //000  Rsrc2=Rsrc2
        //001  Rsrc2=Rsrc2+1
        //010  Rsrc2=Rsrc2+2
        //011  Rsrc2=Rsrc2+4
        //100  Rsrc2=Rsrc2
        //101  Rsrc2=Rsrc2-1
        //110  Rsrc2=Rsrc2-2
        //111  Rsrc2=Rsrc2-4
        //[14:10] src2
        //[9:5]src1
        //[4:0]dst
parameter[3:0]
        JMPF=4'd3;//,//conditional jumps
        //[31:28]  jump
        //[27:26] type of jumps
        //0 - jmpz      pc=pc+offset
        //1 - jmpnz     pc=pc+offset
        //2 - jmpc      pc=pc+offset
        //3 - jmpnc     pc=pc+offset
        //[25]
        //0 - offset = code[24:10](signed)
        //1 - offset = Rsrc2(signed)
        //[24:22]
        //000  Rsrc2=Rsrc2
        //001  Rsrc2=Rsrc2+1
        //010  Rsrc2=Rsrc2+2
        //011  Rsrc2=Rsrc2+4
        //100  Rsrc2=Rsrc2
        //101  Rsrc2=Rsrc2-1
        //110  Rsrc2=Rsrc2-2
        //111  Rsrc2=Rsrc2-4
        //[14:10] src2
        //[9:5]src1
        //[4:0]dst
 
parameter[3:0]
        ALU=4'd4;// AND, OR, XOR,
                // ADD,  MUL,
                // SHR, SHL
        //[31:28]ALU_op
        //[27:25] type of op
        //0- AND
        //1- OR
        //2- XOR
        //3- ADD
        //4- MUL
        //5-shift Rsrc1 left by Rscr2 ...0 MSB->C flag
        //6-shift Rsrc1 right by Rscr2 ...0 LSB ->C flag
        //7-CMP compare,
        //[24:23]
        //000  Rsrc2=Rsrc2
        //001  Rsrc2=Rsrc2+1
        //010  Rsrc2=Rsrc2+2
        //011  Rsrc2=Rsrc2+4
        //100  Rsrc2=Rsrc2
        //101  Rsrc2=Rsrc2-1
        //110  Rsrc2=Rsrc2-2
        //111  Rsrc2=Rsrc2-4
        //[14:10] src2
        //[9:5]src1
        //[4:0]dst
//} OPCODE;
parameter[3:0]
        LDRF=4'd5;//,//LDRF Rdst,Rsrc1,-+Rsrc2
        //[31:28]LDRF_op
        //[27:26] type of LDRF op
        //0-LDRZ Rdst=Rsrc1 if z=1, otherwise Rdst=Rsrc2
        //1-LDRNZ Rdst=Rsrc1 if z=0, otherwise Rdst=Rsrc2
        //2-LDRC Rdst=Rsrc1 if c=1, otherwise Rdst=Rsrc2
        //3-LDRNC Rdst=Rsrc1 if c=0, otherwise Rdst=Rsrc2
        //[24:22]
        //000  Rsrc2=Rsrc2
        //001  Rsrc2=Rsrc2+1
        //010  Rsrc2=Rsrc2+2
        //011  Rsrc2=Rsrc2+4
        //100  Rsrc2=Rsrc2
        //101  Rsrc2=Rsrc2-1
        //110  Rsrc2=Rsrc2-2
        //111  Rsrc2=Rsrc2-4
        //[14:10] src2
        //[9:5]src1
        //[4:0]dst
 
 
parameter[4+1:0]        NOP     =       {32'h0};
//ldr
parameter[4+1:0]        LDRR    =       {LDR,2'b00};
parameter[4+6:0]        LDRH    =       {LDR,7'b01_0_000_0};
parameter[4+6:0]        LDRL    =       {LDR,7'b10_0_000_0};
parameter[4+1:0]        LDRP    =       {LDR,2'b11};
 
//str
parameter[4+1:0]        STRP    ={STR,2'b11};
 
//alu
parameter[4+2:0]        AND             ={ALU,3'd0};
parameter[4+2:0]        OR              ={ALU,3'd1};
parameter[4+2:0]        XOR             ={ALU,3'd2};
parameter[4+2:0]        ADD             ={ALU,3'd3};
parameter[4+2:0]        MUL             ={ALU,3'd4};
parameter[4+2:0]        SHL             ={ALU,3'd5};
parameter[4+2:0]        SHR             ={ALU,3'd6};
parameter[4+2:0]        CMP             ={ALU,3'd7};
 
//jmp
parameter[4+1:0]        JMP             ={JMPUNC,2'd0};
parameter[4+1:0]        JMPR    ={JMPUNC,2'd1};
parameter[4+1:0]        CALL    ={JMPUNC,2'd2};
parameter[4+1:0]        RET             ={JMPUNC,2'd3};
 
parameter[4+1:0]        JMPZ    ={JMPF,2'd0};
parameter[4+1:0]        JMPNZ   ={JMPF,2'd1};
parameter[4+1:0]        JMPC    ={JMPF,2'd2};
parameter[4+1:0]        JMPNC   ={JMPF,2'd3};
 
 
parameter[4+2:0]        LDRZ    ={LDRF,2'd0,1'b0};
parameter[4+2:0]        LDRNZ   ={LDRF,2'd1,1'b0};
parameter[4+2:0]        LDRC    ={LDRF,2'd2,1'b0};
parameter[4+2:0]        LDRNC   ={LDRF,2'd3,1'b0};
 
//common
parameter[0:0]  OFFSET_CODE     =1'b0;
parameter[0:0]  OFFSET_R        =1'b1;
 
parameter[2:0]  INCR_0          =3'b000;
parameter[2:0]  DECR_0          =3'b000;
parameter[2:0]  INCR_1          =3'b001;
parameter[2:0]  INCR_2          =3'b010;
parameter[2:0]  INCR_4          =3'b011;
parameter[2:0]  DECR_1          =3'b101;
parameter[2:0]  DECR_2          =3'b110;
parameter[2:0]  DECR_4          =3'b111;
 
parameter[4:0]  R0                      =5'd0;
parameter[4:0]  R1                      =5'd1;
parameter[4:0]  R2                      =5'd2;
parameter[4:0]  R3                      =5'd3;
parameter[4:0]  R4                      =5'd4;
parameter[4:0]  R5                      =5'd5;
parameter[4:0]  R6                      =5'd6;
parameter[4:0]  R7                      =5'd7;
parameter[4:0]  R8                      =5'd8;
parameter[4:0]  R9                      =5'd9;
parameter[4:0]  R10                     =5'd10;
parameter[4:0]  R11                     =5'd11;
parameter[4:0]  R12                     =5'd12;
parameter[4:0]  R13                     =5'd13;
parameter[4:0]  R14                     =5'd14;
parameter[4:0]  R15                     =5'd15;
parameter[4:0]  R16                     =5'd16;
parameter[4:0]  R17                     =5'd17;
parameter[4:0]  R18                     =5'd18;
parameter[4:0]  R19                     =5'd19;
parameter[4:0]  R20                     =5'd20;
parameter[4:0]  R21                     =5'd21;
parameter[4:0]  R22                     =5'd22;
parameter[4:0]  R23                     =5'd23;
parameter[4:0]  R24                     =5'd24;
parameter[4:0]  R25                     =5'd25;
parameter[4:0]  R26                     =5'd26;
parameter[4:0]  R27                     =5'd27;
parameter[4:0]  R28                     =5'd28;
parameter[4:0]  R29                     =5'd29;
parameter[4:0]  R30                     =5'd30;
parameter[4:0]  R31                     =5'd31;
 
endpackage
 
`endif

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[/] [qrisc32/] [trunk/] [package.sv] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	vinogradov	`//////////////////////////////////////////////////////////////////////////////////////////////`
2			`// Project Qrisc32 is risc cpu implementation, purpose is studying`
3			`// Digital System Design course at Kyoung Hee University during my PhD earning`
4			`// Copyright (C) 2010 Vinogradov Viacheslav`
5			`//`
6			`// This library is free software; you can redistribute it and/or`
7			`// modify it under the terms of the GNU Lesser General Public`
8			`// License as published by the Free Software Foundation; either`
9			`// version 2.1 of the License, or (at your option) any later version.`
10			`//`
11			`// This library is distributed in the hope that it will be useful,`
12			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`// Lesser General Public License for more details.`
15			`//`
16			`// You should have received a copy of the GNU Lesser General Public`
17			`// License along with this library; if not, write to the Free Software`
18			`// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
19			`//`
20			`//`
21			`//////////////////////////////////////////////////////////////////////////////////////////////`
22
23
24			`ifdef RISC_PACK_DEF
25			`else
26			`define RISC_PACK_DEF
27
28			`interface avalon_port;`
29			`logic[31:0] address_r;//address`
30			`logic[31:0] data_r;//data is read`
31			`logic[31:0] data_w;//data to write`
32			`logic rd,wr,wait_req;//read, write and wait request signals`
33			`endinterface`
34
35			`package risc_pack;`
36			`typedef struct packed{`
37			`bit[31:0] val_r1;//value of register src1`
38			`bit[31:0] val_r2;//value of register src2`
39			`bit[31:0] val_dst;//value of register dst`
40
41			`bit[4:0] src_r2;//indicate number of src2 register`
42			`bit[4:0] src_r1;//indicate number of src1 register`
43			`bit[4:0] dst_r;//indicate number of dest register`
44
45			`//add to src2`
46			`bit[3:0] incr_r2;//0 +1 or -1, +2,-2, +4, -4`
47			`bit incr_r2_enable;//`
48
49			`//`
50			`bit write_reg;//indicate write to RF(addres in dst_r, value in dst_v)`
51			`//load store operations, if both bit is zero then bypass MEM stage`
52			`bit read_mem;//indicate read from memory(addres in src1+src2)`
53			`bit write_mem;//indicate write to memory(addres in src1+src2, value in dst)`
54			`//`
55
56			`//if alu and shift operations are zeros then bypass EX stage`
57			`//alu operations`
58			`bit and_op;//AND`
59			`bit or_op;// OR`
60			`bit xor_op;//XOR`
61			`bit add_op;//+`
62			`bit mul_op;//`
63			`bit cmp_op;//compare operation`
64
65			`bit ldrf_op;//conditional load`
66			`//shifter operations`
67			`bit shl_op;//shift left`
68			`bit shr_op;//shift right`
69			`//jmp operations`
70			`//old pc in value in val_r1`
71			`//offset to pc value in val_r2`
72			`//new pc value in val_dst`
73			`//types of jump`
74			`//indicate to calc new address of PC`
75			`bit jmpunc;`
76			`bit jmpz;`
77			`bit jmpnz;`
78			`bit jmpc;`
79			`bit jmpnc;`
80
81			`}pipe_struct;`
82
83			`//typedef enum logic[3:0]{`
84			`//operations`
85			`parameter[3:0] LDR=4'd0;//,//LDR Rdst,[Rsrc1],-+Rsrc2`
86			`//[31:28]LDR_op`
87			`//[27:26] type of LDR op`
88			`//0- Rdst= Rsrc1`
89			`//1-Rdst[31:16] = code[20:5] LDRH Rx,0x1234`
90			`//2-Rdst[15:0] = code[20:5] LDRL Rx,0x5678`
91			`//3- Rdst=[Rsrc1+offset]`
92			`//[25]`
93			`//0 - offset = code[24:10](signed)`
94			`//1 - offset = Rsrc2(signed)`
95			`//[24:22]`
96			`//000 Rsrc2=Rsrc2`
97			`//001 Rsrc2=Rsrc2+1`
98			`//010 Rsrc2=Rsrc2+2`
99			`//011 Rsrc2=Rsrc2+4`
100			`//100 Rsrc2=Rsrc2`
101			`//101 Rsrc2=Rsrc2-1`
102			`//110 Rsrc2=Rsrc2-2`
103			`//111 Rsrc2=Rsrc2-4`
104			`//[14:10] src2`
105			`//[9:5]src1`
106			`//[4:0]dst`
107			`parameter[3:0]`
108			`STR=4'd1;//,//STR Rdst,[Rsrc1],-+Rsrc2`
109			`//[31:28]STR_op`
110			`//[27:26] type of STORE op`
111			`//3- [Rsrc1+offset]=Rdst`
112			`//[25]`
113			`//0 - offset = code[24:10](signed)`
114			`//1 - offset = Rsrc2(signed)`
115			`//[24:23]`
116			`//000 Rsrc2=Rsrc2`
117			`//001 Rsrc2=Rsrc2+1`
118			`//010 Rsrc2=Rsrc2+2`
119			`//011 Rsrc2=Rsrc2+4`
120			`//100 Rsrc2=Rsrc2`
121			`//101 Rsrc2=Rsrc2-1`
122			`//110 Rsrc2=Rsrc2-2`
123			`//111 Rsrc2=Rsrc2-4`
124			`//[14:10] src2`
125			`//[9:5]src1`
126			`//[4:0]dst`
127			`parameter[3:0]`
128			`JMPUNC=4'd2;//,//unconditional jump`
129			`//[31:28] jump`
130			`//[27:26] type of jumps`
131			`//0 - jmp pc[25:0]=code[25:0]`
132			`//1 - jmp pc=pc+offset(relaitive jump) jmpr R2(jmpr R2+4)`
133			`//2 - call pc=pc+offset, Rdst=pc callr R0,0xXXXXXXX,R1+4 or callr R0,R1+4`
134			`//3 - ret pc=Rdst ret Rx or ret Rx,Ry+-0,1,2,4`
135			`//[25]`
136			`//0 - offset = code[24:10](signed)`
137			`//1 - offset = Rsrc2(signed)`
138			`//[24:23]`
139			`//000 Rsrc2=Rsrc2`
140			`//001 Rsrc2=Rsrc2+1`
141			`//010 Rsrc2=Rsrc2+2`
142			`//011 Rsrc2=Rsrc2+4`
143			`//100 Rsrc2=Rsrc2`
144			`//101 Rsrc2=Rsrc2-1`
145			`//110 Rsrc2=Rsrc2-2`
146			`//111 Rsrc2=Rsrc2-4`
147			`//[14:10] src2`
148			`//[9:5]src1`
149			`//[4:0]dst`
150			`parameter[3:0]`
151			`JMPF=4'd3;//,//conditional jumps`
152			`//[31:28] jump`
153			`//[27:26] type of jumps`
154			`//0 - jmpz pc=pc+offset`
155			`//1 - jmpnz pc=pc+offset`
156			`//2 - jmpc pc=pc+offset`
157			`//3 - jmpnc pc=pc+offset`
158			`//[25]`
159			`//0 - offset = code[24:10](signed)`
160			`//1 - offset = Rsrc2(signed)`
161			`//[24:22]`
162			`//000 Rsrc2=Rsrc2`
163			`//001 Rsrc2=Rsrc2+1`
164			`//010 Rsrc2=Rsrc2+2`
165			`//011 Rsrc2=Rsrc2+4`
166			`//100 Rsrc2=Rsrc2`
167			`//101 Rsrc2=Rsrc2-1`
168			`//110 Rsrc2=Rsrc2-2`
169			`//111 Rsrc2=Rsrc2-4`
170			`//[14:10] src2`
171			`//[9:5]src1`
172			`//[4:0]dst`
173
174			`parameter[3:0]`
175			`ALU=4'd4;// AND, OR, XOR,`
176			`// ADD, MUL,`
177			`// SHR, SHL`
178			`//[31:28]ALU_op`
179			`//[27:25] type of op`
180			`//0- AND`
181			`//1- OR`
182			`//2- XOR`
183			`//3- ADD`
184			`//4- MUL`
185			`//5-shift Rsrc1 left by Rscr2 ...0 MSB->C flag`
186			`//6-shift Rsrc1 right by Rscr2 ...0 LSB ->C flag`
187			`//7-CMP compare,`
188			`//[24:23]`
189			`//000 Rsrc2=Rsrc2`
190			`//001 Rsrc2=Rsrc2+1`
191			`//010 Rsrc2=Rsrc2+2`
192			`//011 Rsrc2=Rsrc2+4`
193			`//100 Rsrc2=Rsrc2`
194			`//101 Rsrc2=Rsrc2-1`
195			`//110 Rsrc2=Rsrc2-2`
196			`//111 Rsrc2=Rsrc2-4`
197			`//[14:10] src2`
198			`//[9:5]src1`
199			`//[4:0]dst`
200			`//} OPCODE;`
201			`parameter[3:0]`
202			`LDRF=4'd5;//,//LDRF Rdst,Rsrc1,-+Rsrc2`
203			`//[31:28]LDRF_op`
204			`//[27:26] type of LDRF op`
205			`//0-LDRZ Rdst=Rsrc1 if z=1, otherwise Rdst=Rsrc2`
206			`//1-LDRNZ Rdst=Rsrc1 if z=0, otherwise Rdst=Rsrc2`
207			`//2-LDRC Rdst=Rsrc1 if c=1, otherwise Rdst=Rsrc2`
208			`//3-LDRNC Rdst=Rsrc1 if c=0, otherwise Rdst=Rsrc2`
209			`//[24:22]`
210			`//000 Rsrc2=Rsrc2`
211			`//001 Rsrc2=Rsrc2+1`
212			`//010 Rsrc2=Rsrc2+2`
213			`//011 Rsrc2=Rsrc2+4`
214			`//100 Rsrc2=Rsrc2`
215			`//101 Rsrc2=Rsrc2-1`
216			`//110 Rsrc2=Rsrc2-2`
217			`//111 Rsrc2=Rsrc2-4`
218			`//[14:10] src2`
219			`//[9:5]src1`
220			`//[4:0]dst`
221
222
223			`parameter[4+1:0] NOP = {32'h0};`
224			`//ldr`
225			`parameter[4+1:0] LDRR = {LDR,2'b00};`
226			`parameter[4+6:0] LDRH = {LDR,7'b01_0_000_0};`
227			`parameter[4+6:0] LDRL = {LDR,7'b10_0_000_0};`
228			`parameter[4+1:0] LDRP = {LDR,2'b11};`
229
230			`//str`
231			`parameter[4+1:0] STRP ={STR,2'b11};`
232
233			`//alu`
234			`parameter[4+2:0] AND ={ALU,3'd0};`
235			`parameter[4+2:0] OR ={ALU,3'd1};`
236			`parameter[4+2:0] XOR ={ALU,3'd2};`
237			`parameter[4+2:0] ADD ={ALU,3'd3};`
238			`parameter[4+2:0] MUL ={ALU,3'd4};`
239			`parameter[4+2:0] SHL ={ALU,3'd5};`
240			`parameter[4+2:0] SHR ={ALU,3'd6};`
241			`parameter[4+2:0] CMP ={ALU,3'd7};`
242
243			`//jmp`
244			`parameter[4+1:0] JMP ={JMPUNC,2'd0};`
245			`parameter[4+1:0] JMPR ={JMPUNC,2'd1};`
246			`parameter[4+1:0] CALL ={JMPUNC,2'd2};`
247			`parameter[4+1:0] RET ={JMPUNC,2'd3};`
248
249			`parameter[4+1:0] JMPZ ={JMPF,2'd0};`
250			`parameter[4+1:0] JMPNZ ={JMPF,2'd1};`
251			`parameter[4+1:0] JMPC ={JMPF,2'd2};`
252			`parameter[4+1:0] JMPNC ={JMPF,2'd3};`
253
254
255			`parameter[4+2:0] LDRZ ={LDRF,2'd0,1'b0};`
256			`parameter[4+2:0] LDRNZ ={LDRF,2'd1,1'b0};`
257			`parameter[4+2:0] LDRC ={LDRF,2'd2,1'b0};`
258			`parameter[4+2:0] LDRNC ={LDRF,2'd3,1'b0};`
259
260			`//common`
261			`parameter[0:0] OFFSET_CODE =1'b0;`
262			`parameter[0:0] OFFSET_R =1'b1;`
263
264			`parameter[2:0] INCR_0 =3'b000;`
265			`parameter[2:0] DECR_0 =3'b000;`
266			`parameter[2:0] INCR_1 =3'b001;`
267			`parameter[2:0] INCR_2 =3'b010;`
268			`parameter[2:0] INCR_4 =3'b011;`
269			`parameter[2:0] DECR_1 =3'b101;`
270			`parameter[2:0] DECR_2 =3'b110;`
271			`parameter[2:0] DECR_4 =3'b111;`
272
273			`parameter[4:0] R0 =5'd0;`
274			`parameter[4:0] R1 =5'd1;`
275			`parameter[4:0] R2 =5'd2;`
276			`parameter[4:0] R3 =5'd3;`
277			`parameter[4:0] R4 =5'd4;`
278			`parameter[4:0] R5 =5'd5;`
279			`parameter[4:0] R6 =5'd6;`
280			`parameter[4:0] R7 =5'd7;`
281			`parameter[4:0] R8 =5'd8;`
282			`parameter[4:0] R9 =5'd9;`
283			`parameter[4:0] R10 =5'd10;`
284			`parameter[4:0] R11 =5'd11;`
285			`parameter[4:0] R12 =5'd12;`
286			`parameter[4:0] R13 =5'd13;`
287			`parameter[4:0] R14 =5'd14;`
288			`parameter[4:0] R15 =5'd15;`
289			`parameter[4:0] R16 =5'd16;`
290			`parameter[4:0] R17 =5'd17;`
291			`parameter[4:0] R18 =5'd18;`
292			`parameter[4:0] R19 =5'd19;`
293			`parameter[4:0] R20 =5'd20;`
294			`parameter[4:0] R21 =5'd21;`
295			`parameter[4:0] R22 =5'd22;`
296			`parameter[4:0] R23 =5'd23;`
297			`parameter[4:0] R24 =5'd24;`
298			`parameter[4:0] R25 =5'd25;`
299			`parameter[4:0] R26 =5'd26;`
300			`parameter[4:0] R27 =5'd27;`
301			`parameter[4:0] R28 =5'd28;`
302			`parameter[4:0] R29 =5'd29;`
303			`parameter[4:0] R30 =5'd30;`
304			`parameter[4:0] R31 =5'd31;`
305
306			`endpackage`
307
308			`endif