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URL https://opencores.org/ocsvn/qrisc32/qrisc32/trunk

Subversion Repositories qrisc32

[/] [qrisc32/] [trunk/] [run_sim.tcl] - Blame information for rev 3

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Line No. Rev Author Line
1 3 vinogradov
vlib work
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vmap work work
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alias com {
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vlog -sv "./mem.sv"
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vlog -sv "./package.sv"
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vlog -sv "./qrisc32_EX.sv"
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vlog -sv "./qrisc32_ID.sv"
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vlog -sv "./qrisc32_IF.sv"
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vlog -sv "./qrisc32_MEM.sv"
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vlog -sv "./qrisc32.sv"
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vlog -sv "./qrisc32_TB.sv"
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}
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alias tb_run {
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vsim -novopt work.qrisc32_tb
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /qrisc32_tb/UUT/clk
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/reset
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add wave -noupdate -divider {pipe stalled}
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add wave -noupdate /qrisc32_tb/UUT/pipe_stall
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add wave -noupdate -divider {Instruction bus}
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_instructions_data
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_instructions_addr
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_instructions_rd
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_instructions_wait_req
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add wave -noupdate -divider {Data Read Bus}
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_datar_data
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_datar_addr
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_datar_rd
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_datar_wait_req
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add wave -noupdate -divider {Data Write Bus}
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_dataw_data
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_dataw_addr
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_dataw_wr
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/avm_dataw_wait_req
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add wave -noupdate -divider Registers
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add wave -noupdate -radix hexadecimal /qrisc32_tb/UUT/qrisc32_ID/rf
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run -all
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}
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echo "For compile type command com"
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echo "For run simulation type command tb_run"
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