OpenCores
URL https://opencores.org/ocsvn/qspiflash/qspiflash/trunk

Subversion Repositories qspiflash

[/] [qspiflash/] [trunk/] [bench/] [cpp/] [eqspiflashsim.cpp] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    eqspiflashsim.cpp
4
//
5
// Project:     OpenArty, an entirely open SoC based upon the Arty platform
6
//
7
// Purpose:     This library simulates the operation of a Quad-SPI commanded
8
//              flash, such as the Micron N25Q128A used on the Arty development
9
//              board by Digilent.  As such, it is defined by 16 MBytes of
10
//              memory (4 MWord).
11
//
12
//              This simulator is useful for testing in a Verilator/C++
13
//              environment, where this simulator can be used in place of
14
//              the actual hardware.
15
//
16
// Creator:     Dan Gisselquist, Ph.D.
17
//              Gisselquist Technology, LLC
18
//
19
////////////////////////////////////////////////////////////////////////////////
20
//
21
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
22
//
23
// This program is free software (firmware): you can redistribute it and/or
24
// modify it under the terms of  the GNU General Public License as published
25
// by the Free Software Foundation, either version 3 of the License, or (at
26
// your option) any later version.
27
//
28
// This program is distributed in the hope that it will be useful, but WITHOUT
29
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
30
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
31
// for more details.
32
//
33
// You should have received a copy of the GNU General Public License along
34
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
35
// target there if the PDF file isn't present.)  If not, see
36
// <http://www.gnu.org/licenses/> for a copy.
37
//
38
// License:     GPL, v3, as defined and found on www.gnu.org,
39
//              http://www.gnu.org/licenses/gpl.html
40
//
41
//
42
////////////////////////////////////////////////////////////////////////////////
43
//
44
//
45
#include <stdio.h>
46
#include <string.h>
47
#include <assert.h>
48
#include <stdlib.h>
49
 
50
#include "eqspiflashsim.h"
51
 
52
#define MEMBYTES        (1<<24)
53
 
54
static  const unsigned
55
        DEVESD = 0x014,
56
        // MICROSECONDS = 200,
57
        // MILLISECONDS = MICROSECONDS * 1000,
58
        // SECONDS = MILLISECONDS * 1000,
59
        MICROSECONDS = 20,
60
        MILLISECONDS = MICROSECONDS * 10,
61
        SECONDS = MILLISECONDS * 10,
62
        tSHSL1 =    4, // S# deselect time after a read command
63
        tSHSL2 =   10, // S# deselect time after a non-read command
64
        tW     =   1300 * MICROSECONDS, // write config cycle time
65
        tWNVCR =    200 * MILLISECONDS, // write nonvolatile-config cycle time
66
        tWVECR =    8, // write volatile enhanced config cycle time
67
        tBE    =   32 * SECONDS,        // Bulk erase time
68
        tDP    =   10 * SECONDS,        // Deep power down
69
        tRES   =   30 * SECONDS,
70
// Shall we artificially speed up this process?
71
// These numbers are the "typical" times
72
        tPP    = 500 * MICROSECONDS,    // Page program time
73
        tSE    = 700 * MILLISECONDS,    // Sector erase time
74
        tSS    = 250 * MILLISECONDS;    // Subsector erase time
75
// These are the maximum times
76
        // tW     = 8300 * MICROSECONDS, // write config cycle time
77
        // tWNVCR = 3000 * MILLISECONDS, // write nonvolatile-config cycle time
78
        // tWVECR =    8, // write volatile enhanced config cycle time
79
        // tPP    = 5000 * MICROSECONDS,
80
        // tSE    = 3000 * MILLISECONDS;
81
        // tSS    =  800 * MILLISECONDS;
82
 
83
static  const   char    IDSTR[20]= {
84
                0x20,           // Micron's ID, assigned by JEDEC
85
                (char)0xba, (char)0x18, // Memory type and capacity
86
                (char)0x10,             // Length of data to follow
87
                (char)0xfe, (char)0xfd, // Extended device ID and device config info
88
                (char)0xfc, (char)0xfb, (char)0xfa, (char)0xf9,
89
                (char)0xf8, (char)0xf7, (char)0xf6, (char)0xf5,
90
                (char)0xf4, (char)0xf3, (char)0xf2, (char)0xf1,
91
                (char)0xf0, (char)0xef
92
        };
93
 
94
EQSPIFLASHSIM::EQSPIFLASHSIM(void) {
95
        const   int     NSECTORS = MEMBYTES>>16;
96
        m_mem = new char[MEMBYTES];
97
        m_pmem = new char[256];
98
        m_otp  = new char[65];
99
        for(int i=0; i<65; i++)
100
                m_otp[i] = 0x0ff;
101
        m_otp[64] = 1;
102
        m_otp_wp = false;
103
        m_lockregs = new char[NSECTORS];
104
        for(int i=0; i<NSECTORS; i++)
105
                m_lockregs[i] = 0;
106
 
107
        m_state = EQSPIF_IDLE;
108
        m_last_sck = 1;
109
        m_write_count = 0;
110
        m_ireg = m_oreg = 0;
111
        m_sreg = 0x01c;
112
        m_creg = 0x001; // Initial creg on delivery
113
        m_config   = 0x7; // Volatile configuration register
114
        m_nvconfig = 0x0fff; // Nonvolatile configuration register
115
        m_quad_mode = false;
116
        m_mode_byte = 0;
117
        m_flagreg = 0x0a5;
118
 
119
        m_debug = true;
120
 
121
        memset(m_mem, 0x0ff, MEMBYTES);
122
}
123
 
124
void    EQSPIFLASHSIM::load(const unsigned addr, const char *fname) {
125
        FILE    *fp;
126
        size_t  len;
127
 
128
        if (addr >= MEMBYTES)
129
                return; // return void
130
        len = MEMBYTES-addr*4;
131
 
132
        if (NULL != (fp = fopen(fname, "r"))) {
133
                int     nr = 0;
134
                nr = fread(&m_mem[addr*4], sizeof(char), len, fp);
135
                fclose(fp);
136
                if (nr == 0) {
137
                        fprintf(stderr, "SPI-FLASH: Could not read %s\n", fname);
138
                        perror("O/S Err:");
139
                }
140
        } else {
141
                fprintf(stderr, "SPI-FLASH: Could not open %s\n", fname);
142
                perror("O/S Err:");
143
        }
144
}
145
 
146
#define QOREG(A)        m_oreg = ((m_oreg & (~0x0ff))|(A&0x0ff))
147
 
148
int     EQSPIFLASHSIM::operator()(const int csn, const int sck, const int dat) {
149
        // Keep track of a timer to determine when page program and erase
150
        // cycles complete.
151
 
152
        if (m_write_count > 0) {
153
                if (0 == (--m_write_count)) {// When done with erase/page pgm,
154
                        // Clear the write in progress bit, together with the
155
                        // write enable bit.
156
                        m_sreg &= 0x0fc;
157
                        if (m_debug) printf("Write complete, clearing WIP (inside SIM)\n");
158
                }
159
        }
160
 
161
        if (csn) {
162
                m_last_sck = 1;
163
                m_ireg = 0; m_oreg = 0;
164
 
165
                if ((EQSPIF_PP == m_state)||(EQSPIF_QPP == m_state)) {
166
                        // Start a page program
167
                        if (m_debug) printf("EQSPI: Page Program write cycle begins\n");
168
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
169
                        if (m_debug) printf("EQSPI: pmem = %08lx\n", (unsigned long)m_pmem);
170
                        assert((m_lockregs[(m_addr>>16)&0x0ff]&0x1)==0);
171
                        assert((m_count & 7)==0);
172
                        m_write_count = tPP;
173
                        m_state = EQSPIF_IDLE;
174
                        m_sreg &= (~EQSPIF_WEL_FLAG);
175
                        m_sreg |= (EQSPIF_WIP_FLAG);
176
                        for(int i=0; i<256; i++) {
177
                                /*
178
                                if (m_debug) printf("%02x: m_mem[%02x] = %02x &= %02x = %02x\n",
179
                                        i, (m_addr&(~0x0ff))+i,
180
                                        m_mem[(m_addr&(~0x0ff))+i]&0x0ff, m_pmem[i]&0x0ff,
181
                                        m_mem[(m_addr&(~0x0ff))+i]& m_pmem[i]&0x0ff);
182
                                */
183
                                m_mem[(m_addr&(~0x0ff))+i] &= m_pmem[i];
184
                        }
185
                        m_quad_mode = false;
186
                } else if (EQSPIF_WRCR == m_state) {
187
                        if (m_debug) printf("Actually writing volatile config register\n");
188
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
189
                        m_state = EQSPIF_IDLE;
190
                } else if (EQSPIF_WRNVCONFIG == m_state) {
191
                        if (m_debug) printf("Actually writing nonvolatile config register\n");
192
                        m_write_count = tWNVCR;
193
                        m_state = EQSPIF_IDLE;
194
                } else if (EQSPIF_WREVCONFIG == m_state) {
195
                        if (m_debug) printf("Actually writing Enhanced volatile config register\n");
196
                        m_state = EQSPIF_IDLE;
197
                } else if (EQSPIF_WRSR == m_state) {
198
                        if (m_debug) printf("Actually writing status register\n");
199
                        m_write_count = tW;
200
                        m_state = EQSPIF_IDLE;
201
                        m_sreg &= (~EQSPIF_WEL_FLAG);
202
                        m_sreg |= (EQSPIF_WIP_FLAG);
203
                } else if (EQSPIF_WRLOCK == m_state) {
204
                        if (m_debug) printf("Actually writing lock register\n");
205
                        m_write_count = tW;
206
                        m_state = EQSPIF_IDLE;
207
                } else if (EQSPIF_CLRFLAGS == m_state) {
208
                        if (m_debug) printf("Actually clearing the flags register bits\n");
209
                        m_state = EQSPIF_IDLE;
210
                        m_flagreg &= 0x09f;
211
                } else if (m_state == EQSPIF_SUBSECTOR_ERASE) {
212
                        if (m_debug) printf("Actually Erasing subsector, from %08x\n", m_addr);
213
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
214
                        assert(((m_count & 7)==0)&&(m_count == 32));
215
                        assert((m_lockregs[(m_addr>>16)&0x0ff]&0x1)==0);
216
                        m_write_count = tSS;
217
                        m_state = EQSPIF_IDLE;
218
                        m_sreg &= (~EQSPIF_WEL_FLAG);
219
                        m_sreg |= (EQSPIF_WIP_FLAG);
220
                        m_addr &= (-1<<12);
221
                        for(int i=0; i<(1<<12); i++)
222
                                m_mem[m_addr + i] = 0x0ff;
223
                        if (m_debug) printf("Now waiting %d ticks delay\n", m_write_count);
224
                } else if (m_state == EQSPIF_SECTOR_ERASE) {
225
                        if (m_debug) printf("Actually Erasing sector, from %08x\n", m_addr);
226
                        m_write_count = tSE;
227
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
228
                        assert(((m_count & 7)==0)&&(m_count == 32));
229
                        assert((m_lockregs[(m_addr>>16)&0x0ff]&0x1)==0);
230
                        m_state = EQSPIF_IDLE;
231
                        m_sreg &= (~EQSPIF_WEL_FLAG);
232
                        m_sreg |= (EQSPIF_WIP_FLAG);
233
                        m_addr &= (-1<<16);
234
                        for(int i=0; i<(1<<16); i++)
235
                                m_mem[m_addr + i] = 0x0ff;
236
                        if (m_debug) printf("Now waiting %d ticks delay\n", m_write_count);
237
                } else if (m_state == EQSPIF_BULK_ERASE) {
238
                        m_write_count = tBE;
239
                        m_state = EQSPIF_IDLE;
240
                        m_sreg &= (~EQSPIF_WEL_FLAG);
241
                        m_sreg |= (EQSPIF_WIP_FLAG);
242
                        // Should I be checking the lock register(s) here?
243
                        for(int i=0; i<MEMBYTES; i++)
244
                                m_mem[i] = 0x0ff;
245
                } else if (m_state == EQSPIF_PROGRAM_OTP) {
246
                        // Program the One-Time Programmable (OTP memory
247
                        if (m_debug) printf("EQSPI: OTP Program write cycle begins\n");
248
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
249
                        // assert((m_lockregs[(m_addr>>16)&0x0ff]&0x1)==0);
250
                        assert((m_count & 7)==0);
251
                        m_write_count = tPP; // OTP cycle time as well
252
                        m_state = EQSPIF_IDLE;
253
                        m_sreg &= (~EQSPIF_WEL_FLAG);
254
                        m_sreg |= (EQSPIF_WIP_FLAG);
255
                        for(int i=0; i<65; i++)
256
                                m_otp[i] &= m_pmem[i];
257
                        m_otp_wp = ((m_otp[64]&1)==0);
258
                /*
259
                } else if (m_state == EQSPIF_DEEP_POWER_DOWN) {
260
                        m_write_count = tDP;
261
                        m_state = EQSPIF_IDLE;
262
                } else if (m_state == EQSPIF_RELEASE) {
263
                        m_write_count = tRES;
264
                        m_state = EQSPIF_IDLE;
265
                */
266
                } else if (m_state == EQSPIF_QUAD_READ_CMD) {
267
                        m_state = EQSPIF_IDLE;
268
                        if (m_mode_byte!=0)
269
                                m_quad_mode = false;
270
                        else
271
                                m_state = EQSPIF_XIP;
272
                } else if (m_state == EQSPIF_QUAD_READ) {
273
                        m_state = EQSPIF_IDLE;
274
                        if (m_mode_byte!=0)
275
                                m_quad_mode = false;
276
                        else
277
                                m_state = EQSPIF_XIP;
278
                // } else if (m_state == EQSPIF_XIP) {
279
                }
280
 
281
                m_oreg = 0x0fe;
282
                m_count= 0;
283
                int out = m_nxtout[3];
284
                m_nxtout[3] = m_nxtout[2];
285
                m_nxtout[2] = m_nxtout[1];
286
                m_nxtout[1] = m_nxtout[0];
287
                m_nxtout[0] = dat;
288
                return out;
289
        } else if ((!m_last_sck)||(sck == m_last_sck)) {
290
                // Only change on the falling clock edge
291
                // printf("SFLASH-SKIP, CLK=%d -> %d\n", m_last_sck, sck);
292
                m_last_sck = sck;
293
                int out = m_nxtout[3];
294
                m_nxtout[3] = m_nxtout[2];
295
                m_nxtout[2] = m_nxtout[1];
296
                m_nxtout[1] = m_nxtout[0];
297
                if (m_quad_mode)
298
                        m_nxtout[0] = (m_oreg>>8)&0x0f;
299
                else
300
                        // return ((m_oreg & 0x0100)?2:0) | (dat & 0x0d);
301
                        m_nxtout[0] = (m_oreg & 0x0100)?2:0;
302
                return out;
303
        }
304
 
305
        // We'll only get here if ...
306
        //      last_sck = 1, and sck = 0, thus transitioning on the
307
        //      negative edge as with everything else in this interface
308
        if (m_quad_mode) {
309
                m_ireg = (m_ireg << 4) | (dat & 0x0f);
310
                m_count+=4;
311
                m_oreg <<= 4;
312
        } else {
313
                m_ireg = (m_ireg << 1) | (dat & 1);
314
                m_count++;
315
                m_oreg <<= 1;
316
        }
317
 
318
 
319
        // printf("PROCESS, COUNT = %d, IREG = %02x\n", m_count, m_ireg);
320
        if (m_state == EQSPIF_XIP) {
321
                assert(m_quad_mode);
322
                if (m_count == 24) {
323
                        if (m_debug) printf("EQSPI: Entering from Quad-Read Idle to Quad-Read\n");
324
                        if (m_debug) printf("EQSPI: QI/O Idle Addr = %02x\n", m_ireg&0x0ffffff);
325
                        m_addr = (m_ireg) & 0x0ffffff;
326
                        assert((m_addr & 0xfc00000)==0);
327
                        m_state = EQSPIF_QUAD_READ;
328
                } m_oreg = 0;
329
        } else if (m_count == 8) {
330
                QOREG(0x0a5);
331
                // printf("SFLASH-CMD = %02x\n", m_ireg & 0x0ff);
332
                // Figure out what command we've been given
333
                if (m_debug) printf("SPI FLASH CMD %02x\n", m_ireg&0x0ff);
334
                switch(m_ireg & 0x0ff) {
335
                case 0x01: // Write status register
336
                        if (2 !=(m_sreg & 0x203)) {
337
                                if (m_debug) printf("EQSPI: WEL not set, cannot write status reg\n");
338
                                m_state = EQSPIF_INVALID;
339
                        } else
340
                                m_state = EQSPIF_WRSR;
341
                        break;
342
                case 0x02: // Normal speed (normal SPI, 1wire MOSI) Page program
343
                        if (2 != (m_sreg & 0x203)) {
344
                                if (m_debug) printf("EQSPI: Cannot program at this time, SREG = %x\n", m_sreg);
345
                                m_state = EQSPIF_INVALID;
346
                        } else {
347
                                m_state = EQSPIF_PP;
348
                                if (m_debug) printf("PAGE-PROGRAM COMMAND ACCEPTED\n");
349
                        }
350
                        break;
351
                case 0x03: // Read data bytes
352
                        // Our clock won't support this command, so go
353
                        // to an invalid state
354
                        if (m_debug) printf("EQSPI INVALID: This sim does not support slow reading\n");
355
                        m_state = EQSPIF_INVALID;
356
                        break;
357
                case 0x04: // Write disable
358
                        m_state = EQSPIF_IDLE;
359
                        m_sreg &= (~EQSPIF_WEL_FLAG);
360
                        break;
361
                case 0x05: // Read status register
362
                        m_state = EQSPIF_RDSR;
363
                        if (m_debug) printf("EQSPI: READING STATUS REGISTER: %02x\n", m_sreg);
364
                        QOREG(m_sreg);
365
                        break;
366
                case 0x06: // Write enable
367
                        m_state = EQSPIF_IDLE;
368
                        m_sreg |= EQSPIF_WEL_FLAG;
369
                        if (m_debug) printf("EQSPI: WRITE-ENABLE COMMAND ACCEPTED\n");
370
                        break;
371
                case 0x0b: // Here's the read that we support
372
                        if (m_debug) printf("EQSPI: FAST-READ (single-bit)\n");
373
                        m_state = EQSPIF_FAST_READ;
374
                        break;
375
                case 0x20: // Subsector Erase
376
                        if (2 != (m_sreg & 0x203)) {
377
                                if (m_debug) printf("EQSPI: WEL not set, cannot do a subsector erase\n");
378
                                m_state = EQSPIF_INVALID;
379
                                assert(0&&"WEL not set");
380
                        } else
381
                                m_state = EQSPIF_SUBSECTOR_ERASE;
382
                        break;
383
                case 0x32: // QUAD Page program, 4 bits at a time
384
                        if (2 != (m_sreg & 0x203)) {
385
                                if (m_debug) printf("EQSPI: Cannot program at this time, SREG = %x\n", m_sreg);
386
                                m_state = EQSPIF_INVALID;
387
                                assert(0&&"WEL not set");
388
                        } else {
389
                                m_state = EQSPIF_QPP;
390
                                if (m_debug) printf("EQSPI: QUAD-PAGE-PROGRAM COMMAND ACCEPTED\n");
391
                                if (m_debug) printf("EQSPI: pmem = %08lx\n", (unsigned long)m_pmem);
392
                        }
393
                        break;
394
                case 0x42: // Program OTP array
395
                        if (2 != (m_sreg & 0x203)) {
396
                                if (m_debug) printf("EQSPI: WEL not set, cannot program OTP\n");
397
                                m_state = EQSPIF_INVALID;
398
                        } else if (m_otp_wp) {
399
                                if (m_debug) printf("EQSPI: OTP Write protect is set, cannot program OTP ever again\n");
400
                                m_state = EQSPIF_INVALID;
401
                        } else
402
                                m_state = EQSPIF_PROGRAM_OTP;
403
                        break;
404
                case 0x4b: // Read OTP array
405
                        m_state = EQSPIF_READ_OTP;
406
                        QOREG(0);
407
                        if (m_debug) printf("EQSPI: Read OTP array command\n");
408
                        break;
409
                case 0x50: // Clear flag status register
410
                        m_state = EQSPIF_CLRFLAGS;
411
                        if (m_debug) printf("EQSPI: Clearing FLAGSTATUS REGISTER: %02x\n", m_flagreg);
412
                        QOREG(m_flagreg);
413
                        break;
414
                case 0x61: // WRITE Enhanced volatile config register
415
                        m_state = EQSPIF_WREVCONFIG;
416
                        if (m_debug) printf("EQSPI: WRITING EVCONFIG REGISTER\n");
417
                        break;
418
                case 0x65: // Read Enhanced volatile config register
419
                        m_state = EQSPIF_RDEVCONFIG;
420
                        if (m_debug) printf("EQSPI: READING EVCONFIG REGISTER: %02x\n", m_evconfig);
421
                        QOREG(m_evconfig);
422
                        break;
423
                case 0x06b:
424
                        m_state = EQSPIF_QUAD_READ_CMD;
425
                        // m_quad_mode = true; // Not yet, need to wait past dummy registers
426
                        break;
427
                case 0x70: // Read flag status register
428
                        m_state = EQSPIF_RDFLAGS;
429
                        if (m_debug) printf("EQSPI: READING FLAGSTATUS REGISTER: %02x\n", m_flagreg);
430
                        QOREG(m_flagreg);
431
                        break;
432
                case 0x81: // Write volatile config register
433
                        m_state = EQSPIF_WRCR;
434
                        if (m_debug) printf("EQSPI: WRITING CONFIG REGISTER: %02x\n", m_config);
435
                        break;
436
                case 0x85: // Read volatile config register
437
                        m_state = EQSPIF_RDCR;
438
                        if (m_debug) printf("EQSPI: READING CONFIG REGISTER: %02x\n", m_config);
439
                        QOREG(m_config>>8);
440
                        break;
441
                case 0x9e: // Read ID (fall through)
442
                case 0x9f: // Read ID
443
                        m_state = EQSPIF_RDID; m_addr = 0;
444
                        if (m_debug) printf("EQSPI: READING ID\n");
445
                        QOREG(IDSTR[0]);
446
                        break;
447
                case 0xb1: // Write nonvolatile config register
448
                        m_state = EQSPIF_WRNVCONFIG;
449
                        if (m_debug) printf("EQSPI: WRITING NVCONFIG REGISTER: %02x\n", m_nvconfig);
450
                        break;
451
                case 0xb5: // Read nonvolatile config register
452
                        m_state = EQSPIF_RDNVCONFIG;
453
                        if (m_debug) printf("EQSPI: READING NVCONFIG REGISTER: %02x\n", m_nvconfig);
454
                        QOREG(m_nvconfig>>8);
455
                        break;
456
                case 0xc7: // Bulk Erase
457
                        if (2 != (m_sreg & 0x203)) {
458
                                if (m_debug) printf("EQSPI: WEL not set, cannot erase device\n");
459
                                m_state = EQSPIF_INVALID;
460
                        } else
461
                                m_state = EQSPIF_BULK_ERASE;
462
                        break;
463
                case 0xd8: // Sector Erase
464
                        if (2 != (m_sreg & 0x203)) {
465
                                if (m_debug) printf("EQSPI: WEL not set, cannot erase sector\n");
466
                                m_state = EQSPIF_INVALID;
467
                                assert(0&&"WEL not set");
468
                        } else {
469
                                m_state = EQSPIF_SECTOR_ERASE;
470
                                if (m_debug) printf("EQSPI: SECTOR_ERASE COMMAND\n");
471
                        }
472
                        break;
473
                case 0xe5: // Write lock register
474
                        m_state = EQSPIF_WRLOCK;
475
                        if (m_debug) printf("EQSPI: WRITING LOCK REGISTER\n");
476
                        break;
477
                case 0xe8: // Read lock register
478
                        m_state = EQSPIF_RDLOCK;
479
                        if (m_debug) printf("EQSPI: READ LOCK REGISTER (Waiting on address)\n");
480
                        break;
481
                case 0x0eb: // Here's the (other) read that we support
482
                        // printf("EQSPI: QUAD-I/O-READ\n");
483
                        // m_state = EQSPIF_QUAD_READ_CMD;
484
                        // m_quad_mode = true;
485
                        assert(0 && "Quad Input/Output fast read not supported");
486
                        break;
487
                default:
488
                        printf("EQSPI: UNRECOGNIZED SPI FLASH CMD: %02x\n", m_ireg&0x0ff);
489
                        m_state = EQSPIF_INVALID;
490
                        assert(0 && "Unrecognized command\n");
491
                        break;
492
                }
493
        } else if ((0 == (m_count&0x07))&&(m_count != 0)) {
494
                QOREG(0);
495
                switch(m_state) {
496
                case EQSPIF_IDLE:
497
                        printf("TOO MANY CLOCKS, SPIF in IDLE\n");
498
                        break;
499
                case EQSPIF_WRSR:
500
                        if (m_count == 16) {
501
                                m_sreg = (m_sreg & 0x07c) | (m_ireg & 0x07c);
502
                                if (m_debug) printf("Request to set sreg to 0x%02x\n",
503
                                        m_ireg&0x0ff);
504
                        } else {
505
                                printf("TOO MANY CLOCKS FOR WRR!!!\n");
506
                                exit(-2);
507
                                m_state = EQSPIF_IDLE;
508
                        }
509
                        break;
510
                case EQSPIF_WRCR: // Write volatile config register, 0x81
511
                        if (m_count == 8) {
512
                                m_config = m_ireg & 0x0ff;
513
                                printf("Setting volatile config register to %08x\n", m_config);
514
                                assert((m_config & 0xfb)==0x8b);
515
                        } break;
516
                case EQSPIF_WRNVCONFIG: // Write nonvolatile config register
517
                        if (m_count == 8) {
518
                                m_nvconfig = m_ireg & 0x0ffdf;
519
                                printf("Setting nonvolatile config register to %08x\n", m_config);
520
                                assert((m_nvconfig & 0xffc5)==0x8fc5);
521
                        } break;
522
                case EQSPIF_WREVCONFIG: // Write enhanced volatile config reg
523
                        if (m_count == 8) {
524
                                m_evconfig = m_ireg & 0x0ff;
525
                                printf("Setting enhanced volatile config register to %08x\n", m_evconfig);
526
                                assert((m_evconfig & 0x0d7)==0xd7);
527
                        } break;
528
                case EQSPIF_WRLOCK:
529
                        if (m_count == 32) {
530
                                m_addr = (m_ireg>>24)&0x0ff;
531
                                if ((m_lockregs[m_addr]&2)==0)
532
                                        m_lockregs[m_addr] = m_ireg&3;
533
                                printf("Setting lock register[%02x] to %d\n", m_addr, m_lockregs[m_addr]);
534
                                assert((m_config & 0xfb)==0x8b);
535
                        } break;
536
                case EQSPIF_RDLOCK:
537
                        if (m_count == 24) {
538
                                m_addr = (m_ireg>>16)&0x0ff;
539
                                QOREG(m_lockregs[m_addr]);
540
                                printf("Reading lock register[%02x]: %d\n", m_addr, m_lockregs[m_addr]);
541
                        } else
542
                                QOREG(m_lockregs[m_addr]);
543
                        break;
544
                case EQSPIF_CLRFLAGS:
545
                        assert(0 && "Too many clocks for CLSR command!!\n");
546
                        break;
547
                case EQSPIF_READ_OTP:
548
                        if (m_count == 32) {
549
                                m_addr = m_ireg & 0x0ffffff;
550
                                assert(m_addr < 65);
551
                                m_otp[64] = (m_otp_wp)?0:1;
552
 
553
                                if (m_debug) printf("READOTP, SETTING ADDR = %08x (%02x:%02x:%02x:%02x)\n", m_addr,
554
                                        ((m_addr<65)?m_otp[m_addr]:0)&0x0ff,
555
                                        ((m_addr<64)?m_otp[m_addr+1]:0)&0x0ff,
556
                                        ((m_addr<63)?m_otp[m_addr+2]:0)&0x0ff,
557
                                        ((m_addr<62)?m_otp[m_addr+3]:0)&0x0ff);
558
                                if (m_debug) printf("READOTP, Array is %s, m_otp[64] = %d\n",
559
                                        (m_otp_wp)?"Locked":"Unlocked",
560
                                        m_otp[64]);
561
                                QOREG(m_otp[m_addr]);
562
                        } else if (m_count < 40) {
563
                        } // else if (m_count == 40)
564
                        else if ((m_count&7)==0) {
565
                                if (m_debug) printf("READOTP, ADDR = %08x\n", m_addr);
566
                                if (m_addr < 65)
567
                                        QOREG(m_otp[m_addr]);
568
                                else
569
                                        QOREG(0);
570
                                if (m_debug) printf("EQSPI: READING OTP, %02x%s\n",
571
                                        (m_addr<65)?m_otp[m_addr]&0x0ff:0xfff,
572
                                        (m_addr > 65)?"-- PAST OTP LENGTH!":"");
573
                                m_addr++;
574
                        }
575
                        break;
576
                case EQSPIF_RDID:
577
                        if ((m_count&7)==0) {
578
                                m_addr++;
579
                                if (m_debug) printf("READID, ADDR = %08x\n", m_addr);
580
                                if (m_addr < sizeof(IDSTR))
581
                                        QOREG(IDSTR[m_addr]);
582
                                else
583
                                        QOREG(0);
584
                                if (m_debug) printf("EQSPI: READING ID, %02x%s\n",
585
                                        IDSTR[m_addr]&0x0ff,
586
                                        (m_addr >= sizeof(IDSTR))?"-- PAST ID LENGTH!":"");
587
                        }
588
                        break;
589
                case EQSPIF_RDSR:
590
                        // printf("Read SREG = %02x, wait = %08x\n", m_sreg,
591
                                // m_write_count);
592
                        QOREG(m_sreg);
593
                        break;
594
                case EQSPIF_RDCR:
595
                        if (m_debug) printf("Read CREG = %02x\n", m_creg);
596
                        QOREG(m_creg);
597
                        break;
598
                case EQSPIF_FAST_READ:
599
                        if (m_count < 32) {
600
                                if (m_debug) printf("FAST READ, WAITING FOR FULL COMMAND (count = %d)\n", m_count);
601
                                QOREG(0x0c3);
602
                        } else if (m_count == 32) {
603
                                m_addr = m_ireg & 0x0ffffff;
604
                                if (m_debug) printf("FAST READ, ADDR = %08x\n", m_addr);
605
                                QOREG(0x0c3);
606
                                assert((m_addr & 0xf000003)==0);
607
                        } else if ((m_count >= 40)&&(0 == (m_sreg&0x01))) {
608
                                if (m_count == 40)
609
                                        printf("DUMMY BYTE COMPLETE ...\n");
610
                                QOREG(m_mem[m_addr++]);
611
                                if (m_debug) printf("SPIF[%08x] = %02x -> %02x\n", m_addr-1, m_mem[m_addr-1]&0x0ff, m_oreg);
612
                        } else if (0 != (m_sreg&0x01)) {
613
                                m_oreg = 0;
614
                                if (m_debug) printf("CANNOT READ WHEN WRITE IN PROGRESS, m_sreg = %02x\n", m_sreg);
615
                        } else printf("How did I get here, m_count = %d\n", m_count);
616
                        break;
617
                case EQSPIF_QUAD_READ_CMD:
618
                        // The command to go into quad read mode took 8 bits
619
                        // that changes the timings, else we'd use quad_Read
620
                        // below
621
                        if (m_count == 32) {
622
                                m_addr = m_ireg & 0x0ffffff;
623
                                // printf("FAST READ, ADDR = %08x\n", m_addr);
624
                                printf("EQSPI: QUAD READ, ADDR = %06x (%02x:%02x:%02x:%02x)\n", m_addr,
625
                                        (m_addr<0x1000000)?(m_mem[m_addr]&0x0ff):0,
626
                                        (m_addr<0x0ffffff)?(m_mem[m_addr+1]&0x0ff):0,
627
                                        (m_addr<0x0fffffe)?(m_mem[m_addr+2]&0x0ff):0,
628
                                        (m_addr<0x0fffffd)?(m_mem[m_addr+3]&0x0ff):0);
629
                                assert((m_addr & (~(MEMBYTES-1)))==0);
630
                        } else if (m_count == 32+8) {
631
                                QOREG(m_mem[m_addr++]);
632
                                m_quad_mode = true;
633
                                m_mode_byte = (m_ireg & 0x080);
634
                                printf("EQSPI: (QUAD) MODE BYTE = %02x\n", m_mode_byte);
635
                        } else if ((m_count > 32+8)&&(0 == (m_sreg&0x01))) {
636
                                QOREG(m_mem[m_addr++]);
637
                                // printf("EQSPIF[%08x]/QR = %02x\n",
638
                                        // m_addr-1, m_oreg);
639
                        } else {
640
                                printf("ERR: EQSPIF--TRYING TO READ WHILE BUSY! (count = %d)\n", m_count);
641
                                m_oreg = 0;
642
                        }
643
                        break;
644
                case EQSPIF_QUAD_READ:
645
                        if (m_count == 24+8*4) {// Requires 8 QUAD clocks
646
                                m_mode_byte = (m_ireg>>24) & 0x10;
647
                                printf("EQSPI/QR: MODE BYTE = %02x\n", m_mode_byte);
648
                                QOREG(m_mem[m_addr++]);
649
                        } else if ((m_count >= 64)&&(0 == (m_sreg&0x01))) {
650
                                QOREG(m_mem[m_addr++]);
651
                                printf("EQSPIF[%08x]/QR = %02x\n", m_addr-1, m_oreg & 0x0ff);
652
                        } else {
653
                                m_oreg = 0;
654
                                printf("EQSPI/QR ... m_count = %d\n", m_count);
655
                        }
656
                        break;
657
                case EQSPIF_PP:
658
                        if (m_count == 32) {
659
                                m_addr = m_ireg & 0x0ffffff;
660
                                if (m_debug) printf("EQSPI: PAGE-PROGRAM ADDR = %06x\n", m_addr);
661
                                assert((m_addr & 0xfc00000)==0);
662
                                // m_page = m_addr >> 8;
663
                                for(int i=0; i<256; i++)
664
                                        m_pmem[i] = 0x0ff;
665
                        } else if (m_count >= 40) {
666
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
667
                                // printf("EQSPI: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
668
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
669
                        } break;
670
                case EQSPIF_QPP:
671
                        if (m_count == 32) {
672
                                m_addr = m_ireg & 0x0ffffff;
673
                                m_quad_mode = true;
674
                                if (m_debug) printf("EQSPI/QR: PAGE-PROGRAM ADDR = %06x\n", m_addr);
675
                                assert((m_addr & 0xfc00000)==0);
676
                                // m_page = m_addr >> 8;
677
                                for(int i=0; i<256; i++)
678
                                        m_pmem[i] = 0x0ff;
679
                        } else if (m_count >= 40) {
680
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
681
                                // printf("EQSPI/QR: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
682
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
683
                        } break;
684
                case EQSPIF_SUBSECTOR_ERASE:
685
                        if (m_count == 32) {
686
                                m_addr = m_ireg & 0x0fff000;
687
                                if (m_debug) printf("SUBSECTOR_ERASE ADDRESS = %08x\n", m_addr);
688
                                assert((m_addr & 0xff000000)==0);
689
                        } break;
690
                case EQSPIF_SECTOR_ERASE:
691
                        if (m_count == 32) {
692
                                m_addr = m_ireg & 0x0ff0000;
693
                                if (m_debug) printf("SECTOR_ERASE ADDRESS = %08x\n", m_addr);
694
                                assert((m_addr & 0xf000000)==0);
695
                        } break;
696
                case EQSPIF_PROGRAM_OTP:
697
                        if (m_count == 32) {
698
                                m_addr = m_ireg & 0x0ff;
699
                                for(int i=0; i<65; i++)
700
                                        m_pmem[i] = 0x0ff;
701
                        } else if ((m_count >= 40)&&(m_addr < 65)) {
702
                                m_pmem[m_addr++] = m_ireg & 0x0ff;
703
                        } break;
704
                /*
705
                case EQSPIF_RELEASE:
706
                        if (m_count >= 32) {
707
                                QOREG(DEVESD);
708
                        } break;
709
                */
710
                default:
711
                        printf("EQSPI ... DEFAULT OP???\n");
712
                        QOREG(0xff);
713
                        break;
714
                }
715
        } // else printf("SFLASH->count = %d\n", m_count);
716
 
717
        m_last_sck = sck;
718
        int     out = m_nxtout[3];
719
        m_nxtout[3] = m_nxtout[2];
720
        m_nxtout[2] = m_nxtout[1];
721
        m_nxtout[1] = m_nxtout[0];
722
        if (m_quad_mode)
723
                m_nxtout[0] =  (m_oreg>>8)&0x0f;
724
        else
725
                m_nxtout[0] =  (m_oreg & 0x0100)?2:0;
726
        return out;
727
}
728
 

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.