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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: eqspiflash.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose: Provide access to the flash device on an Arty, via the Extended
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// SPI interface. Reads and writes will use the QuadSPI interface
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// (4-bits at a time) all other commands (register and otherwise) will use
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// the SPI interface (1 bit at a time).
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//
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// Registers:
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// 0. Erase register control. Provides status of pending writes, erases,
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// and commands (sub)sector erase operations.
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// Bit-Fields:
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// 31. WIP (Write-In-Progress), write a '1' to this bit to command
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// an erase sequence.
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// 30. WriteEnabled -- set to a '1' to disable write protection and
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// to write a WRITE-ENABLE to the device. Set to a '0' to
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// disable WRITE-ENABLE-LATCH. (Key is required to enable
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// writes)
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// 29. Quad mode read/writes enabled. (Rest of controller will use
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// extended SPI mode, but reads and writes will use Quad
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// mode.)
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// 28. Subsector erase bit (set 1 to erase a subsector, 0 to
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// erase a full sector, maintains last value written from
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// an erase command, starts at '0')
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// 27. SD ID loaded
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// 26. Write protect violation--cleared upon any valid write
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// 25. XIP enabled. (Leave read mode in XIP, so you can start
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// next read faster.)
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// 24. Unused
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// 23..0: Address of erase sector upon erase command
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// 23..14: Sector address (can only be changed w/ key)
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// 23..10: Subsector address (can only be changed w/ key)
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// 9.. 0: write protect KEY bits, always read a '0', write
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// commands, such as WP disable or erase, must always
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// write with a '1be' to activate.
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// 0. WEL: All writes that do not command an erase will be used
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// to set/clear the write enable latch.
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// Send 0x06, return, if WP is clear (enable writes)
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// Send 0x04, return
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// 1. STATUS
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// Send 0x05, read 1-byte
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// Send 0x01, write 1-byte: i_wb_data[7:0]
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// 2. NV-CONFIG (16-bits)
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// Send 0xB5, read 2-bytes
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// Send 0xB1, write 2-bytes: i_wb_data[15:0]
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// 3. V-CONFIG (8-bits)
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// Send 0x85, read 1-byte
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// Send 0x81, write 1-byte: i_wb_data[7:0]
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// 4. EV-CONFIG (8-bits)
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// Send 0x65, read 1-byte
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// Send 0x61, write 1-byte: i_wb_data[7:0]
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// 5. Lock (send 32-bits, rx 1 byte)
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// Send 0xE8, last-sector-addr (3b), read 1-byte
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// Send 0xE5, last-sector-addr (3b), write 1-byte: i_wb_data[7:0]
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// 6. Flag Status
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// Send 0x70, read 1-byte
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// Send 0x50, to clear, no bytes to write
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// 7. Asynch Read-ID: Write here to cause controller to read ID into buffer
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// 8.-12. ID buffer (20 bytes, 5 words)
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// Attempted reads before buffer is full will stall bus until
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// buffer is read. Writes act like the asynch-Read-ID command,
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// and will cause the controller to read the buffer.
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// 13.-14. Unused, mapped to Asynch-read-ID
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// 15. OTP control word
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// Write zero to permanently lock OTP
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// Read to determine if OTP is permanently locked
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// 16.-31. OTP (64-bytes, 16 words, buffered until write)
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// (Send DWP before writing to clear write enable latch)
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// `define QSPI_READ_ONLY
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module eqspiflash(i_clk_200mhz, i_rst,
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// Incoming wishbone connection(s)
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// The two strobe lines allow the data to live on a
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// separate part of the master bus from the control
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// registers. Only one strobe will ever be active at any
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// time, no strobes will ever be active unless i_wb_cyc
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// is also active.
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i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
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i_wb_addr, i_wb_data,
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// Outgoing wishbone data
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o_wb_ack, o_wb_stall, o_wb_data,
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// Quad SPI connections
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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// Interrupt the CPU
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o_interrupt, o_cmd_accepted,
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// Debug the interface
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o_dbg);
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input i_clk_200mhz, i_rst;
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// Wishbone bus inputs
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input [21:0] i_wb_addr; // 24 bits of addr space
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input [31:0] i_wb_data;
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// Wishbone bus outputs
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output reg o_wb_ack;
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output wire o_wb_stall;
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output reg [31:0] o_wb_data;
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// Quad SPI connections
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output wire o_qspi_sck, o_qspi_cs_n;
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output wire [1:0] o_qspi_mod;
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output wire [3:0] o_qspi_dat;
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input wire [3:0] i_qspi_dat;
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//
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output reg o_interrupt;
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//
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output reg o_cmd_accepted;
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//
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output wire [31:0] o_dbg;
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initial o_cmd_accepted = 1'b0;
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always @(posedge i_clk_200mhz)
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o_cmd_accepted=((i_wb_data_stb)||(i_wb_ctrl_stb))&&(~o_wb_stall);
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//
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// llqspi
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//
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// Providing the low-level SPI interface
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//
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reg spi_wr, spi_hold, spi_spd, spi_dir, spi_recycle;
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reg [31:0] spi_word;
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reg [1:0] spi_len;
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wire [31:0] spi_out;
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wire spi_valid, spi_busy, spi_stopped;
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llqspi lowlvl(i_clk_200mhz, spi_wr, spi_hold, spi_word, spi_len,
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spi_spd, spi_dir, spi_recycle, spi_out, spi_valid, spi_busy,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat);
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assign spi_stopped = (o_qspi_cs_n)&&(~spi_busy)&&(~spi_wr);
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//
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// Bus module
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//
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// Providing a shared interface to the WB bus
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//
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// Wishbone data (returns)
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wire bus_wb_ack, bus_wb_stall;
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wire [31:0] bus_wb_data;
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// Latched request data
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wire bus_wr;
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wire [21:0] bus_addr;
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wire [31:0] bus_data;
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wire [21:0] bus_sector;
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// Strobe commands
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wire bus_ack;
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wire bus_readreq, bus_piperd, bus_ereq, bus_wreq,
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bus_pipewr, bus_endwr, bus_ctreq, bus_idreq,
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bus_other_req,
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// Live parameters
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w_xip, w_quad, w_idloaded;
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reg bus_wip;
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qspibus preproc(i_clk_200mhz, i_rst,
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i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb,
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i_wb_we, i_wb_addr, i_wb_data,
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bus_wb_ack, bus_wb_stall, bus_wb_data,
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bus_wr, bus_addr, bus_data, bus_sector,
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bus_readreq, bus_piperd,
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bus_wreq, bus_ereq,
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bus_pipewr, bus_endwr,
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bus_ctreq, bus_idreq, bus_other_req, bus_ack,
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w_xip, w_quad, w_idloaded, bus_wip, spi_stopped);
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//
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// Read flash module
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//
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// Providing a means of (and the logic to support) reading from
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// the flash
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//
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wire rd_data_ack;
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wire [31:0] rd_data;
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//
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wire rd_bus_ack;
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//
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wire rd_qspi_req;
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wire rd_qspi_grant;
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//
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wire rd_spi_wr, rd_spi_hold, rd_spi_spd, rd_spi_dir,
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rd_spi_recycle;
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wire [31:0] rd_spi_word;
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wire [1:0] rd_spi_len;
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//
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readqspi rdproc(i_clk_200mhz, bus_readreq, bus_piperd,
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bus_other_req,
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bus_addr, rd_bus_ack,
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rd_qspi_req, rd_qspi_grant,
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rd_spi_wr, rd_spi_hold, rd_spi_word, rd_spi_len,
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rd_spi_spd, rd_spi_dir, rd_spi_recycle,
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spi_out, spi_valid,
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spi_busy, spi_stopped, rd_data_ack, rd_data,
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w_quad, w_xip);
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//
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// Write/Erase flash module
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//
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// Logic to write (program) and erase the flash.
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//
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// Wishbone bus return
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wire ew_data_ack;
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wire [31:0] ew_data;
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// Arbiter interaction
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wire ew_qspi_req;
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wire ew_qspi_grant;
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// Bus controller return
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wire ew_bus_ack;
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// SPI control wires
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wire ew_spi_wr, ew_spi_hold, ew_spi_spd, ew_spi_dir;
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wire [31:0] ew_spi_word;
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wire [1:0] ew_spi_len;
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//
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wire w_ew_wip;
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//
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writeqspi ewproc(i_clk_200mhz, bus_wreq,bus_ereq,
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bus_pipewr, bus_endwr,
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bus_addr, bus_data,
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ew_bus_ack, ew_qspi_req, ew_qspi_grant,
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ew_spi_wr, ew_spi_hold, ew_spi_word, ew_spi_len,
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ew_spi_spd, ew_spi_dir,
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spi_out, spi_valid, spi_busy, spi_stopped,
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ew_data_ack, w_quad, w_ew_wip);
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//
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// Control module
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//
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// Logic to read/write status and configuration registers
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//
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// Wishbone bus return
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wire ct_data_ack;
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wire [31:0] ct_data;
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// Arbiter interaction
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wire ct_qspi_req;
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wire ct_grant;
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// Bus controller return
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wire ct_ack;
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// SPI control wires
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wire ct_spi_wr, ct_spi_hold, ct_spi_spd, ct_spi_dir;
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wire [31:0] ct_spi_word;
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wire [1:0] ct_spi_len;
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//
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ctrlspi ctproc(i_clk_200mhz,
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bus_ctreq, bus_wr, bus_addr[2:0], bus_data, bus_sector,
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ct_qspi_req, ct_grant,
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ct_spi_wr, ct_spi_hold, ct_spi_word, ct_spi_len,
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ct_spi_spd, ct_spi_dir,
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spi_out, spi_valid, spi_busy, spi_stopped,
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ct_ack, ct_data_ack, ct_data, w_xip, w_quad);
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assign ct_spi_hold = 1'b0;
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assign ct_spi_spd = 1'b0;
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//
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// ID/OTP module
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//
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// Access to ID and One-Time-Programmable registers, but to read
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// and to program (the OTP), and to finally lock (OTP) registers.
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//
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// Wishbone bus return
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wire id_data_ack;
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wire [31:0] id_data;
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// Arbiter interaction
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wire id_qspi_req;
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wire id_qspi_grant;
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// Bus controller return
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wire id_bus_ack;
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// SPI control wires
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wire id_spi_wr, id_spi_hold, id_spi_spd, id_spi_dir;
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wire [31:0] id_spi_word;
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wire [1:0] id_spi_len;
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//
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wire w_id_wip;
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//
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idotpqspi idotp(i_clk_200mhz, bus_idreq,
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bus_wr, bus_pipewr, bus_addr[4:0], bus_data, id_bus_ack,
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id_qspi_req, id_qspi_grant,
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id_spi_wr, id_spi_hold, id_spi_word, id_spi_len,
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id_spi_spd, id_spi_dir,
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spi_out, spi_valid, spi_busy, spi_stopped,
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id_data_ack, id_data, w_idloaded, w_id_wip);
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// Arbitrator
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reg owned;
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reg [1:0] owner;
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initial owned = 1'b0;
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always @(posedge i_clk_200mhz) // 7 inputs (spi_stopped is the CE)
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if ((~owned)&&(spi_stopped))
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begin
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casez({rd_qspi_req,ew_qspi_req,id_qspi_req,ct_qspi_req})
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|
4'b1???: begin owned<= 1'b1; owner <= 2'b00; end
|
318 |
|
|
4'b01??: begin owned<= 1'b1; owner <= 2'b01; end
|
319 |
|
|
4'b001?: begin owned<= 1'b1; owner <= 2'b10; end
|
320 |
|
|
4'b0001: begin owned<= 1'b1; owner <= 2'b11; end
|
321 |
|
|
default: begin owned<= 1'b0; owner <= 2'b00; end
|
322 |
|
|
endcase
|
323 |
|
|
end else if ((owned)&&(spi_stopped))
|
324 |
|
|
begin
|
325 |
|
|
casez({rd_qspi_req,ew_qspi_req,id_qspi_req,ct_qspi_req,owner})
|
326 |
|
|
6'b0???00: owned<= 1'b0;
|
327 |
|
|
6'b?0??01: owned<= 1'b0;
|
328 |
|
|
6'b??0?10: owned<= 1'b0;
|
329 |
|
|
6'b???011: owned<= 1'b0;
|
330 |
|
|
default: begin ; end
|
331 |
|
|
endcase
|
332 |
|
|
end
|
333 |
|
|
|
334 |
|
|
assign rd_qspi_grant = (owned)&&(owner == 2'b00);
|
335 |
|
|
assign ew_qspi_grant = (owned)&&(owner == 2'b01);
|
336 |
|
|
assign id_qspi_grant = (owned)&&(owner == 2'b10);
|
337 |
|
|
assign ct_grant = (owned)&&(owner == 2'b11);
|
338 |
|
|
|
339 |
|
|
// Module controller
|
340 |
|
|
always @(posedge i_clk_200mhz)
|
341 |
|
|
case(owner)
|
342 |
|
|
2'b00: begin
|
343 |
|
|
spi_wr <= (owned)&&(rd_spi_wr);
|
344 |
|
|
spi_hold <= rd_spi_hold;
|
345 |
|
|
spi_word <= rd_spi_word;
|
346 |
|
|
spi_len <= rd_spi_len;
|
347 |
|
|
spi_spd <= rd_spi_spd;
|
348 |
|
|
spi_dir <= rd_spi_dir;
|
349 |
|
|
spi_recycle <= rd_spi_recycle;
|
350 |
|
|
end
|
351 |
|
|
2'b01: begin
|
352 |
|
|
spi_wr <= (owned)&&(ew_spi_wr);
|
353 |
|
|
spi_hold <= ew_spi_hold;
|
354 |
|
|
spi_word <= ew_spi_word;
|
355 |
|
|
spi_len <= ew_spi_len;
|
356 |
|
|
spi_spd <= ew_spi_spd;
|
357 |
|
|
spi_dir <= ew_spi_dir;
|
358 |
|
|
spi_recycle <= 1'b1; // Long recycle time
|
359 |
|
|
end
|
360 |
|
|
2'b10: begin
|
361 |
|
|
spi_wr <= (owned)&&(id_spi_wr);
|
362 |
|
|
spi_hold <= id_spi_hold;
|
363 |
|
|
spi_word <= id_spi_word;
|
364 |
|
|
spi_len <= id_spi_len;
|
365 |
|
|
spi_spd <= id_spi_spd;
|
366 |
|
|
spi_dir <= id_spi_dir;
|
367 |
|
|
spi_recycle <= 1'b1; // Long recycle time
|
368 |
|
|
end
|
369 |
|
|
2'b11: begin
|
370 |
|
|
spi_wr <= (owned)&&(ct_spi_wr);
|
371 |
|
|
spi_hold <= ct_spi_hold;
|
372 |
|
|
spi_word <= ct_spi_word;
|
373 |
|
|
spi_len <= ct_spi_len;
|
374 |
|
|
spi_spd <= ct_spi_spd;
|
375 |
|
|
spi_dir <= ct_spi_dir;
|
376 |
|
|
spi_recycle <= 1'b1; // Long recycle time
|
377 |
|
|
end
|
378 |
|
|
endcase
|
379 |
|
|
|
380 |
|
|
reg last_wip;
|
381 |
|
|
initial bus_wip = 1'b0;
|
382 |
|
|
initial last_wip = 1'b0;
|
383 |
|
|
initial o_interrupt = 1'b0;
|
384 |
|
|
always @(posedge i_clk_200mhz)
|
385 |
|
|
begin
|
386 |
|
|
bus_wip <= w_ew_wip || w_id_wip;
|
387 |
|
|
last_wip <= bus_wip;
|
388 |
|
|
o_interrupt <= ((~bus_wip)&&(last_wip));
|
389 |
|
|
end
|
390 |
|
|
|
391 |
|
|
|
392 |
|
|
// Now, let's return values onto the wb bus
|
393 |
|
|
always @(posedge i_clk_200mhz)
|
394 |
|
|
begin
|
395 |
|
|
// Ack our internal bus controller. This means the command was
|
396 |
|
|
// accepted, and the bus can go on to looking for the next
|
397 |
|
|
// command. It controls the i_wb_stall line, just not the
|
398 |
|
|
// i_wb_ack line.
|
399 |
|
|
|
400 |
|
|
// Ack the wishbone with any response
|
401 |
|
|
o_wb_ack <= (bus_wb_ack)|(rd_data_ack)|(ew_data_ack)|(id_data_ack)|(ct_data_ack);
|
402 |
|
|
o_wb_data <= (bus_wb_ack)?bus_wb_data
|
403 |
|
|
: (id_data_ack) ? id_data : spi_out;
|
404 |
|
|
end
|
405 |
|
|
|
406 |
|
|
assign o_wb_stall = bus_wb_stall;
|
407 |
|
|
assign bus_ack = (rd_bus_ack|ew_bus_ack|id_bus_ack|ct_ack);
|
408 |
|
|
|
409 |
|
|
assign o_dbg = {
|
410 |
|
|
i_wb_cyc, i_wb_ctrl_stb, i_wb_data_stb, o_wb_ack, bus_ack, //5
|
411 |
|
|
//
|
412 |
|
|
(spi_wr)&&(~spi_busy), spi_valid, spi_word[31:25],
|
413 |
|
|
spi_out[7:2],
|
414 |
|
|
//
|
415 |
|
|
o_qspi_cs_n, o_qspi_sck, o_qspi_mod, // 4 bits
|
416 |
|
|
o_qspi_dat, i_qspi_dat // 8 bits
|
417 |
|
|
};
|
418 |
|
|
endmodule
|
419 |
|
|
|
420 |
|
|
module qspibus(i_clk, i_rst, i_cyc, i_data_stb, i_ctrl_stb,
|
421 |
|
|
i_we, i_addr, i_data,
|
422 |
|
|
o_wb_ack, o_wb_stall, o_wb_data,
|
423 |
|
|
o_wr, o_addr, o_data, o_sector,
|
424 |
|
|
o_readreq, o_piperd, o_wrreq, o_erreq, o_pipewr, o_endwr,
|
425 |
|
|
o_ctreq, o_idreq, o_other,
|
426 |
|
|
i_ack, i_xip, i_quad, i_idloaded, i_wip, i_spi_stopped);
|
427 |
|
|
//
|
428 |
|
|
input i_clk, i_rst;
|
429 |
|
|
// Wishbone bus inputs
|
430 |
|
|
input i_cyc, i_data_stb, i_ctrl_stb, i_we;
|
431 |
|
|
input [21:0] i_addr;
|
432 |
|
|
input [31:0] i_data;
|
433 |
|
|
// Wishbone bus outputs
|
434 |
|
|
output reg o_wb_ack;
|
435 |
|
|
output reg o_wb_stall;
|
436 |
|
|
output wire [31:0] o_wb_data;
|
437 |
|
|
// Internal signals to the QSPI flash interface
|
438 |
|
|
output reg o_wr;
|
439 |
|
|
output reg [21:0] o_addr;
|
440 |
|
|
output reg [31:0] o_data;
|
441 |
|
|
output wire [21:0] o_sector;
|
442 |
|
|
output reg o_readreq, o_piperd, o_wrreq, o_erreq,
|
443 |
|
|
o_pipewr, o_endwr,
|
444 |
|
|
o_ctreq, o_idreq;
|
445 |
|
|
output wire o_other;
|
446 |
|
|
input i_ack, i_xip, i_quad, i_idloaded;
|
447 |
|
|
input i_wip, i_spi_stopped;
|
448 |
|
|
|
449 |
|
|
|
450 |
|
|
//
|
451 |
|
|
reg pending, lcl_wrreq, lcl_ctreq, lcl_ack, ack, wp_err, wp;
|
452 |
|
|
reg lcl_reg;
|
453 |
|
|
reg [14:0] esector;
|
454 |
|
|
reg [21:0] next_addr;
|
455 |
|
|
|
456 |
|
|
|
457 |
|
|
reg pipeable;
|
458 |
|
|
reg same_page;
|
459 |
|
|
always @(posedge i_clk)
|
460 |
|
|
same_page <= (i_data_stb)&&(i_we)
|
461 |
|
|
&&(i_addr[21:6] == o_addr[21:6])
|
462 |
|
|
&&(i_addr[5:0] == o_addr[5:0] + 6'h1);
|
463 |
|
|
|
464 |
|
|
initial pending = 1'b0;
|
465 |
|
|
initial o_readreq = 1'b0;
|
466 |
|
|
initial lcl_wrreq = 1'b0;
|
467 |
|
|
initial lcl_ctreq = 1'b0;
|
468 |
|
|
initial o_ctreq = 1'b0;
|
469 |
|
|
initial o_idreq = 1'b0;
|
470 |
|
|
|
471 |
|
|
initial ack = 1'b0;
|
472 |
|
|
always @(posedge i_clk)
|
473 |
|
|
ack <= (i_ack)||(lcl_ack);
|
474 |
|
|
|
475 |
|
|
// wire [9:0] key;
|
476 |
|
|
// assign key = 10'h1be;
|
477 |
|
|
reg lcl_key, set_sector, ctreg_stb;
|
478 |
|
|
initial lcl_key = 1'b0;
|
479 |
|
|
always @(posedge i_clk)
|
480 |
|
|
// Write protect "key" to enable the disabling of write protect
|
481 |
|
|
lcl_key<= (i_ctrl_stb)&&(~wp)&&(i_we)&&(i_addr[5:0]==6'h00)
|
482 |
|
|
&&(i_data[9:0] == 10'h1be)&&(i_data[31:30]==2'b11);
|
483 |
|
|
initial set_sector = 1'b0;
|
484 |
|
|
always @(posedge i_clk)
|
485 |
|
|
set_sector <= (i_ctrl_stb)&&(~o_wb_stall)
|
486 |
|
|
&&(i_we)&&(i_addr[5:0]==6'h00)
|
487 |
|
|
&&(i_data[9:0] == 10'h1be);
|
488 |
|
|
|
489 |
|
|
always @(posedge i_clk)
|
490 |
|
|
if (i_ctrl_stb)
|
491 |
|
|
lcl_reg <= (i_addr[3:0] == 4'h00);
|
492 |
|
|
|
493 |
|
|
initial ctreg_stb = 1'b0;
|
494 |
|
|
initial o_wb_stall = 1'b0;
|
495 |
|
|
always @(posedge i_clk)
|
496 |
|
|
begin // Inputs: rst, stb, stb, stall, ack, addr[4:0] -- 9
|
497 |
|
|
if (i_rst)
|
498 |
|
|
o_wb_stall <= 1'b0;
|
499 |
|
|
else
|
500 |
|
|
o_wb_stall <= (((i_data_stb)||(i_ctrl_stb))&&(~o_wb_stall))
|
501 |
|
|
||((pending)&&(~ack));
|
502 |
|
|
|
503 |
|
|
ctreg_stb <= (i_ctrl_stb)&&(~o_wb_stall)&&(i_addr[4:0]==5'h00)&&(~pending)
|
504 |
|
|
||(pending)&&(ctreg_stb)&&(~lcl_ack)&&(~i_ack);
|
505 |
|
|
if (~o_wb_stall)
|
506 |
|
|
begin // Bus command accepted!
|
507 |
|
|
if ((i_data_stb)||(i_ctrl_stb))
|
508 |
|
|
begin
|
509 |
|
|
pending <= 1'b1;
|
510 |
|
|
o_addr <= i_addr;
|
511 |
|
|
o_data <= i_data;
|
512 |
|
|
o_wr <= i_we;
|
513 |
|
|
next_addr <= i_addr + 22'h1;
|
514 |
|
|
end
|
515 |
|
|
|
516 |
|
|
if ((i_data_stb)&&(~i_we))
|
517 |
|
|
o_readreq <= 1'b1;
|
518 |
|
|
|
519 |
|
|
if ((i_data_stb)&&(i_we))
|
520 |
|
|
lcl_wrreq <= 1'b1;
|
521 |
|
|
if ((i_ctrl_stb)&&(~i_addr[4]))
|
522 |
|
|
begin
|
523 |
|
|
casez(i_addr[4:0])
|
524 |
|
|
5'h0: lcl_ctreq<= 1'b1;
|
525 |
|
|
5'h1: lcl_ctreq <= 1'b1;
|
526 |
|
|
5'h2: lcl_ctreq <= 1'b1;
|
527 |
|
|
5'h3: lcl_ctreq <= 1'b1;
|
528 |
|
|
5'h4: lcl_ctreq <= 1'b1;
|
529 |
|
|
5'h5: lcl_ctreq <= 1'b1;
|
530 |
|
|
5'h6: lcl_ctreq <= 1'b1;
|
531 |
|
|
5'h7: lcl_ctreq <= 1'b1;
|
532 |
|
|
5'h8: o_idreq <= 1'b1; // ID[0]
|
533 |
|
|
5'h9: o_idreq <= 1'b1; // ID[1]
|
534 |
|
|
5'ha: o_idreq <= 1'b1; // ID[2]
|
535 |
|
|
5'hb: o_idreq <= 1'b1; // ID[3]
|
536 |
|
|
5'hc: o_idreq <= 1'b1; // ID[4]
|
537 |
|
|
5'hd: o_idreq <= 1'b1; //
|
538 |
|
|
5'he: o_idreq <= 1'b1;
|
539 |
|
|
5'hf: o_idreq <= 1'b1; // Program OTP register
|
540 |
|
|
default: begin o_idreq <= 1'b1; end
|
541 |
|
|
endcase
|
542 |
|
|
end else if (i_ctrl_stb)
|
543 |
|
|
o_idreq <= 1'b1;
|
544 |
|
|
end else if (ack)
|
545 |
|
|
begin
|
546 |
|
|
pending <= 1'b0;
|
547 |
|
|
o_readreq <= 1'b0;
|
548 |
|
|
o_idreq <= 1'b0;
|
549 |
|
|
lcl_ctreq <= 1'b0;
|
550 |
|
|
lcl_wrreq <= 1'b0;
|
551 |
|
|
end
|
552 |
|
|
|
553 |
|
|
if(i_rst)
|
554 |
|
|
begin
|
555 |
|
|
pending <= 1'b0;
|
556 |
|
|
o_readreq <= 1'b0;
|
557 |
|
|
o_idreq <= 1'b0;
|
558 |
|
|
lcl_ctreq <= 1'b0;
|
559 |
|
|
lcl_wrreq <= 1'b0;
|
560 |
|
|
end
|
561 |
|
|
|
562 |
|
|
if ((i_data_stb)&&(~o_wb_stall))
|
563 |
|
|
o_piperd <= ((~i_we)&&(~o_wb_stall)&&(pipeable)&&(i_addr == next_addr));
|
564 |
|
|
else if ((i_ack)||(((i_ctrl_stb)||(i_data_stb))&&(~o_wb_stall)))
|
565 |
|
|
o_piperd <= 1'b0;
|
566 |
|
|
if ((i_data_stb)&&(~o_wb_stall))
|
567 |
|
|
pipeable <= (~i_we);
|
568 |
|
|
else if ((i_ctrl_stb)&&(~o_wb_stall))
|
569 |
|
|
pipeable <= 1'b0;
|
570 |
|
|
|
571 |
|
|
o_pipewr <= (same_page)||(pending)&&(o_pipewr);
|
572 |
|
|
end
|
573 |
|
|
|
574 |
|
|
reg r_other, last_wip;
|
575 |
|
|
|
576 |
|
|
reg last_pending;
|
577 |
|
|
always @(posedge i_clk)
|
578 |
|
|
last_pending <= pending;
|
579 |
|
|
always @(posedge i_clk)
|
580 |
|
|
last_wip <= i_wip;
|
581 |
|
|
wire new_req;
|
582 |
|
|
assign new_req = (pending)&&(~last_pending);
|
583 |
|
|
|
584 |
|
|
initial o_wrreq = 1'b0;
|
585 |
|
|
initial o_erreq = 1'b0;
|
586 |
|
|
initial wp_err = 1'b0;
|
587 |
|
|
initial lcl_ack = 1'b0;
|
588 |
|
|
initial r_other = 1'b0;
|
589 |
|
|
initial o_endwr = 1'b1;
|
590 |
|
|
initial wp = 1'b1;
|
591 |
|
|
always @(posedge i_clk)
|
592 |
|
|
begin
|
593 |
|
|
if (i_ack)
|
594 |
|
|
begin
|
595 |
|
|
o_erreq <= 1'b0;
|
596 |
|
|
o_wrreq <= 1'b0;
|
597 |
|
|
o_ctreq <= 1'b0;
|
598 |
|
|
r_other <= 1'b0;
|
599 |
|
|
end
|
600 |
|
|
|
601 |
|
|
if ((last_wip)&&(~i_wip))
|
602 |
|
|
wp <= 1'b1;
|
603 |
|
|
|
604 |
|
|
// o_endwr <= ((~i_cyc)||(~o_wr)||(o_pipewr))
|
605 |
|
|
// ||(~new_req)&&(o_endwr);
|
606 |
|
|
o_endwr <= ((pending)&&(~o_pipewr))||((~pending)&&(~i_cyc));
|
607 |
|
|
|
608 |
|
|
// Default ACK is always set to zero, unless the following ...
|
609 |
|
|
o_wb_ack <= 1'b0;
|
610 |
|
|
|
611 |
|
|
if (set_sector)
|
612 |
|
|
begin
|
613 |
|
|
esector[13:0] <= { o_data[23:14], 4'h0 };
|
614 |
|
|
wp <= (o_data[30])&&(new_req)||(wp)&&(~new_req);
|
615 |
|
|
if (o_data[28])
|
616 |
|
|
begin
|
617 |
|
|
esector[14] <= o_data[28];
|
618 |
|
|
esector[3:0] <= o_data[13:10];
|
619 |
|
|
end
|
620 |
|
|
end
|
621 |
|
|
|
622 |
|
|
lcl_ack <= 1'b0;
|
623 |
|
|
if ((i_wip)&&(new_req)&&(~same_page))
|
624 |
|
|
begin
|
625 |
|
|
o_wb_ack <= 1'b1;
|
626 |
|
|
lcl_ack <= 1'b1;
|
627 |
|
|
end else if ((ctreg_stb)&&(new_req))
|
628 |
|
|
begin // A request of the status register
|
629 |
|
|
// Always ack control register, even on failed attempts
|
630 |
|
|
// to erase.
|
631 |
|
|
o_wb_ack <= 1'b1;
|
632 |
|
|
lcl_ack <= 1'b1;
|
633 |
|
|
|
634 |
|
|
if (lcl_key)
|
635 |
|
|
begin
|
636 |
|
|
o_ctreq <= 1'b0;
|
637 |
|
|
o_erreq <= 1'b1;
|
638 |
|
|
r_other <= 1'b1;
|
639 |
|
|
lcl_ack <= 1'b0;
|
640 |
|
|
end else if ((o_wr)&&(~o_data[31]))
|
641 |
|
|
begin // WEL or WEL disable
|
642 |
|
|
o_ctreq <= (wp == o_data[30]);
|
643 |
|
|
r_other <= (wp == o_data[30]);
|
644 |
|
|
lcl_ack <= (wp != o_data[30]);
|
645 |
|
|
wp <= !o_data[30];
|
646 |
|
|
end else if (~o_wr)
|
647 |
|
|
lcl_ack <= 1'b1;
|
648 |
|
|
wp_err <= (o_data[31])&&(~lcl_key);
|
649 |
|
|
end else if ((lcl_ctreq)&&(new_req))
|
650 |
|
|
begin
|
651 |
|
|
o_ctreq <= 1'b1;
|
652 |
|
|
r_other <= 1'b1;
|
653 |
|
|
end else if ((lcl_wrreq)&&(new_req))
|
654 |
|
|
begin
|
655 |
|
|
if (~wp)
|
656 |
|
|
begin
|
657 |
|
|
o_wrreq <= 1'b1;
|
658 |
|
|
r_other <= 1'b1;
|
659 |
|
|
o_endwr <= 1'b0;
|
660 |
|
|
lcl_ack <= 1'b0;
|
661 |
|
|
end else begin
|
662 |
|
|
o_wb_ack <= 1'b1;
|
663 |
|
|
wp_err <= 1'b1;
|
664 |
|
|
lcl_ack <= 1'b1;
|
665 |
|
|
end
|
666 |
|
|
end
|
667 |
|
|
|
668 |
|
|
if (i_rst)
|
669 |
|
|
begin
|
670 |
|
|
o_ctreq <= 1'b0;
|
671 |
|
|
o_erreq <= 1'b0;
|
672 |
|
|
o_wrreq <= 1'b0;
|
673 |
|
|
r_other <= 1'b0;
|
674 |
|
|
end
|
675 |
|
|
|
676 |
|
|
end
|
677 |
|
|
|
678 |
|
|
|
679 |
|
|
assign o_wb_data[31:0] = { i_wip, ~wp, i_quad, esector[14],
|
680 |
|
|
i_idloaded, wp_err, i_xip, i_spi_stopped,
|
681 |
|
|
esector[13:0], 10'h00 };
|
682 |
|
|
assign o_sector = { esector[13:0], 8'h00 }; // 22 bits
|
683 |
|
|
assign o_other = (r_other)||(o_idreq);
|
684 |
|
|
|
685 |
|
|
endmodule
|
686 |
|
|
|
687 |
|
|
|
688 |
|
|
`define RD_IDLE 4'h0
|
689 |
|
|
`define RD_IDLE_GET_PORT 4'h1
|
690 |
|
|
`define RD_SLOW_DUMMY 4'h2
|
691 |
|
|
`define RD_SLOW_READ_DATA 4'h3
|
692 |
|
|
`define RD_QUAD_READ_DATA 4'h4
|
693 |
|
|
`define RD_QUAD_DUMMY 4'h5
|
694 |
|
|
`define RD_QUAD_ADDRESS 4'h6
|
695 |
|
|
`define RD_XIP 4'h7
|
696 |
|
|
`define RD_GO_TO_IDLE 4'h8
|
697 |
|
|
`define RD_GO_TO_XIP 4'h9
|
698 |
|
|
|
699 |
|
|
module readqspi(i_clk, i_readreq, i_piperd, i_other_req, i_addr, o_bus_ack,
|
700 |
|
|
o_qspi_req, i_grant,
|
701 |
|
|
o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
|
702 |
|
|
o_spi_spd, o_spi_dir, o_spi_recycle,
|
703 |
|
|
i_spi_data, i_spi_valid, i_spi_busy, i_spi_stopped,
|
704 |
|
|
o_data_ack, o_data, i_quad, i_xip);
|
705 |
|
|
input i_clk;
|
706 |
|
|
input i_readreq, i_piperd, i_other_req;
|
707 |
|
|
input [21:0] i_addr;
|
708 |
|
|
output reg o_bus_ack, o_qspi_req;
|
709 |
|
|
input wire i_grant;
|
710 |
|
|
output reg o_spi_wr;
|
711 |
|
|
output wire o_spi_hold;
|
712 |
|
|
output reg [31:0] o_spi_word;
|
713 |
|
|
output reg [1:0] o_spi_len;
|
714 |
|
|
output reg o_spi_spd, o_spi_dir, o_spi_recycle;
|
715 |
|
|
input [31:0] i_spi_data;
|
716 |
|
|
input i_spi_valid, i_spi_busy, i_spi_stopped;
|
717 |
|
|
output reg o_data_ack;
|
718 |
|
|
output reg [31:0] o_data;
|
719 |
|
|
input i_quad, i_xip;
|
720 |
|
|
|
721 |
|
|
reg accepted;
|
722 |
|
|
initial accepted = 1'b0;
|
723 |
|
|
always @(posedge i_clk)
|
724 |
|
|
accepted <= (~i_spi_busy)&&(i_grant)&&(o_spi_wr)&&(~accepted);
|
725 |
|
|
|
726 |
|
|
reg [3:0] rd_state;
|
727 |
|
|
reg r_leave_xip, r_xip, r_quad, r_requested;
|
728 |
|
|
initial rd_state = `RD_IDLE;
|
729 |
|
|
initial o_data_ack = 1'b0;
|
730 |
|
|
initial o_bus_ack = 1'b0;
|
731 |
|
|
initial o_qspi_req = 1'b0;
|
732 |
|
|
always @(posedge i_clk)
|
733 |
|
|
begin
|
734 |
|
|
o_data_ack <= 1'b0;
|
735 |
|
|
o_bus_ack <= 1'b0;
|
736 |
|
|
o_spi_recycle <= 1'b0;
|
737 |
|
|
if (i_spi_valid)
|
738 |
|
|
o_data <= i_spi_data;
|
739 |
|
|
case(rd_state)
|
740 |
|
|
`RD_IDLE: begin
|
741 |
|
|
r_requested <= 1'b0;
|
742 |
|
|
o_qspi_req <= 1'b0;
|
743 |
|
|
o_spi_word <= { ((i_quad)? 8'h6B: 8'h0b), i_addr, 2'b00 };
|
744 |
|
|
o_spi_wr <= 1'b0;
|
745 |
|
|
o_spi_dir <= 1'b0;
|
746 |
|
|
o_spi_spd <= 1'b0;
|
747 |
|
|
o_spi_len <= 2'b11;
|
748 |
|
|
r_xip <= (i_xip)&&(i_quad);
|
749 |
|
|
r_leave_xip <= 1'b0; // Not in it, so can't leave it
|
750 |
|
|
r_quad <= i_quad;
|
751 |
|
|
if (i_readreq)
|
752 |
|
|
begin
|
753 |
|
|
rd_state <= `RD_IDLE_GET_PORT;
|
754 |
|
|
o_bus_ack <= 1'b1;
|
755 |
|
|
end end
|
756 |
|
|
`RD_IDLE_GET_PORT: begin
|
757 |
|
|
o_spi_wr <= 1'b1; // Write the address
|
758 |
|
|
o_qspi_req <= 1'b1;
|
759 |
|
|
if (accepted)
|
760 |
|
|
rd_state <= `RD_SLOW_DUMMY;
|
761 |
|
|
end
|
762 |
|
|
`RD_SLOW_DUMMY: begin
|
763 |
|
|
o_spi_wr <= 1'b1; // Write 8 dummy clocks
|
764 |
|
|
o_qspi_req <= 1'b1;
|
765 |
|
|
o_spi_dir <= 1'b0;
|
766 |
|
|
o_spi_spd <= 1'b0;
|
767 |
|
|
o_spi_word[31:24] <= (r_xip) ? 8'h00 : 8'hff;
|
768 |
|
|
o_spi_len <= 2'b00; // 8 clocks = 8-bits
|
769 |
|
|
if (accepted)
|
770 |
|
|
rd_state <= (r_quad)?`RD_QUAD_READ_DATA
|
771 |
|
|
: `RD_SLOW_READ_DATA;
|
772 |
|
|
end
|
773 |
|
|
`RD_SLOW_READ_DATA: begin
|
774 |
|
|
o_qspi_req <= 1'b1;
|
775 |
|
|
o_spi_dir <= 1'b1;
|
776 |
|
|
o_spi_spd <= 1'b0;
|
777 |
|
|
o_spi_len <= 2'b11;
|
778 |
|
|
o_spi_wr <= (~r_requested)||(i_piperd);
|
779 |
|
|
// if (accepted)
|
780 |
|
|
// o_spi_wr <= (i_piperd);
|
781 |
|
|
o_data_ack <= (r_requested)&&(i_spi_valid);
|
782 |
|
|
o_bus_ack <= (r_requested)&&(accepted)&&(i_piperd);
|
783 |
|
|
r_requested <= (r_requested)||(accepted);
|
784 |
|
|
if ((i_spi_valid)&&(~o_spi_wr))
|
785 |
|
|
rd_state <= `RD_GO_TO_IDLE;
|
786 |
|
|
end
|
787 |
|
|
`RD_QUAD_READ_DATA: begin
|
788 |
|
|
o_qspi_req <= 1'b1;
|
789 |
|
|
o_spi_dir <= 1'b1;
|
790 |
|
|
o_spi_spd <= 1'b1;
|
791 |
|
|
o_spi_len <= 2'b11;
|
792 |
|
|
o_spi_recycle <= (r_leave_xip)? 1'b1: 1'b0;
|
793 |
|
|
r_requested <= (r_requested)||(accepted);
|
794 |
|
|
o_data_ack <= (r_requested)&&(i_spi_valid)&&(~r_leave_xip);
|
795 |
|
|
o_bus_ack <= (r_requested)&&(accepted)&&(i_piperd)&&(~r_leave_xip);
|
796 |
|
|
o_spi_wr <= (~r_requested)||(i_piperd);
|
797 |
|
|
// if (accepted)
|
798 |
|
|
// o_spi_wr <= (i_piperd);
|
799 |
|
|
if (accepted)
|
800 |
|
|
o_data <= i_spi_data;
|
801 |
|
|
if ((i_spi_valid)&&(~o_spi_wr))
|
802 |
|
|
rd_state <= ((r_leave_xip)||(~r_xip))?`RD_GO_TO_IDLE:`RD_GO_TO_XIP;
|
803 |
|
|
end
|
804 |
|
|
`RD_QUAD_ADDRESS: begin
|
805 |
|
|
o_qspi_req <= 1'b1;
|
806 |
|
|
o_spi_wr <= 1'b1;
|
807 |
|
|
o_spi_dir <= 1'b0; // Write the address
|
808 |
|
|
o_spi_spd <= 1'b1; // High speed
|
809 |
|
|
o_spi_word[31:0] <= { i_addr, 2'b00, 8'h00 };
|
810 |
|
|
o_spi_len <= 2'b10; // 24 bits, High speed, 6 clocks
|
811 |
|
|
if (accepted)
|
812 |
|
|
rd_state <= `RD_QUAD_DUMMY;
|
813 |
|
|
end
|
814 |
|
|
`RD_QUAD_DUMMY: begin
|
815 |
|
|
o_qspi_req <= 1'b1;
|
816 |
|
|
o_spi_wr <= 1'b1;
|
817 |
|
|
o_spi_dir <= 1'b0; // Write the dummy
|
818 |
|
|
o_spi_spd <= 1'b1; // High speed
|
819 |
|
|
o_spi_word[31:0] <= (r_xip)? 32'h00 : 32'hffffffff;
|
820 |
|
|
o_spi_len <= 2'b11; // 8 clocks = 32-bits, quad speed
|
821 |
|
|
if (accepted)
|
822 |
|
|
rd_state <= (r_quad)?`RD_QUAD_READ_DATA
|
823 |
|
|
: `RD_SLOW_READ_DATA;
|
824 |
|
|
end
|
825 |
|
|
`RD_XIP: begin
|
826 |
|
|
r_requested <= 1'b0;
|
827 |
|
|
o_qspi_req <= 1'b1;
|
828 |
|
|
o_spi_word <= { i_addr, 2'b00, 8'h00 };
|
829 |
|
|
o_spi_wr <= 1'b0;
|
830 |
|
|
o_spi_dir <= 1'b0; // Write to SPI
|
831 |
|
|
o_spi_spd <= 1'b1; // High speed
|
832 |
|
|
o_spi_len <= 2'b11;
|
833 |
|
|
r_leave_xip <= i_other_req;
|
834 |
|
|
r_xip <= (~i_other_req);
|
835 |
|
|
o_bus_ack <= 1'b0;
|
836 |
|
|
if ((i_readreq)||(i_other_req))
|
837 |
|
|
begin
|
838 |
|
|
rd_state <= `RD_QUAD_ADDRESS;
|
839 |
|
|
o_bus_ack <= i_readreq;
|
840 |
|
|
end end
|
841 |
|
|
`RD_GO_TO_IDLE: begin
|
842 |
|
|
o_qspi_req <= 1'b0;
|
843 |
|
|
o_spi_wr <= 1'b0;
|
844 |
|
|
if ((i_spi_stopped)&&(~i_grant))
|
845 |
|
|
rd_state <= `RD_IDLE;
|
846 |
|
|
end
|
847 |
|
|
`RD_GO_TO_XIP: begin
|
848 |
|
|
o_qspi_req <= 1'b1;
|
849 |
|
|
o_spi_wr <= 1'b0;
|
850 |
|
|
if (i_spi_stopped)
|
851 |
|
|
rd_state <= `RD_XIP;
|
852 |
|
|
end
|
853 |
|
|
default: begin
|
854 |
|
|
// rd_state <= (i_grant)?`RD_BREAK;
|
855 |
|
|
o_qspi_req <= 1'b0;
|
856 |
|
|
o_spi_wr <= 1'b0;
|
857 |
|
|
if ((i_spi_stopped)&&(~i_grant))
|
858 |
|
|
rd_state <= `RD_IDLE;
|
859 |
|
|
end
|
860 |
|
|
endcase
|
861 |
|
|
end
|
862 |
|
|
|
863 |
|
|
assign o_spi_hold = 1'b0;
|
864 |
|
|
|
865 |
|
|
endmodule
|
866 |
|
|
|
867 |
|
|
module writeqspi(i_clk, i_wreq, i_ereq, i_pipewr, i_endpipe, i_addr, i_data,
|
868 |
|
|
o_bus_ack, o_qspi_req, i_qspi_grant,
|
869 |
|
|
o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
|
870 |
|
|
o_spi_spd, o_spi_dir, i_spi_data, i_spi_valid,
|
871 |
|
|
i_spi_busy, i_spi_stopped,
|
872 |
|
|
o_data_ack, i_quad, o_wip);
|
873 |
|
|
input i_clk;
|
874 |
|
|
//
|
875 |
|
|
input i_wreq, i_ereq, i_pipewr, i_endpipe;
|
876 |
|
|
input [21:0] i_addr;
|
877 |
|
|
input [31:0] i_data;
|
878 |
|
|
output reg o_bus_ack, o_qspi_req;
|
879 |
|
|
input i_qspi_grant;
|
880 |
|
|
output reg o_spi_wr, o_spi_hold;
|
881 |
|
|
output reg [31:0] o_spi_word;
|
882 |
|
|
output reg [1:0] o_spi_len;
|
883 |
|
|
output reg o_spi_spd, o_spi_dir;
|
884 |
|
|
input [31:0] i_spi_data;
|
885 |
|
|
input i_spi_valid;
|
886 |
|
|
input i_spi_busy, i_spi_stopped;
|
887 |
|
|
output reg o_data_ack;
|
888 |
|
|
input i_quad;
|
889 |
|
|
output reg o_wip;
|
890 |
|
|
|
891 |
|
|
`ifdef QSPI_READ_ONLY
|
892 |
|
|
always @(posedge i_clk)
|
893 |
|
|
o_data_ack <= (i_wreq)||(i_ereq);
|
894 |
|
|
always @(posedge i_clk)
|
895 |
|
|
o_bus_ack <= (i_wreq)||(i_ereq);
|
896 |
|
|
|
897 |
|
|
always @(posedge i_clk)
|
898 |
|
|
begin
|
899 |
|
|
o_qspi_req <= 1'b0;
|
900 |
|
|
o_spi_wr <= 1'b0;
|
901 |
|
|
o_spi_hold <= 1'b0;
|
902 |
|
|
o_spi_dir <= 1'b1; // Read
|
903 |
|
|
o_spi_spd <= i_quad;
|
904 |
|
|
o_spi_len <= 2'b00;
|
905 |
|
|
o_spi_word <= 32'h00;
|
906 |
|
|
o_wip <= 1'b0;
|
907 |
|
|
end
|
908 |
|
|
`else
|
909 |
|
|
|
910 |
|
|
`define WR_IDLE 4'h0
|
911 |
|
|
`define WR_START_WRITE 4'h1
|
912 |
|
|
`define WR_START_QWRITE 4'h2
|
913 |
|
|
`define WR_PROGRAM 4'h3
|
914 |
|
|
`define WR_PROGRAM_GETNEXT 4'h4
|
915 |
|
|
`define WR_START_ERASE 4'h5
|
916 |
|
|
`define WR_WAIT_ON_STOP 4'h6
|
917 |
|
|
`define WR_REQUEST_STATUS 4'h7
|
918 |
|
|
`define WR_REQUEST_STATUS_NEXT 4'h8
|
919 |
|
|
`define WR_READ_STATUS 4'h9
|
920 |
|
|
`define WR_WAIT_ON_FINAL_STOP 4'ha
|
921 |
|
|
|
922 |
|
|
reg accepted;
|
923 |
|
|
initial accepted = 1'b0;
|
924 |
|
|
always @(posedge i_clk)
|
925 |
|
|
accepted <= (~i_spi_busy)&&(i_qspi_grant)&&(o_spi_wr)&&(~accepted);
|
926 |
|
|
|
927 |
|
|
|
928 |
|
|
reg cyc, chk_wip;
|
929 |
|
|
reg [3:0] wr_state;
|
930 |
|
|
initial wr_state = `WR_IDLE;
|
931 |
|
|
initial cyc = 1'b0;
|
932 |
|
|
always @(posedge i_clk)
|
933 |
|
|
begin
|
934 |
|
|
chk_wip <= 1'b0;
|
935 |
|
|
o_bus_ack <= 1'b0;
|
936 |
|
|
o_data_ack <= 1'b0;
|
937 |
|
|
cyc <= (cyc)&&(~i_endpipe);
|
938 |
|
|
case(wr_state)
|
939 |
|
|
`WR_IDLE: begin
|
940 |
|
|
o_qspi_req <= 1'b0;
|
941 |
|
|
cyc <= 1'b0;
|
942 |
|
|
if (i_ereq)
|
943 |
|
|
wr_state <= `WR_START_ERASE;
|
944 |
|
|
else if (i_wreq)
|
945 |
|
|
wr_state <= (i_quad)?`WR_START_QWRITE
|
946 |
|
|
: `WR_START_WRITE;
|
947 |
|
|
end
|
948 |
|
|
`WR_START_WRITE: begin
|
949 |
|
|
o_wip <= 1'b1;
|
950 |
|
|
o_qspi_req <= 1'b1;
|
951 |
|
|
o_spi_wr <= 1'b1;
|
952 |
|
|
o_spi_dir <= 1'b0;
|
953 |
|
|
o_spi_len <= 2'b11;
|
954 |
|
|
o_spi_spd <= 1'b0;
|
955 |
|
|
o_spi_hold <= 1'b1;
|
956 |
|
|
o_spi_word <= { 8'h02, i_addr, 2'b00 };
|
957 |
|
|
cyc <= 1'b1;
|
958 |
|
|
if (accepted)
|
959 |
|
|
begin
|
960 |
|
|
o_bus_ack <= 1'b1;
|
961 |
|
|
o_data_ack <= 1'b1;
|
962 |
|
|
wr_state <= `WR_PROGRAM;
|
963 |
|
|
o_spi_word <= i_data;
|
964 |
|
|
end end
|
965 |
|
|
`WR_START_QWRITE: begin
|
966 |
|
|
o_wip <= 1'b1;
|
967 |
|
|
o_qspi_req <= 1'b1;
|
968 |
|
|
o_spi_wr <= 1'b1;
|
969 |
|
|
o_spi_dir <= 1'b0;
|
970 |
|
|
o_spi_len <= 2'b11;
|
971 |
|
|
o_spi_spd <= 1'b0;
|
972 |
|
|
o_spi_hold <= 1'b1;
|
973 |
|
|
o_spi_word <= { 8'h32, i_addr, 2'b00 };
|
974 |
|
|
cyc <= 1'b1;
|
975 |
|
|
if (accepted)
|
976 |
|
|
begin
|
977 |
|
|
o_bus_ack <= 1'b1;
|
978 |
|
|
o_data_ack <= 1'b1;
|
979 |
|
|
wr_state <= `WR_PROGRAM;
|
980 |
|
|
o_spi_word <= i_data;
|
981 |
|
|
end end
|
982 |
|
|
`WR_PROGRAM: begin
|
983 |
|
|
o_wip <= 1'b1;
|
984 |
|
|
o_qspi_req <= 1'b1;
|
985 |
|
|
o_spi_wr <= 1'b1;
|
986 |
|
|
o_spi_dir <= 1'b0;
|
987 |
|
|
o_spi_len <= 2'b11;
|
988 |
|
|
o_spi_spd <= i_quad;
|
989 |
|
|
o_spi_hold <= 1'b1;
|
990 |
|
|
// o_spi_word <= i_data;
|
991 |
|
|
if (accepted)
|
992 |
|
|
wr_state <= `WR_PROGRAM_GETNEXT;
|
993 |
|
|
end
|
994 |
|
|
`WR_PROGRAM_GETNEXT: begin
|
995 |
|
|
o_wip <= 1'b1;
|
996 |
|
|
o_qspi_req <= 1'b1;
|
997 |
|
|
o_spi_wr <= 1'b0;
|
998 |
|
|
o_spi_dir <= 1'b0;
|
999 |
|
|
o_spi_len <= 2'b11;
|
1000 |
|
|
o_spi_spd <= i_quad;
|
1001 |
|
|
o_spi_hold <= 1'b1;
|
1002 |
|
|
o_spi_word <= i_data;
|
1003 |
|
|
if (~cyc)
|
1004 |
|
|
wr_state <= `WR_WAIT_ON_STOP;
|
1005 |
|
|
else if (i_pipewr)
|
1006 |
|
|
begin
|
1007 |
|
|
o_bus_ack <= 1'b1;
|
1008 |
|
|
o_data_ack <= 1'b1;
|
1009 |
|
|
wr_state <= `WR_PROGRAM;
|
1010 |
|
|
end end
|
1011 |
|
|
`WR_START_ERASE: begin
|
1012 |
|
|
o_wip <= 1'b1;
|
1013 |
|
|
o_qspi_req <= 1'b1;
|
1014 |
|
|
o_spi_wr <= 1'b1;
|
1015 |
|
|
o_spi_dir <= 1'b0;
|
1016 |
|
|
o_spi_spd <= 1'b0;
|
1017 |
|
|
o_spi_len <= 2'b11;
|
1018 |
|
|
if (i_data[28])
|
1019 |
|
|
// Subsector erase
|
1020 |
|
|
o_spi_word[31:24] <= 8'h20;
|
1021 |
|
|
else
|
1022 |
|
|
// Sector erase
|
1023 |
|
|
o_spi_word[31:24] <= 8'hd8;
|
1024 |
|
|
o_spi_word[23:0] <= { i_data[21:10], 12'h0 };
|
1025 |
|
|
// Data has already been ack'd, so no need to ack
|
1026 |
|
|
// it again. However, we can now free the QSPI
|
1027 |
|
|
// bus processor to accept another command from the
|
1028 |
|
|
// bus.
|
1029 |
|
|
o_bus_ack <= accepted;
|
1030 |
|
|
if (accepted)
|
1031 |
|
|
wr_state <= `WR_WAIT_ON_STOP;
|
1032 |
|
|
end
|
1033 |
|
|
`WR_WAIT_ON_STOP: begin
|
1034 |
|
|
o_wip <= 1'b1;
|
1035 |
|
|
o_qspi_req <= 1'b0;
|
1036 |
|
|
o_spi_wr <= 1'b0;
|
1037 |
|
|
o_spi_hold <= 1'b0;
|
1038 |
|
|
if (i_spi_stopped)
|
1039 |
|
|
wr_state <= `WR_REQUEST_STATUS;
|
1040 |
|
|
end
|
1041 |
|
|
`WR_REQUEST_STATUS: begin
|
1042 |
|
|
o_wip <= 1'b1;
|
1043 |
|
|
o_qspi_req <= 1'b1;
|
1044 |
|
|
o_spi_hold <= 1'b0;
|
1045 |
|
|
o_spi_wr <= 1'b1;
|
1046 |
|
|
o_spi_spd <= 1'b0; // Slow speed
|
1047 |
|
|
o_spi_len <= 2'b00; // 8 bytes
|
1048 |
|
|
o_spi_dir <= 1'b0; // Write
|
1049 |
|
|
o_spi_word <= { 8'h05, 24'h00 };
|
1050 |
|
|
if (accepted)
|
1051 |
|
|
wr_state <= `WR_REQUEST_STATUS_NEXT;
|
1052 |
|
|
end
|
1053 |
|
|
`WR_REQUEST_STATUS_NEXT: begin
|
1054 |
|
|
o_wip <= 1'b1;
|
1055 |
|
|
o_qspi_req <= 1'b1;
|
1056 |
|
|
o_spi_hold <= 1'b0;
|
1057 |
|
|
o_spi_wr <= 1'b1;
|
1058 |
|
|
o_spi_spd <= 1'b0; // Slow speed
|
1059 |
|
|
o_spi_len <= 2'b00; // 8 bytes
|
1060 |
|
|
o_spi_dir <= 1'b1; // Read
|
1061 |
|
|
o_spi_word <= 32'h00;
|
1062 |
|
|
if (accepted)
|
1063 |
|
|
wr_state <= `WR_READ_STATUS;
|
1064 |
|
|
end
|
1065 |
|
|
`WR_READ_STATUS: begin
|
1066 |
|
|
o_wip <= 1'b1;
|
1067 |
|
|
o_qspi_req <= 1'b1;
|
1068 |
|
|
o_spi_hold <= 1'b0;
|
1069 |
|
|
o_spi_wr <= 1'b1;
|
1070 |
|
|
o_spi_spd <= 1'b0; // Slow speed
|
1071 |
|
|
o_spi_len <= 2'b00; // 8 bytes
|
1072 |
|
|
o_spi_dir <= 1'b1; // Read
|
1073 |
|
|
o_spi_word <= 32'h00;
|
1074 |
|
|
if (i_spi_valid)
|
1075 |
|
|
chk_wip <= 1'b1;
|
1076 |
|
|
if ((chk_wip)&&(~i_spi_data[0]))
|
1077 |
|
|
wr_state <= `WR_WAIT_ON_FINAL_STOP;
|
1078 |
|
|
end
|
1079 |
|
|
// `WR_WAIT_ON_FINAL_STOP: // Same as the default
|
1080 |
|
|
default: begin
|
1081 |
|
|
o_qspi_req <= 1'b0;
|
1082 |
|
|
o_spi_wr <= 1'b0;
|
1083 |
|
|
o_wip <= 1'b0;
|
1084 |
|
|
if (i_spi_stopped)
|
1085 |
|
|
wr_state <= `WR_IDLE;
|
1086 |
|
|
end
|
1087 |
|
|
endcase
|
1088 |
|
|
end
|
1089 |
|
|
`endif
|
1090 |
|
|
|
1091 |
|
|
endmodule
|
1092 |
|
|
|
1093 |
|
|
|
1094 |
|
|
`define CT_SAFE
|
1095 |
|
|
`define CT_IDLE 3'h0
|
1096 |
|
|
`define CT_NEXT 3'h1
|
1097 |
|
|
`define CT_GRANTED 3'h2
|
1098 |
|
|
`define CT_DATA 3'h3
|
1099 |
|
|
`define CT_READ_DATA 3'h4
|
1100 |
|
|
`define CT_WAIT_FOR_IDLE 3'h5
|
1101 |
|
|
|
1102 |
|
|
// CTRL commands:
|
1103 |
|
|
// WEL (write-enable latch)
|
1104 |
|
|
// Read Status
|
1105 |
|
|
module ctrlspi(i_clk, i_req, i_wr, i_addr, i_data, i_sector_address,
|
1106 |
|
|
o_spi_req, i_grant,
|
1107 |
|
|
o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
|
1108 |
|
|
o_spi_spd, o_spi_dir,
|
1109 |
|
|
i_spi_data, i_spi_valid, i_spi_busy,
|
1110 |
|
|
i_spi_stopped,
|
1111 |
|
|
o_bus_ack, o_data_ack, o_data, o_xip, o_quad);
|
1112 |
|
|
input i_clk;
|
1113 |
|
|
// From the WB bus controller
|
1114 |
|
|
input i_req;
|
1115 |
|
|
input i_wr;
|
1116 |
|
|
input [2:0] i_addr;
|
1117 |
|
|
input [31:0] i_data;
|
1118 |
|
|
input [21:0] i_sector_address;
|
1119 |
|
|
// To/from the arbiter
|
1120 |
|
|
output reg o_spi_req;
|
1121 |
|
|
input i_grant;
|
1122 |
|
|
// To/from the low-level SPI driver
|
1123 |
|
|
output reg o_spi_wr;
|
1124 |
|
|
output wire o_spi_hold;
|
1125 |
|
|
output reg [31:0] o_spi_word;
|
1126 |
|
|
output reg [1:0] o_spi_len;
|
1127 |
|
|
output wire o_spi_spd;
|
1128 |
|
|
output reg o_spi_dir;
|
1129 |
|
|
input [31:0] i_spi_data;
|
1130 |
|
|
input i_spi_valid;
|
1131 |
|
|
input i_spi_busy, i_spi_stopped;
|
1132 |
|
|
// Return data to the bus controller, and the wishbone bus
|
1133 |
|
|
output reg o_bus_ack, o_data_ack;
|
1134 |
|
|
output reg [31:0] o_data;
|
1135 |
|
|
// Configuration items that we may have configured.
|
1136 |
|
|
output reg o_xip;
|
1137 |
|
|
output wire o_quad;
|
1138 |
|
|
|
1139 |
|
|
// Command registers
|
1140 |
|
|
reg [1:0] ctcmd_len;
|
1141 |
|
|
reg [31:0] ctcmd_word;
|
1142 |
|
|
// Data stage registers
|
1143 |
|
|
reg ctdat_skip, // Skip the data phase?
|
1144 |
|
|
ctdat_wr; // Write during data? (or not read)
|
1145 |
|
|
wire [1:0] ctdat_len;
|
1146 |
|
|
reg [31:0] ctdat_word;
|
1147 |
|
|
|
1148 |
|
|
reg [2:0] ctstate;
|
1149 |
|
|
reg accepted;
|
1150 |
|
|
|
1151 |
|
|
|
1152 |
|
|
initial accepted = 1'b0;
|
1153 |
|
|
always @(posedge i_clk)
|
1154 |
|
|
accepted <= (~i_spi_busy)&&(i_grant)&&(o_spi_wr)&&(~accepted);
|
1155 |
|
|
|
1156 |
|
|
reg r_ctdat_len, ctbus_ack;
|
1157 |
|
|
assign ctdat_len = { 1'b0, r_ctdat_len };
|
1158 |
|
|
|
1159 |
|
|
// First step, calculate the values for our state machine
|
1160 |
|
|
initial o_xip = 1'b0;
|
1161 |
|
|
// initial o_quad = 1'b0;
|
1162 |
|
|
always @(posedge i_clk)
|
1163 |
|
|
if (i_req) // A request for us to act from the bus controller
|
1164 |
|
|
begin
|
1165 |
|
|
ctdat_skip <= 1'b0;
|
1166 |
|
|
ctbus_ack <= 1'b1;
|
1167 |
|
|
ctcmd_word[23:0] <= { i_sector_address, 2'b00 };
|
1168 |
|
|
ctdat_word <= { i_data[7:0], 24'h00 };
|
1169 |
|
|
ctcmd_len <= 2'b00; // 8bit command (for all but Lock regs)
|
1170 |
|
|
r_ctdat_len <= 1'b0; // 8bit data (read or write)
|
1171 |
|
|
ctdat_wr <= i_wr;
|
1172 |
|
|
casez({ i_addr[2:0], i_wr, i_data[30] })
|
1173 |
|
|
5'b00010: begin // Write Disable
|
1174 |
|
|
ctcmd_word[31:24] <= 8'h04;
|
1175 |
|
|
ctdat_skip <= 1'b1;
|
1176 |
|
|
ctbus_ack <= 1'b0;
|
1177 |
|
|
end
|
1178 |
|
|
5'b00011: begin // Write enable
|
1179 |
|
|
ctcmd_word[31:24] <= 8'h06;
|
1180 |
|
|
ctdat_skip <= 1'b1;
|
1181 |
|
|
ctbus_ack <= 1'b0;
|
1182 |
|
|
end
|
1183 |
|
|
// 4'b0010?: begin // Read Status register
|
1184 |
|
|
// Moved to defaults section
|
1185 |
|
|
5'b0011?: begin // Write Status register (Requires WEL)
|
1186 |
|
|
ctcmd_word[31:24] <= 8'h01;
|
1187 |
|
|
`ifdef CT_SAFE
|
1188 |
|
|
ctdat_word <= { 6'h00, i_data[1:0], 24'h00 };
|
1189 |
|
|
`else
|
1190 |
|
|
ctdat_word <= { i_data[7:0], 24'h00 };
|
1191 |
|
|
`endif
|
1192 |
|
|
end
|
1193 |
|
|
5'b0100?: begin // Read NV-Config register (two bytes)
|
1194 |
|
|
ctcmd_word[31:24] <= 8'hB5;
|
1195 |
|
|
r_ctdat_len <= 1'b1; // 16-bit data
|
1196 |
|
|
end
|
1197 |
|
|
5'b0101?: begin // Write NV-Config reg (2 bytes, Requires WEL)
|
1198 |
|
|
ctcmd_word[31:24] <= 8'hB1;
|
1199 |
|
|
r_ctdat_len <= 1'b1; // 16-bit data
|
1200 |
|
|
`ifdef CT_SAFE
|
1201 |
|
|
ctdat_word <= { 4'h8, 3'h7, 3'h7, i_data[5:1], 1'b1, 16'h00 };
|
1202 |
|
|
`else
|
1203 |
|
|
ctdat_word <= { i_data[15:0], 16'h00 };
|
1204 |
|
|
`endif
|
1205 |
|
|
end
|
1206 |
|
|
5'b0110?: begin // Read V-Config register
|
1207 |
|
|
ctcmd_word[31:24] <= 8'h85;
|
1208 |
|
|
end
|
1209 |
|
|
5'b0111?: begin // Write V-Config register (Requires WEL)
|
1210 |
|
|
ctcmd_word[31:24] <= 8'h81;
|
1211 |
|
|
r_ctdat_len <= 1'b0; // 8-bit data
|
1212 |
|
|
`ifdef CT_SAFE
|
1213 |
|
|
ctdat_word <= { 4'h8, i_data[3:2], 2'b11, 24'h00 };
|
1214 |
|
|
`else
|
1215 |
|
|
ctdat_word <= { i_data[7:0], 24'h00 };
|
1216 |
|
|
`endif
|
1217 |
|
|
o_xip <= i_data[3];
|
1218 |
|
|
end
|
1219 |
|
|
5'b1000?: begin // Read EV-Config register
|
1220 |
|
|
ctcmd_word[31:24] <= 8'h65;
|
1221 |
|
|
end
|
1222 |
|
|
5'b1001?: begin // Write EV-Config register (Requires WEL)
|
1223 |
|
|
ctcmd_word[31:24] <= 8'h61;
|
1224 |
|
|
// o_quad <= (~i_data[7]);
|
1225 |
|
|
`ifdef CT_SAFE
|
1226 |
|
|
ctdat_word <= { 1'b1, 3'h5, 4'hf, 24'h00 };
|
1227 |
|
|
`else
|
1228 |
|
|
ctdat_word <= { i_data[7:0], 24'h00 };
|
1229 |
|
|
`endif
|
1230 |
|
|
end
|
1231 |
|
|
5'b1010?: begin // Read Lock register
|
1232 |
|
|
ctcmd_word[31:0] <= { 8'he8, i_sector_address, 2'b00 };
|
1233 |
|
|
ctcmd_len <= 2'b11;
|
1234 |
|
|
ctdat_wr <= 1'b0; // Read, not write
|
1235 |
|
|
end
|
1236 |
|
|
5'b1011?: begin // Write Lock register (Requires WEL)
|
1237 |
|
|
ctcmd_word[31:0] <= { 8'he5, i_sector_address, 2'b00 };
|
1238 |
|
|
ctcmd_len <= 2'b11;
|
1239 |
|
|
ctdat_wr <= 1'b1; // Write
|
1240 |
|
|
end
|
1241 |
|
|
5'b1100?: begin // Read Flag Status register
|
1242 |
|
|
ctcmd_word[31:24] <= 8'h70;
|
1243 |
|
|
ctdat_wr <= 1'b0; // Read, not write
|
1244 |
|
|
end
|
1245 |
|
|
5'b1101?: begin // Write/Clear Flag Status register (No WEL required)
|
1246 |
|
|
ctcmd_word[31:24] <= 8'h50;
|
1247 |
|
|
ctdat_skip <= 1'b1;
|
1248 |
|
|
end
|
1249 |
|
|
default: begin // Default to reading the status register
|
1250 |
|
|
ctcmd_word[31:24] <= 8'h05;
|
1251 |
|
|
ctdat_wr <= 1'b0; // Read, not write
|
1252 |
|
|
r_ctdat_len <= 1'b0; // 8-bit data
|
1253 |
|
|
end
|
1254 |
|
|
endcase
|
1255 |
|
|
end
|
1256 |
|
|
|
1257 |
|
|
assign o_quad = 1'b0;
|
1258 |
|
|
|
1259 |
|
|
reg nxt_data_ack;
|
1260 |
|
|
|
1261 |
|
|
// Second step, actually drive the state machine
|
1262 |
|
|
initial ctstate = `CT_IDLE;
|
1263 |
|
|
always @(posedge i_clk)
|
1264 |
|
|
begin
|
1265 |
|
|
o_spi_wr <= 1'b1;
|
1266 |
|
|
o_bus_ack <= 1'b0;
|
1267 |
|
|
o_data_ack <= 1'b0;
|
1268 |
|
|
if (i_spi_valid)
|
1269 |
|
|
o_data <= i_spi_data;
|
1270 |
|
|
case(ctstate)
|
1271 |
|
|
`CT_IDLE: begin
|
1272 |
|
|
o_spi_req <= 1'b0;
|
1273 |
|
|
o_spi_wr <= 1'b0;
|
1274 |
|
|
if (i_req) // Need a clock to let the digestion
|
1275 |
|
|
ctstate <= `CT_NEXT; // process complete
|
1276 |
|
|
end
|
1277 |
|
|
`CT_NEXT: begin
|
1278 |
|
|
o_spi_wr <= 1'b1;
|
1279 |
|
|
o_spi_req <= 1'b1;
|
1280 |
|
|
o_spi_word <= ctcmd_word;
|
1281 |
|
|
o_spi_len <= ctcmd_len;
|
1282 |
|
|
o_spi_dir <= 1'b0; // Write
|
1283 |
|
|
if (accepted)
|
1284 |
|
|
begin
|
1285 |
|
|
ctstate <= (ctdat_skip)?`CT_WAIT_FOR_IDLE:`CT_DATA;
|
1286 |
|
|
o_bus_ack <= (ctdat_skip);
|
1287 |
|
|
o_data_ack <= (ctdat_skip)&&(ctbus_ack);
|
1288 |
|
|
end end
|
1289 |
|
|
`CT_GRANTED: begin
|
1290 |
|
|
o_spi_wr <= 1'b1;
|
1291 |
|
|
if ((accepted)&&(ctdat_skip))
|
1292 |
|
|
ctstate <= `CT_WAIT_FOR_IDLE;
|
1293 |
|
|
else if (accepted)//&&(~ctdat_skip)
|
1294 |
|
|
ctstate <= `CT_DATA;
|
1295 |
|
|
end
|
1296 |
|
|
`CT_DATA: begin
|
1297 |
|
|
o_spi_wr <= 1'b1;
|
1298 |
|
|
o_spi_len <= ctdat_len;
|
1299 |
|
|
o_spi_dir <= ~ctdat_wr;
|
1300 |
|
|
o_spi_word <= ctdat_word;
|
1301 |
|
|
if (accepted)
|
1302 |
|
|
o_bus_ack <= 1'b1;
|
1303 |
|
|
if (accepted)
|
1304 |
|
|
ctstate <= (ctdat_wr)?`CT_WAIT_FOR_IDLE:`CT_READ_DATA;
|
1305 |
|
|
if ((accepted)&&(ctdat_wr))
|
1306 |
|
|
o_data_ack <= 1'b1;
|
1307 |
|
|
end
|
1308 |
|
|
`CT_READ_DATA: begin
|
1309 |
|
|
o_spi_wr <= 1'b0; // No more words to go, just to wait
|
1310 |
|
|
o_spi_req <= 1'b1;
|
1311 |
|
|
if (i_spi_valid) // for a value to read
|
1312 |
|
|
begin
|
1313 |
|
|
o_data_ack <= 1'b1;
|
1314 |
|
|
o_data <= i_spi_data;
|
1315 |
|
|
ctstate <= `CT_WAIT_FOR_IDLE;
|
1316 |
|
|
end end
|
1317 |
|
|
default: begin // `CT_WAIT_FOR_IDLE
|
1318 |
|
|
o_spi_wr <= 1'b0;
|
1319 |
|
|
o_spi_req <= 1'b0;
|
1320 |
|
|
if (i_spi_stopped)
|
1321 |
|
|
ctstate <= `CT_IDLE;
|
1322 |
|
|
end
|
1323 |
|
|
endcase
|
1324 |
|
|
end
|
1325 |
|
|
|
1326 |
|
|
// All of this is done in straight SPI mode, so our speed will always be zero
|
1327 |
|
|
assign o_spi_hold = 1'b0;
|
1328 |
|
|
assign o_spi_spd = 1'b0;
|
1329 |
|
|
|
1330 |
|
|
endmodule
|
1331 |
|
|
|
1332 |
|
|
`define ID_IDLE 5'h00
|
1333 |
|
|
`define ID_WAIT_ON_START_ID 5'h01
|
1334 |
|
|
`define ID_WAIT_ON_START_OTP 5'h02
|
1335 |
|
|
`define ID_WAIT_ON_START_OTP_WRITE 5'h03
|
1336 |
|
|
`define ID_READ_DATA_COMMAND 5'h04
|
1337 |
|
|
`define ID_GET_DATA 5'h05
|
1338 |
|
|
`define ID_LOADED 5'h06
|
1339 |
|
|
`define ID_LOADED_NEXT 5'h07
|
1340 |
|
|
`define ID_OTP_SEND_DUMMY 5'h08
|
1341 |
|
|
`define ID_OTP_CLEAR 5'h09
|
1342 |
|
|
`define ID_OTP_GET_DATA 5'h0a
|
1343 |
|
|
`define ID_OTP_WRITE 5'h0b
|
1344 |
|
|
`define ID_WAIT_ON_STOP 5'h0c
|
1345 |
|
|
`define ID_REQ_STATUS 5'h0d
|
1346 |
|
|
`define ID_REQ_STATUS_NEXT 5'h0e
|
1347 |
|
|
`define ID_READ_STATUS 5'h0f
|
1348 |
|
|
//
|
1349 |
|
|
`define ID_FINAL_STOP 5'h10
|
1350 |
|
|
|
1351 |
|
|
module idotpqspi(i_clk, i_req, i_wr, i_pipewr, i_addr, i_data, o_bus_ack,
|
1352 |
|
|
o_qspi_req, i_qspi_grant,
|
1353 |
|
|
o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
|
1354 |
|
|
o_spi_spd, o_spi_dir, i_spi_data, i_spi_valid,
|
1355 |
|
|
i_spi_busy, i_spi_stopped, o_data_ack, o_data, o_loaded,
|
1356 |
|
|
o_wip);
|
1357 |
|
|
input i_clk;
|
1358 |
|
|
input i_req, i_wr, i_pipewr;
|
1359 |
|
|
input [4:0] i_addr;
|
1360 |
|
|
input [31:0] i_data;
|
1361 |
|
|
output reg o_bus_ack, o_qspi_req;
|
1362 |
|
|
input i_qspi_grant;
|
1363 |
|
|
output reg o_spi_wr, o_spi_hold;
|
1364 |
|
|
output reg [31:0] o_spi_word;
|
1365 |
|
|
output reg [1:0] o_spi_len;
|
1366 |
|
|
output wire o_spi_spd;
|
1367 |
|
|
output reg o_spi_dir;
|
1368 |
|
|
input [31:0] i_spi_data;
|
1369 |
|
|
input i_spi_valid, i_spi_busy, i_spi_stopped;
|
1370 |
|
|
output reg o_data_ack;
|
1371 |
|
|
output reg [31:0] o_data;
|
1372 |
|
|
output wire o_loaded;
|
1373 |
|
|
output reg o_wip;
|
1374 |
|
|
|
1375 |
|
|
reg id_loaded;
|
1376 |
|
|
initial id_loaded = 1'b0;
|
1377 |
|
|
assign o_loaded= id_loaded;
|
1378 |
|
|
|
1379 |
|
|
/*
|
1380 |
|
|
// Only the ID register will be kept in memory, OTP will be read
|
1381 |
|
|
// or written upon request
|
1382 |
|
|
always @(posedge i_clk)
|
1383 |
|
|
if (i_addr[4])
|
1384 |
|
|
o_data <= otpmem[i_addr[3:0]];
|
1385 |
|
|
else
|
1386 |
|
|
o_data <= idmem[i_addr[2:0]];
|
1387 |
|
|
|
1388 |
|
|
always @(posedge i_clk)
|
1389 |
|
|
if ((otp_loaded)&&(i_req)&&(i_addr[4]))
|
1390 |
|
|
o_data_ack <= 1'b1;
|
1391 |
|
|
else if ((id_loaded)&&(i_req)&&(~i_addr[4]))
|
1392 |
|
|
o_data_ack <= idmem[i_addr[2:0]];
|
1393 |
|
|
else
|
1394 |
|
|
o_data_ack <= 1'b0;
|
1395 |
|
|
*/
|
1396 |
|
|
|
1397 |
|
|
reg otp_read_request, id_read_request, accepted, otp_wr_request,
|
1398 |
|
|
id_read_device, last_id_read;
|
1399 |
|
|
reg [4:0] req_addr;
|
1400 |
|
|
reg [2:0] lcl_id_addr;
|
1401 |
|
|
reg [4:0] id_state;
|
1402 |
|
|
always @(posedge i_clk)
|
1403 |
|
|
begin
|
1404 |
|
|
otp_read_request <= (i_req)&&(~i_wr)&&((i_addr[4])||(i_addr[3:0]==4'hf));
|
1405 |
|
|
last_id_read <= (i_req)&&(~i_addr[4])&&(i_addr[3:0]!=4'hf);
|
1406 |
|
|
id_read_request <= (i_req)&&(~i_addr[4])&&(i_addr[3:0]!=4'hf)&&(~last_id_read);
|
1407 |
|
|
id_read_device <= (i_req)&&(~i_addr[4])&&(i_addr[3:0]!=4'hf)&&(~id_loaded);
|
1408 |
|
|
accepted <= (~i_spi_busy)&&(i_qspi_grant)&&(o_spi_wr)&&(~accepted);
|
1409 |
|
|
|
1410 |
|
|
otp_wr_request <= (i_req)&&(i_wr)&&((i_addr[4])||(i_addr[3:0]==4'hf));
|
1411 |
|
|
|
1412 |
|
|
if (id_state == `ID_IDLE)
|
1413 |
|
|
req_addr <= (i_addr[4:0]==5'h0f) ? 5'h10
|
1414 |
|
|
: { 1'b0, i_addr[3:0] };
|
1415 |
|
|
end
|
1416 |
|
|
|
1417 |
|
|
reg last_addr;
|
1418 |
|
|
always @(posedge i_clk)
|
1419 |
|
|
last_addr <= (lcl_id_addr >= 3'h4);
|
1420 |
|
|
|
1421 |
|
|
reg [31:0] idmem[0:5];
|
1422 |
|
|
reg [31:0] r_data;
|
1423 |
|
|
|
1424 |
|
|
// Now, quickly, let's deal with the fact that the data from the
|
1425 |
|
|
// bus comes one clock later ...
|
1426 |
|
|
reg nxt_data_ack, nxt_data_spi;
|
1427 |
|
|
reg [31:0] nxt_data;
|
1428 |
|
|
|
1429 |
|
|
reg set_val, chk_wip;
|
1430 |
|
|
reg [2:0] set_addr;
|
1431 |
|
|
|
1432 |
|
|
always @(posedge i_clk)
|
1433 |
|
|
begin // Depends upon state[4], otp_rd, otp_wr, otp_pipe, id_req, accepted, last_addr
|
1434 |
|
|
o_bus_ack <= 1'b0;
|
1435 |
|
|
// o_data_ack <= 1'b0;
|
1436 |
|
|
o_spi_hold <= 1'b0;
|
1437 |
|
|
nxt_data_ack <= 1'b0;
|
1438 |
|
|
nxt_data_spi <= 1'b0;
|
1439 |
|
|
chk_wip <= 1'b0;
|
1440 |
|
|
set_val <= 1'b0;
|
1441 |
|
|
if ((id_loaded)&&(id_read_request))
|
1442 |
|
|
begin
|
1443 |
|
|
nxt_data_ack <= 1'b1;
|
1444 |
|
|
o_bus_ack <= 1'b1;
|
1445 |
|
|
end
|
1446 |
|
|
nxt_data <= idmem[i_addr[2:0]];
|
1447 |
|
|
o_spi_wr <= 1'b0; // By default, we send nothing
|
1448 |
|
|
case(id_state)
|
1449 |
|
|
`ID_IDLE: begin
|
1450 |
|
|
o_qspi_req <= 1'b0;
|
1451 |
|
|
o_spi_dir <= 1'b0; // Write to SPI
|
1452 |
|
|
lcl_id_addr <= 3'h0;
|
1453 |
|
|
o_spi_word[23:7] <= 17'h00;
|
1454 |
|
|
o_spi_word[6:0] <= { req_addr[4:0], 2'b00 };
|
1455 |
|
|
r_data <= i_data;
|
1456 |
|
|
o_wip <= 1'b0;
|
1457 |
|
|
if (otp_read_request)
|
1458 |
|
|
begin
|
1459 |
|
|
// o_spi_word <= { 8'h48, 8'h00, 8'h00, 8'h00 };
|
1460 |
|
|
id_state <= `ID_WAIT_ON_START_OTP;
|
1461 |
|
|
o_bus_ack <= 1'b1;
|
1462 |
|
|
end else if (otp_wr_request)
|
1463 |
|
|
begin
|
1464 |
|
|
o_bus_ack <= 1'b1;
|
1465 |
|
|
// o_data_ack <= 1'b1;
|
1466 |
|
|
nxt_data_ack <= 1'b1;
|
1467 |
|
|
id_state <= `ID_WAIT_ON_START_OTP_WRITE;
|
1468 |
|
|
end else if (id_read_device)
|
1469 |
|
|
begin
|
1470 |
|
|
id_state <= `ID_WAIT_ON_START_ID;
|
1471 |
|
|
o_bus_ack <= 1'b0;
|
1472 |
|
|
o_spi_word[31:24] <= 8'h9f;
|
1473 |
|
|
end end
|
1474 |
|
|
`ID_WAIT_ON_START_ID: begin
|
1475 |
|
|
o_spi_wr <= 1'b1;
|
1476 |
|
|
o_qspi_req <= 1'b1;
|
1477 |
|
|
o_spi_len <= 2'b0; // 8 bits
|
1478 |
|
|
if (accepted)
|
1479 |
|
|
id_state <= `ID_READ_DATA_COMMAND;
|
1480 |
|
|
end
|
1481 |
|
|
`ID_WAIT_ON_START_OTP: begin
|
1482 |
|
|
o_spi_wr <= 1'b1;
|
1483 |
|
|
o_spi_word[31:24] <= 8'h4B;
|
1484 |
|
|
o_qspi_req <= 1'b1;
|
1485 |
|
|
o_spi_len <= 2'b11; // 32 bits
|
1486 |
|
|
o_spi_word[6:0] <= { req_addr[4:0], 2'b00 };
|
1487 |
|
|
if (accepted) // Read OTP command was just sent
|
1488 |
|
|
id_state <= `ID_OTP_SEND_DUMMY;
|
1489 |
|
|
end
|
1490 |
|
|
`ID_WAIT_ON_START_OTP_WRITE: begin
|
1491 |
|
|
o_spi_wr <= 1'b1;
|
1492 |
|
|
o_qspi_req <= 1'b1;
|
1493 |
|
|
o_wip <= 1'b1;
|
1494 |
|
|
o_spi_len <= 2'b11; // 32 bits
|
1495 |
|
|
o_spi_word[31:24] <= 8'h42;
|
1496 |
|
|
if (accepted) // Read OTP command was just sent
|
1497 |
|
|
id_state <= `ID_OTP_WRITE;
|
1498 |
|
|
end
|
1499 |
|
|
`ID_READ_DATA_COMMAND: begin
|
1500 |
|
|
o_spi_len <= 2'b11; // 32-bits
|
1501 |
|
|
o_spi_wr <= (~last_addr); // Still transmitting
|
1502 |
|
|
o_spi_dir <= 1'b1; // Read from SPI
|
1503 |
|
|
o_qspi_req <= 1'b1;
|
1504 |
|
|
if (accepted)
|
1505 |
|
|
id_state <= `ID_GET_DATA;
|
1506 |
|
|
end
|
1507 |
|
|
`ID_GET_DATA: begin
|
1508 |
|
|
o_spi_len <= 2'b11; // 32-bits
|
1509 |
|
|
o_spi_wr <= (~last_addr); // Still transmitting
|
1510 |
|
|
o_spi_dir <= 1'b1; // Read from SPI
|
1511 |
|
|
o_qspi_req <= 1'b1;
|
1512 |
|
|
if (i_spi_valid) // same as accepted
|
1513 |
|
|
begin
|
1514 |
|
|
set_val <= 1'b1;
|
1515 |
|
|
set_addr <= lcl_id_addr[2:0];
|
1516 |
|
|
// idmem[lcl_id_addr[2:0]] <= i_spi_data;
|
1517 |
|
|
lcl_id_addr <= lcl_id_addr + 3'h1;
|
1518 |
|
|
if (last_addr)
|
1519 |
|
|
id_state <= `ID_LOADED;
|
1520 |
|
|
end end
|
1521 |
|
|
`ID_LOADED: begin
|
1522 |
|
|
id_loaded <= 1'b1;
|
1523 |
|
|
o_bus_ack <= 1'b1;
|
1524 |
|
|
o_spi_wr <= 1'b0;
|
1525 |
|
|
nxt_data_ack <= 1'b1;
|
1526 |
|
|
id_state <= `ID_LOADED_NEXT;
|
1527 |
|
|
end
|
1528 |
|
|
`ID_LOADED_NEXT: begin
|
1529 |
|
|
o_spi_len <= 2'b11; // 32-bits
|
1530 |
|
|
o_bus_ack <= 1'b0;
|
1531 |
|
|
o_spi_wr <= 1'b0;
|
1532 |
|
|
nxt_data_ack <= 1'b1;
|
1533 |
|
|
id_state <= `ID_IDLE;
|
1534 |
|
|
end
|
1535 |
|
|
`ID_OTP_SEND_DUMMY: begin
|
1536 |
|
|
o_spi_len <= 2'b00; // 1 byte
|
1537 |
|
|
o_spi_wr <= 1'b1; // Still writing
|
1538 |
|
|
o_spi_dir <= 1'b0; // Write to SPI
|
1539 |
|
|
if (accepted) // Wait for the command to be accepted
|
1540 |
|
|
id_state <= `ID_OTP_CLEAR;
|
1541 |
|
|
end
|
1542 |
|
|
`ID_OTP_CLEAR: begin
|
1543 |
|
|
o_spi_wr <= 1'b1; // Still writing
|
1544 |
|
|
o_spi_dir <= 1'b1; // Read from SPI
|
1545 |
|
|
o_spi_len <= 2'b11; // Read from SPI
|
1546 |
|
|
if (accepted)
|
1547 |
|
|
id_state <= `ID_OTP_GET_DATA;
|
1548 |
|
|
end
|
1549 |
|
|
`ID_OTP_GET_DATA: begin
|
1550 |
|
|
if (i_spi_valid)
|
1551 |
|
|
begin
|
1552 |
|
|
id_state <= `ID_FINAL_STOP;
|
1553 |
|
|
nxt_data_ack <= 1'b1;
|
1554 |
|
|
nxt_data_spi <= 1'b1;
|
1555 |
|
|
end end
|
1556 |
|
|
`ID_OTP_WRITE: begin
|
1557 |
|
|
o_spi_wr <= 1'b1;
|
1558 |
|
|
o_spi_len <= 2'b11;
|
1559 |
|
|
o_spi_dir <= 1'b0; // Write to SPI
|
1560 |
|
|
o_spi_word <= r_data;
|
1561 |
|
|
// o_bus_ack <= (otp_wr_request)&&(accepted)&&(i_pipewr);
|
1562 |
|
|
// o_data_ack <= (otp_wr_request)&&(accepted);
|
1563 |
|
|
if (accepted) // &&(~i_pipewr)
|
1564 |
|
|
id_state <= `ID_WAIT_ON_STOP;
|
1565 |
|
|
else if(accepted)
|
1566 |
|
|
begin
|
1567 |
|
|
o_spi_word <= i_data;
|
1568 |
|
|
r_data <= i_data;
|
1569 |
|
|
end end
|
1570 |
|
|
`ID_WAIT_ON_STOP: begin
|
1571 |
|
|
o_spi_wr <= 1'b0;
|
1572 |
|
|
if (i_spi_stopped)
|
1573 |
|
|
id_state <= `ID_REQ_STATUS;
|
1574 |
|
|
end
|
1575 |
|
|
`ID_REQ_STATUS: begin
|
1576 |
|
|
o_spi_wr <= 1'b1;
|
1577 |
|
|
o_spi_hold <= 1'b0;
|
1578 |
|
|
o_spi_word[31:24] <= 8'h05;
|
1579 |
|
|
o_spi_dir <= 1'b0;
|
1580 |
|
|
o_spi_len <= 2'b00;
|
1581 |
|
|
if (accepted)
|
1582 |
|
|
id_state <= `ID_REQ_STATUS_NEXT;
|
1583 |
|
|
end
|
1584 |
|
|
`ID_REQ_STATUS_NEXT: begin
|
1585 |
|
|
o_spi_wr <= 1'b1;
|
1586 |
|
|
o_spi_hold <= 1'b0;
|
1587 |
|
|
o_spi_dir <= 1'b1; // Read
|
1588 |
|
|
o_spi_len <= 2'b00; // 8 bits
|
1589 |
|
|
// o_spi_word <= dont care
|
1590 |
|
|
if (accepted)
|
1591 |
|
|
id_state <= `ID_READ_STATUS;
|
1592 |
|
|
end
|
1593 |
|
|
`ID_READ_STATUS: begin
|
1594 |
|
|
o_spi_wr <= 1'b1;
|
1595 |
|
|
o_spi_hold <= 1'b0;
|
1596 |
|
|
o_spi_dir <= 1'b1; // Read
|
1597 |
|
|
o_spi_len <= 2'b00; // 8 bits
|
1598 |
|
|
// o_spi_word <= dont care
|
1599 |
|
|
if (i_spi_valid)
|
1600 |
|
|
chk_wip <= 1'b1;
|
1601 |
|
|
if ((chk_wip)&&(~i_spi_data[0]))
|
1602 |
|
|
begin
|
1603 |
|
|
o_wip <= 1'b0;
|
1604 |
|
|
id_state <= `ID_FINAL_STOP;
|
1605 |
|
|
end end
|
1606 |
|
|
default: begin // ID_FINAL_STOP
|
1607 |
|
|
o_bus_ack <= 1'b0;
|
1608 |
|
|
nxt_data_ack <= 1'b0;
|
1609 |
|
|
o_qspi_req <= 1'b0;
|
1610 |
|
|
o_spi_wr <= 1'b0;
|
1611 |
|
|
o_spi_hold <= 1'b0;
|
1612 |
|
|
o_spi_dir <= 1'b1; // Read
|
1613 |
|
|
o_spi_len <= 2'b00; // 8 bits
|
1614 |
|
|
// o_spi_word <= dont care
|
1615 |
|
|
if (i_spi_stopped)
|
1616 |
|
|
id_state <= `ID_IDLE;
|
1617 |
|
|
end
|
1618 |
|
|
endcase
|
1619 |
|
|
end
|
1620 |
|
|
|
1621 |
|
|
always @(posedge i_clk)
|
1622 |
|
|
begin
|
1623 |
|
|
if (nxt_data_ack)
|
1624 |
|
|
o_data <= (nxt_data_spi)?i_spi_data : nxt_data;
|
1625 |
|
|
o_data_ack <= nxt_data_ack;
|
1626 |
|
|
end
|
1627 |
|
|
|
1628 |
|
|
always @(posedge i_clk)
|
1629 |
|
|
if (set_val)
|
1630 |
|
|
idmem[set_addr] <= i_spi_data;
|
1631 |
|
|
|
1632 |
|
|
assign o_spi_spd = 1'b0; // Slow, 1-bit at a time
|
1633 |
|
|
|
1634 |
|
|
endmodule
|
1635 |
|
|
|
1636 |
|
|
|
1637 |
|
|
|