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[/] [qspiflash/] [trunk/] [rtl/] [llqspi.v] - Blame information for rev 7

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1 3 dgisselq
///////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3
// Filename:    llqspi.v
4
//
5 3 dgisselq
// Project:     Wishbone Controlled Quad SPI Flash Controller
6 2 dgisselq
//
7
// Purpose:     Reads/writes a word (user selectable number of bytes) of data
8
//              to/from a Quad SPI port.  The port is understood to be 
9
//              a normal SPI port unless the driver requests four bit mode.
10
//              When not in use, unlike our previous SPI work, no bits will
11
//              toggle.
12
//
13
// Creator:     Dan Gisselquist
14
//              Gisselquist Tecnology, LLC
15
//
16 3 dgisselq
///////////////////////////////////////////////////////////////////////////
17 2 dgisselq
//
18 3 dgisselq
// Copyright (C) 2015, Gisselquist Technology, LLC
19 2 dgisselq
//
20 3 dgisselq
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// You should have received a copy of the GNU General Public License along
31
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
32
// target there if the PDF file isn't present.)  If not, see
33
// <http://www.gnu.org/licenses/> for a copy.
34
//
35
// License:     GPL, v3, as defined and found on www.gnu.org,
36
//              http://www.gnu.org/licenses/gpl.html
37
//
38
//
39
///////////////////////////////////////////////////////////////////////////
40 4 dgisselq
`define QSPI_IDLE       3'h0
41
`define QSPI_START      3'h1
42
`define QSPI_BITS       3'h2
43
`define QSPI_READY      3'h3
44
`define QSPI_HOLDING    3'h4
45
`define QSPI_STOP       3'h5
46
`define QSPI_STOP_B     3'h6
47 2 dgisselq
 
48
// Modes
49
`define QSPI_MOD_SPI    2'b00
50
`define QSPI_MOD_QOUT   2'b10
51
`define QSPI_MOD_QIN    2'b11
52
 
53
module  llqspi(i_clk,
54
                // Module interface
55
                i_wr, i_hold, i_word, i_len, i_spd, i_dir,
56
                        o_word, o_valid, o_busy,
57
                // QSPI interface
58 3 dgisselq
                o_sck, o_cs_n, o_mod, o_dat, i_dat);
59 2 dgisselq
        input                   i_clk;
60
        // Chip interface
61
        //      Can send info
62
        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
63
        //                      i_word = { 1'b0, 32'info to send },
64
        //                      i_len = # of bytes in word-1
65
        input                   i_wr, i_hold;
66
        input           [31:0]   i_word;
67
        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
68
        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
69
        input                   i_dir; // 0 -> read, 1 -> write to SPI
70
        output  reg     [31:0]   o_word;
71
        output  reg             o_valid, o_busy;
72
        // Interface with the QSPI lines
73
        output  reg             o_sck;
74
        output  reg             o_cs_n;
75
        output  reg     [1:0]    o_mod;
76
        output  reg     [3:0]    o_dat;
77
        input           [3:0]    i_dat;
78
 
79 7 dgisselq
        // output       wire    [22:0]  o_dbg;
80
        // assign       o_dbg = { state, spi_len,
81
                // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
82
 
83 2 dgisselq
        // Timing:
84
        //
85
        //      Tick    Clk     BSY/WR  CS_n    BIT/MO  STATE
86
        //       0      1       0/0     1        -      
87
        //       1      1       0/1     1        -
88
        //       2      1       1/0     0         -      QSPI_START
89
        //       3      0        1/0     0         -      QSPI_START
90
        //       4      0        1/0     0         0      QSPI_BITS
91
        //       5      1       1/0     0         0      QSPI_BITS
92
        //       6      0        1/0     0         1      QSPI_BITS
93
        //       7      1       1/0     0         1      QSPI_BITS
94
        //       8      0        1/0     0         2      QSPI_BITS
95
        //       9      1       1/0     0         2      QSPI_BITS
96
        //      10      0        1/0     0         3      QSPI_BITS
97
        //      11      1       1/0     0         3      QSPI_BITS
98
        //      12      0        1/0     0         4      QSPI_BITS
99
        //      13      1       1/0     0         4      QSPI_BITS
100
        //      14      0        1/0     0         5      QSPI_BITS
101
        //      15      1       1/0     0         5      QSPI_BITS
102
        //      16      0        1/0     0         6      QSPI_BITS
103
        //      17      1       1/1     0         6      QSPI_BITS
104
        //      18      0        1/1     0         7      QSPI_READY
105
        //      19      1       0/1     0         7      QSPI_READY
106
        //      20      0        1/0/V   0         8      QSPI_BITS
107
        //      21      1       1/0     0         8      QSPI_BITS
108
        //      22      0        1/0     0         9      QSPI_BITS
109
        //      23      1       1/0     0         9      QSPI_BITS
110
        //      24      0        1/0     0        10      QSPI_BITS
111
        //      25      1       1/0     0        10      QSPI_BITS
112
        //      26      0        1/0     0        11      QSPI_BITS
113
        //      27      1       1/0     0        11      QSPI_BITS
114
        //      28      0        1/0     0        12      QSPI_BITS
115
        //      29      1       1/0     0        12      QSPI_BITS
116
        //      30      0        1/0     0        13      QSPI_BITS
117
        //      31      1       1/0     0        13      QSPI_BITS
118
        //      32      0        1/0     0        14      QSPI_BITS
119
        //      33      1       1/0     0        14      QSPI_BITS
120
        //      34      0        1/0     0        15      QSPI_READY
121
        //      35      1       1/0     0        15      QSPI_READY
122
        //      36      1       1/0/V   0         -      QSPI_STOP
123
        //      37      1       1/0     0         -      QSPI_STOPB
124
        //      38      1       1/0     1        -      QSPI_IDLE
125
        //      39      1       0/0     1        -
126
        // Now, let's switch from single bit to quad mode
127
        //      40      1       0/0     1        -      QSPI_IDLE
128
        //      41      1       0/1     1        -      QSPI_IDLE
129
        //      42      1       1/0     0         -      QSPI_START
130
        //      43      0        1/0     0         -      QSPI_START
131
        //      44      0        1/0     0         0      QSPI_BITS
132
        //      45      1       1/0     0         0      QSPI_BITS
133
        //      46      0        1/0     0         1      QSPI_BITS
134
        //      47      1       1/0     0         1      QSPI_BITS
135
        //      48      0        1/0     0         2      QSPI_BITS
136
        //      49      1       1/0     0         2      QSPI_BITS
137
        //      50      0        1/0     0         3      QSPI_BITS
138
        //      51      1       1/0     0         3      QSPI_BITS
139
        //      52      0        1/0     0         4      QSPI_BITS
140
        //      53      1       1/0     0         4      QSPI_BITS
141
        //      54      0        1/0     0         5      QSPI_BITS
142
        //      55      1       1/0     0         5      QSPI_BITS
143
        //      56      0        1/0     0         6      QSPI_BITS
144
        //      57      1       1/1/QR  0         6      QSPI_BITS
145
        //      58      0        1/1/QR  0         7      QSPI_READY
146
        //      59      1       0/1/QR  0         7      QSPI_READY
147
        //      60      0        1/0/?/V 0         8-11   QSPI_BITS
148
        //      61      1       1/0/?   0         8-11   QSPI_BITS
149
        //      62      0        1/0/?   0         12-15  QSPI_BITS
150
        //      63      1       1/0/?   0         12-15  QSPI_BITS
151
        //      64      1       1/0/?/V 0        -       QSPI_STOP
152
        //      65      1       1/0/?   0        -       QSPI_STOPB
153
        //      66      1       1/0/?   1       -       QSPI_IDLE
154
        //      67      1       0/0     1       -       QSPI_IDLE
155
        // Now let's try something entirely in Quad read mode, from the
156
        // beginning
157
        //      68      1       0/1/QR  1       -       QSPI_IDLE
158
        //      69      1       1/0     0        -       QSPI_START
159
        //      70      0        1/0     0        -       QSPI_START
160
        //      71      0        1/0     0        0-3     QSPI_BITS
161
        //      72      1       1/0     0        0-3     QSPI_BITS
162
        //      73      0        1/1/QR  0        4-7     QSPI_BITS
163
        //      74      1       0/1/QR  0        4-7     QSPI_BITS
164
        //      75      0        1/?/?/V 0        8-11    QSPI_BITS
165
        //      76      1       1/?/?   0        8-11    QSPI_BITS
166
        //      77      0        1/1/QR  0        12-15   QSPI_BITS
167
        //      78      1       0/1/QR  0        12-15   QSPI_BITS
168
        //      79      0        1/?/?/V 0        16-19   QSPI_BITS
169
        //      80      1       1/0     0        16-19   QSPI_BITS
170
        //      81      0        1/0     0        20-23   QSPI_BITS
171
        //      82      1       1/0     0        20-23   QSPI_BITS
172
        //      83      1       1/0/V   0        -       QSPI_STOP
173
        //      84      1       1/0     0        -       QSPI_STOPB
174
        //      85      1       1/0     1       -       QSPI_IDLE
175
        //      86      1       0/0     1       -       QSPI_IDLE
176
 
177
        wire    i_miso;
178
        assign  i_miso = i_dat[1];
179
 
180
        reg             r_spd, r_dir;
181
        reg     [5:0]    spi_len;
182
        reg     [31:0]   r_word;
183
        reg     [30:0]   r_input;
184
        reg     [2:0]    state;
185
        initial state = `QSPI_IDLE;
186
        initial o_sck   = 1'b1;
187
        initial o_cs_n  = 1'b1;
188
        initial o_dat   = 4'hd;
189
        initial o_valid = 1'b0;
190
        initial o_busy  = 1'b0;
191
        initial r_input = 31'h000;
192
        always @(posedge i_clk)
193
                if ((state == `QSPI_IDLE)&&(o_sck))
194
                begin
195
                        o_cs_n <= 1'b1;
196
                        o_valid <= 1'b0;
197
                        o_busy  <= 1'b0;
198
                        o_mod <= `QSPI_MOD_SPI;
199
                        if (i_wr)
200
                        begin
201
                                r_word <= i_word;
202
                                state <= `QSPI_START;
203
                                r_spd <= i_spd;
204
                                r_dir <= i_dir;
205
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
206
                                o_cs_n <= 1'b0;
207
                                o_busy <= 1'b1;
208
                                o_sck <= 1'b1;
209
                        end
210
                end else if (state == `QSPI_START)
211
                begin // We come in here with sck high, stay here 'til sck is low
212
                        o_sck <= 1'b0;
213
                        if (o_sck == 1'b0)
214
                        begin
215
                                state <= `QSPI_BITS;
216
                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
217
                                if (r_spd)
218
                                        r_word <= { r_word[27:0], 4'h0 };
219
                                else
220
                                        r_word <= { r_word[30:0], 1'b0 };
221
                        end
222
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
223
                        o_cs_n <= 1'b0;
224
                        o_busy <= 1'b1;
225
                        o_valid <= 1'b0;
226
                        if (r_spd)
227
                        begin
228
                                o_dat <= r_word[31:28];
229
                                // r_word <= { r_word[27:0], 4'h0 };
230
                        end else begin
231
                                o_dat <= { 3'b110, r_word[31] };
232
                                // r_word <= { r_word[30:0], 1'b0 };
233
                        end
234
                end else if (~o_sck)
235
                begin
236
                        o_sck <= 1'b1;
237
                        o_busy <= ((state != `QSPI_READY)||(~i_wr));
238
                        o_valid <= 1'b0;
239
                end else if (state == `QSPI_BITS)
240
                begin
241
                        // Should enter into here with at least a spi_len
242
                        // of one, perhaps more
243
                        o_sck <= 1'b0;
244
                        o_busy <= 1'b1;
245
                        if (r_spd)
246
                        begin
247
                                o_dat <= r_word[31:28];
248
                                r_word <= { r_word[27:0], 4'h0 };
249
                                spi_len <= spi_len - 6'h4;
250
                                if (spi_len == 6'h4)
251
                                        state <= `QSPI_READY;
252
                        end else begin
253
                                o_dat <= { 3'b110, r_word[31] };
254
                                r_word <= { r_word[30:0], 1'b0 };
255
                                spi_len <= spi_len - 6'h1;
256
                                if (spi_len == 6'h1)
257
                                        state <= `QSPI_READY;
258
                        end
259
 
260
                        o_valid <= 1'b0;
261
                        if (~o_mod[1])
262
                                r_input <= { r_input[29:0], i_miso };
263
                        else if (o_mod[1])
264
                                r_input <= { r_input[26:0], i_dat };
265
                end else if (state == `QSPI_READY)
266
                begin
267
                        o_valid <= 1'b0;
268
                        o_cs_n <= 1'b0;
269
                        o_busy <= 1'b1;
270
                        // This is the state on the last clock (both low and
271
                        // high clocks) of the data.  Data is valid during
272
                        // this state.  Here we chose to either STOP or
273
                        // continue and transmit more.
274 4 dgisselq
                        o_sck <= (i_hold); // No clocks while holding
275 2 dgisselq
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
276
                        begin
277
                                state <= `QSPI_BITS;
278
                                o_busy <= 1'b1;
279
                                o_sck <= 1'b0;
280
 
281
                                // Read the new request off the bus
282
                                r_spd <= i_spd;
283
                                r_dir <= i_dir;
284
                                // Set up the first bits on the bus
285
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
286
                                if (i_spd)
287
                                begin
288
                                        o_dat <= i_word[31:28];
289
                                        r_word <= { i_word[27:0], 4'h0 };
290
                                        // spi_len <= spi_len - 4;
291
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
292
                                                - 6'h4;
293
                                end else begin
294
                                        o_dat <= { 3'b110, i_word[31] };
295
                                        r_word <= { i_word[30:0], 1'b0 };
296
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
297
                                                - 6'h1;
298
                                end
299
 
300
                                // Read a bit upon any transition
301
                                o_valid <= 1'b1;
302
                                if (~o_mod[1])
303
                                begin
304
                                        r_input <= { r_input[29:0], i_miso };
305
                                        o_word  <= { r_input[30:0], i_miso };
306
                                end else if (o_mod[1])
307
                                begin
308
                                        r_input <= { r_input[26:0], i_dat };
309
                                        o_word  <= { r_input[27:0], i_dat };
310
                                end
311
                        end else begin
312
                                o_sck <= 1'b1;
313 4 dgisselq
                                state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
314
                                o_busy <= (~i_hold);
315 2 dgisselq
 
316
                                // Read a bit upon any transition
317
                                o_valid <= 1'b1;
318
                                if (~o_mod[1])
319
                                begin
320
                                        r_input <= { r_input[29:0], i_miso };
321
                                        o_word  <= { r_input[30:0], i_miso };
322
                                end else if (o_mod[1])
323
                                begin
324
                                        r_input <= { r_input[26:0], i_dat };
325
                                        o_word  <= { r_input[27:0], i_dat };
326
                                end
327
                        end
328 4 dgisselq
                end else if (state == `QSPI_HOLDING)
329
                begin
330
                        // We need this state so that the o_valid signal
331
                        // can get strobed with our last result.  Otherwise
332
                        // we could just sit in READY waiting for a new command.
333
                        //
334
                        // Incidentally, the change producing this state was
335
                        // the result of a nasty race condition.  See the
336
                        // commends in wbqspiflash for more details.
337
                        //
338
                        o_valid <= 1'b0;
339
                        o_cs_n <= 1'b0;
340
                        o_busy <= 1'b0;
341
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
342
                        begin
343
                                state  <= `QSPI_BITS;
344
                                o_busy <= 1'b1;
345
                                o_sck  <= 1'b0;
346
 
347
                                // Read the new request off the bus
348
                                r_spd <= i_spd;
349
                                r_dir <= i_dir;
350
                                // Set up the first bits on the bus
351
                                o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
352
                                if (i_spd)
353
                                begin
354
                                        o_dat <= i_word[31:28];
355
                                        r_word <= { i_word[27:0], 4'h0 };
356
                                        spi_len<= { 1'b0, i_len, 3'b100 };
357
                                end else begin
358
                                        o_dat <= { 3'b110, i_word[31] };
359
                                        r_word <= { i_word[30:0], 1'b0 };
360
                                        spi_len<= { 1'b0, i_len, 3'b111 };
361
                                end
362
                        end else begin
363
                                o_sck <= 1'b1;
364
                                state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
365
                                o_busy <= (~i_hold);
366
                        end
367 2 dgisselq
                end else if (state == `QSPI_STOP)
368
                begin
369
                        o_sck   <= 1'b1; // Stop the clock
370
                        o_valid <= 1'b0; // Output may have just been valid, but no more
371
                        o_busy  <= 1'b1; // Still busy till port is clear
372
                        state <= `QSPI_STOP_B;
373
                        o_mod <= `QSPI_MOD_SPI;
374
                end else if (state == `QSPI_STOP_B)
375
                begin
376
                        o_cs_n <= 1'b1;
377
                        o_sck <= 1'b1;
378
                        // Do I need this????
379
                        // spi_len <= 3; // Minimum CS high time before next cmd
380
                        state <= `QSPI_IDLE;
381
                        o_valid <= 1'b0;
382
                        o_busy <= 1'b1;
383
                        o_mod <= `QSPI_MOD_SPI;
384
                end else begin // Invalid states, should never get here
385
                        state   <= `QSPI_STOP;
386
                        o_valid <= 1'b0;
387
                        o_busy  <= 1'b1;
388
                        o_cs_n  <= 1'b1;
389
                        o_sck   <= 1'b1;
390
                        o_mod   <= `QSPI_MOD_SPI;
391
                        o_dat   <= 4'hd;
392
                end
393
 
394
endmodule
395
 

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