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[/] [qspiflash/] [trunk/] [rtl/] [wbqspiflash.v] - Blame information for rev 16

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1 14 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3
// Filename:    wbspiflash.v
4
//
5 3 dgisselq
// Project:     Wishbone Controlled Quad SPI Flash Controller
6 2 dgisselq
//
7
// Purpose:     Access a Quad SPI flash via a WISHBONE interface.  This
8
//              includes both read and write (and erase) commands to the SPI
9
//              flash.  All read/write commands are accomplished using the
10
//              high speed (4-bit) interface.  Further, the device will be
11
//              left/kept in the 4-bit read interface mode between accesses,
12
//              for a minimum read latency.
13
//
14 3 dgisselq
//      Wishbone Registers (See spec sheet for more detail):
15 2 dgisselq
//      0: local config(r) / erase commands(w) / deep power down cmds / etc.
16
//      R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
17
//              { last_erased_sector, 14'h00 } if (WIP)
18
//              else { current_sector_being_erased, 14'h00 }
19
//              current if write in progress, last if written
20
//      W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
21 3 dgisselq
//      1: Configuration register
22
//      2: Status register (R/w)
23
//      3: Read ID (read only)
24 2 dgisselq
//      (19 bits): Data (R/w, but expect writes to take a while)
25
//              
26
//
27 14 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
28 8 dgisselq
//              Gisselquist Technology, LLC
29 2 dgisselq
//
30 14 dgisselq
////////////////////////////////////////////////////////////////////////////////
31 2 dgisselq
//
32 14 dgisselq
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
33 2 dgisselq
//
34 3 dgisselq
// This program is free software (firmware): you can redistribute it and/or
35
// modify it under the terms of  the GNU General Public License as published
36
// by the Free Software Foundation, either version 3 of the License, or (at
37
// your option) any later version.
38
//
39
// This program is distributed in the hope that it will be useful, but WITHOUT
40
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
41
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
42
// for more details.
43
//
44
// You should have received a copy of the GNU General Public License along
45 14 dgisselq
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
46 3 dgisselq
// target there if the PDF file isn't present.)  If not, see
47
// <http://www.gnu.org/licenses/> for a copy.
48
//
49
// License:     GPL, v3, as defined and found on www.gnu.org,
50
//              http://www.gnu.org/licenses/gpl.html
51
//
52
//
53 14 dgisselq
////////////////////////////////////////////////////////////////////////////////
54 7 dgisselq
//
55
`include "flash_config.v"
56 14 dgisselq
`default_nettype        none
57 7 dgisselq
//
58 16 dgisselq
`define WBQSPI_RESET            5'd0
59
`define WBQSPI_RESET_QUADMODE   5'd1
60
`define WBQSPI_IDLE             5'd2
61
`define WBQSPI_RDIDLE           5'd3    // Idle, but in fast read mode
62
`define WBQSPI_WBDECODE         5'd4
63
`define WBQSPI_RD_DUMMY         5'd5
64
`define WBQSPI_QRD_ADDRESS      5'd6
65
`define WBQSPI_QRD_DUMMY        5'd7
66
`define WBQSPI_READ_CMD         5'd8
67
`define WBQSPI_READ_DATA        5'd9
68
`define WBQSPI_WAIT_TIL_RDIDLE  5'd10
69
`define WBQSPI_READ_ID_CMD      5'd11
70
`define WBQSPI_READ_ID          5'd12
71
`define WBQSPI_READ_STATUS      5'd13
72
`define WBQSPI_READ_CONFIG      5'd14
73
`define WBQSPI_WAIT_TIL_IDLE    5'd15
74 7 dgisselq
//
75
//
76
`ifndef READ_ONLY
77
//
78 16 dgisselq
`define WBQSPI_WAIT_WIP_CLEAR   5'd16
79
`define WBQSPI_CHECK_WIP_CLEAR  5'd17
80
`define WBQSPI_CHECK_WIP_DONE   5'd18
81
`define WBQSPI_WEN              5'd19
82
`define WBQSPI_PP               5'd20   // Program page
83
`define WBQSPI_QPP              5'd21   // Program page, 4 bit mode
84
`define WBQSPI_WR_DATA          5'd22
85
`define WBQSPI_WR_BUS_CYCLE     5'd23
86
`define WBQSPI_WRITE_STATUS     5'd24
87
`define WBQSPI_WRITE_CONFIG     5'd25
88
`define WBQSPI_ERASE_WEN        5'd26
89
`define WBQSPI_ERASE_CMD        5'd27
90
`define WBQSPI_ERASE_BLOCK      5'd28
91
`define WBQSPI_CLEAR_STATUS     5'd29
92
`define WBQSPI_IDLE_CHECK_WIP   5'd30
93 7 dgisselq
//
94
`endif
95 2 dgisselq
 
96 16 dgisselq
module  wbqspiflash(i_clk,
97 2 dgisselq
                // Internal wishbone connections
98
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
99
                i_wb_addr, i_wb_data,
100
                // Wishbone return values
101
                o_wb_ack, o_wb_stall, o_wb_data,
102
                // Quad Spi connections to the external device
103
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
104 3 dgisselq
                o_interrupt);
105 7 dgisselq
        parameter       ADDRESS_WIDTH=22;
106 16 dgisselq
        localparam      AW = ADDRESS_WIDTH-2;
107
        input   wire            i_clk;
108 2 dgisselq
        // Wishbone, inputs first
109 14 dgisselq
        input   wire            i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
110 16 dgisselq
        input   wire    [(AW-1):0]       i_wb_addr;
111 14 dgisselq
        input   wire    [31:0]   i_wb_data;
112 2 dgisselq
        // then outputs
113
        output  reg             o_wb_ack;
114
        output  reg             o_wb_stall;
115
        output  reg     [31:0]   o_wb_data;
116
        // Quad SPI control wires
117
        output  wire            o_qspi_sck, o_qspi_cs_n;
118
        output  wire    [1:0]    o_qspi_mod;
119
        output  wire    [3:0]    o_qspi_dat;
120 14 dgisselq
        input   wire    [3:0]    i_qspi_dat;
121 2 dgisselq
        // Interrupt line
122
        output  reg             o_interrupt;
123 7 dgisselq
        // output       wire    [31:0]  o_debug;
124 2 dgisselq
 
125
        reg             spi_wr, spi_hold, spi_spd, spi_dir;
126
        reg     [31:0]   spi_in;
127
        reg     [1:0]    spi_len;
128
        wire    [31:0]   spi_out;
129
        wire            spi_valid, spi_busy;
130 4 dgisselq
        wire            w_qspi_sck, w_qspi_cs_n;
131
        wire    [3:0]    w_qspi_dat;
132
        wire    [1:0]    w_qspi_mod;
133 7 dgisselq
        // wire [22:0]  spi_dbg;
134 16 dgisselq
        llqspi  lldriver(i_clk,
135 2 dgisselq
                        spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
136
                                spi_out, spi_valid, spi_busy,
137 4 dgisselq
                        w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
138 3 dgisselq
                                i_qspi_dat);
139 2 dgisselq
 
140
        // Erase status tracking
141
        reg             write_in_progress, write_protect;
142 7 dgisselq
        reg     [(ADDRESS_WIDTH-17):0]   erased_sector;
143 2 dgisselq
        reg             dirty_sector;
144
        initial begin
145
                write_in_progress = 1'b0;
146 7 dgisselq
                erased_sector = 0;
147 2 dgisselq
                dirty_sector  = 1'b1;
148
                write_protect = 1'b1;
149
        end
150
 
151 14 dgisselq
        wire    [23:0]   w_wb_addr;
152
        generate
153
        if (ADDRESS_WIDTH>=24)
154
                assign w_wb_addr = { i_wb_addr[21:0], 2'b00 };
155
        else
156
                assign w_wb_addr = { {(24-ADDRESS_WIDTH){1'b0}}, i_wb_addr, 2'b00 };
157
        endgenerate
158
 
159
        // Repeat for spif_addr
160
        reg     [(ADDRESS_WIDTH-3):0]    spif_addr;
161
        wire    [23:0]   w_spif_addr;
162
        generate
163
        if (ADDRESS_WIDTH>=24)
164
                assign w_spif_addr = { spif_addr[21:0], 2'b00 };
165
        else
166
                assign w_spif_addr = { {(24-ADDRESS_WIDTH){1'b0}}, spif_addr, 2'b00 };
167
        endgenerate
168
 
169 2 dgisselq
        reg     [7:0]    last_status;
170 16 dgisselq
        reg     [9:0]    reset_counter;
171 2 dgisselq
        reg             quad_mode_enabled;
172 4 dgisselq
        reg             spif_cmd, spif_override;
173 2 dgisselq
        reg     [31:0]   spif_data;
174 14 dgisselq
        reg     [4:0]    state;
175 2 dgisselq
        reg             spif_ctrl, spif_req;
176 16 dgisselq
        reg             alt_cmd, alt_ctrl;
177 7 dgisselq
        wire    [(ADDRESS_WIDTH-17):0]   spif_sector;
178 16 dgisselq
        assign  spif_sector = spif_addr[(AW-1):14];
179 2 dgisselq
 
180 7 dgisselq
        // assign       o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
181
 
182 2 dgisselq
        initial state = `WBQSPI_RESET;
183
        initial o_wb_ack   = 1'b0;
184
        initial o_wb_stall = 1'b1;
185
        initial spi_wr     = 1'b0;
186
        initial spi_len    = 2'b00;
187
        initial quad_mode_enabled = 1'b0;
188
        initial o_interrupt = 1'b0;
189 16 dgisselq
        initial spif_override = 1'b1;
190
        initial spif_ctrl     = 1'b0;
191
        always @(posedge i_clk)
192 4 dgisselq
        begin
193
        spif_override <= 1'b0;
194 16 dgisselq
        alt_cmd  <= (reset_counter[9:8]==2'b10)?reset_counter[3]:1'b1; // Toggle CS_n
195
        alt_ctrl <= (reset_counter[9:8]==2'b10)?reset_counter[0]:1'b1; // Toggle clock too
196 2 dgisselq
        if (state == `WBQSPI_RESET)
197
        begin
198
                // From a reset, we should
199
                //      Enable the Quad I/O mode
200
                //      Disable the Write protection bits in the status register
201
                //      Chip should already be up and running, so we can start
202
                //      immediately ....
203
                o_wb_ack <= 1'b0;
204
                o_wb_stall <= 1'b1;
205 4 dgisselq
                spi_wr   <= 1'b0;
206 2 dgisselq
                spi_hold <= 1'b0;
207
                spi_spd  <= 1'b0;
208
                spi_dir  <= 1'b0;
209
                last_status <= 8'h00;
210 4 dgisselq
                state <= `WBQSPI_RESET_QUADMODE;
211 2 dgisselq
                spif_req <= 1'b0;
212 4 dgisselq
                spif_override <= 1'b1;
213 16 dgisselq
                last_status   <= 8'h00; //
214
                reset_counter <= 10'h3fc; //
215 4 dgisselq
                        // This guarantees that we aren't starting in quad
216
                        // I/O mode, where the FPGA configuration scripts may
217
                        // have left us.
218
        end else if (state == `WBQSPI_RESET_QUADMODE)
219 2 dgisselq
        begin
220 4 dgisselq
                // Okay, so here's the problem: we don't know whether or not
221
                // the Xilinx loader started us up in Quad Read I/O idle mode.
222 14 dgisselq
                // So, thus we need to toggle the clock and CS_n, with fewer
223
                // clocks than are necessary to transmit a word.
224
                //
225 4 dgisselq
                // Not ready to handle the bus yet, so stall any requests
226
                o_wb_ack   <= 1'b0;
227
                o_wb_stall <= 1'b1;
228
 
229
                // Do something ...
230 16 dgisselq
                if (reset_counter == 10'h00)
231 2 dgisselq
                begin
232 4 dgisselq
                        spif_override <= 1'b0;
233
                        state <= `WBQSPI_IDLE;
234 16 dgisselq
 
235
                        // Find out if we can use Quad I/O mode ...
236
                        state <= `WBQSPI_READ_CONFIG;
237
                        spi_wr <= 1'b1;
238
                        spi_len <= 2'b01;
239
                        spi_in <= { 8'h35, 24'h00};
240
 
241 4 dgisselq
                end else begin
242 16 dgisselq
                        reset_counter <= reset_counter - 10'h1;
243 4 dgisselq
                        spif_override <= 1'b1;
244 2 dgisselq
                end
245
        end else if (state == `WBQSPI_IDLE)
246
        begin
247
                o_interrupt <= 1'b0;
248
                o_wb_stall <= 1'b0;
249
                o_wb_ack <= 1'b0;
250
                spif_cmd   <= i_wb_we;
251
                spif_addr  <= i_wb_addr;
252
                spif_data  <= i_wb_data;
253
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
254
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
255
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
256
                spi_hold <= 1'b0;
257
                spi_spd  <= 1'b0;
258
                spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
259
                // Data register access
260 14 dgisselq
                if (i_wb_data_stb)
261 2 dgisselq
                begin
262
 
263
                        if (i_wb_we) // Request to write a page
264
                        begin
265 7 dgisselq
`ifdef  READ_ONLY
266
                                o_wb_ack <= 1'b1;
267
                                o_wb_stall <= 1'b0;
268
                        end else
269
`else
270 2 dgisselq
                                if((~write_protect)&&(~write_in_progress))
271
                                begin // 00
272
                                        spi_wr <= 1'b1;
273
                                        spi_len <= 2'b00; // 8 bits
274
                                        // Send a write enable command
275
                                        spi_in <= { 8'h06, 24'h00 };
276
                                        state <= `WBQSPI_WEN;
277
 
278
                                        o_wb_ack <= 1'b0;
279
                                        o_wb_stall <= 1'b1;
280
                                end else if (write_protect)
281
                                begin // whether or not write-in_progress ...
282
                                        // Do nothing on a write protect
283
                                        // violation
284
                                        //
285
                                        o_wb_ack <= 1'b1;
286
                                        o_wb_stall <= 1'b0;
287
                                end else begin // write is in progress, wait
288
                                        // for it to complete
289
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
290
                                        o_wb_ack <= 1'b0;
291
                                        o_wb_stall <= 1'b1;
292
                                end
293
                        end else if (~write_in_progress)
294 7 dgisselq
`endif
295 2 dgisselq
                        begin // Read access, normal mode(s)
296
                                o_wb_ack   <= 1'b0;
297
                                o_wb_stall <= 1'b1;
298
                                spi_wr     <= 1'b1;     // Write cmd to device
299
                                if (quad_mode_enabled)
300
                                begin
301 14 dgisselq
                                        spi_in <= { 8'heb, w_wb_addr };
302 2 dgisselq
                                        state <= `WBQSPI_QRD_ADDRESS;
303
                                        spi_len    <= 2'b00; // single byte, cmd only
304
                                end else begin
305 14 dgisselq
                                        spi_in <= { 8'h0b, w_wb_addr };
306 2 dgisselq
                                        state <= `WBQSPI_RD_DUMMY;
307
                                        spi_len    <= 2'b11; // cmd+addr,32bits
308
                                end
309 7 dgisselq
`ifndef READ_ONLY
310 2 dgisselq
                        end else begin
311
                                // A write is in progress ... need to stall
312
                                // the bus until the write is complete.
313
                                state <= `WBQSPI_WAIT_WIP_CLEAR;
314
                                o_wb_ack   <= 1'b0;
315
                                o_wb_stall <= 1'b1;
316 7 dgisselq
`endif
317 2 dgisselq
                        end
318 14 dgisselq
                end else if ((i_wb_ctrl_stb)&&(i_wb_we))
319 2 dgisselq
                begin
320 7 dgisselq
`ifdef  READ_ONLY
321
                        o_wb_ack   <= 1'b1;
322
                        o_wb_stall <= 1'b0;
323
`else
324 2 dgisselq
                        o_wb_stall <= 1'b1;
325
                        case(i_wb_addr[1:0])
326
                        2'b00: begin // Erase command register
327 16 dgisselq
                                write_protect <= !i_wb_data[28];
328 2 dgisselq
                                o_wb_stall <= 1'b0;
329
 
330 16 dgisselq
                                if((i_wb_data[31])&&(!write_in_progress))
331 2 dgisselq
                                begin
332
                                        // Command an erase--ack it immediately
333
 
334
                                        o_wb_ack <= 1'b1;
335
                                        o_wb_stall <= 1'b0;
336
 
337
                                        if ((i_wb_data[31])&&(~write_protect))
338
                                        begin
339
                                                spi_wr <= 1'b1;
340
                                                spi_len <= 2'b00;
341
                                                // Send a write enable command
342
                                                spi_in <= { 8'h06, 24'h00 };
343
                                                state <= `WBQSPI_ERASE_CMD;
344
                                                o_wb_stall <= 1'b1;
345
                                        end
346
                                end else if (i_wb_data[31])
347
                                begin
348
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
349
                                        o_wb_ack   <= 1'b1;
350
                                        o_wb_stall <= 1'b1;
351
                                end else
352
                                        o_wb_ack   <= 1'b1;
353
                                        o_wb_stall <= 1'b0;
354
                                end
355
                        2'b01: begin
356
                                // Write the configuration register
357
                                o_wb_ack <= 1'b1;
358
                                o_wb_stall <= 1'b1;
359
 
360
                                // Need to send a write enable command first
361
                                spi_wr <= 1'b1;
362
                                spi_len <= 2'b00; // 8 bits
363
                                // Send a write enable command
364
                                spi_in <= { 8'h06, 24'h00 };
365
                                state <= `WBQSPI_WRITE_CONFIG;
366
                                end
367
                        2'b10: begin
368
                                // Write the status register
369
                                o_wb_ack <= 1'b1; // Ack immediately
370
                                o_wb_stall <= 1'b1; // Stall other cmds
371
                                // Need to send a write enable command first
372
                                spi_wr <= 1'b1;
373
                                spi_len <= 2'b00; // 8 bits
374
                                // Send a write enable command
375
                                spi_in <= { 8'h06, 24'h00 };
376
                                state <= `WBQSPI_WRITE_STATUS;
377
                                end
378
                        2'b11: begin // Write the ID register??? makes no sense
379
                                o_wb_ack <= 1'b1;
380
                                o_wb_stall <= 1'b0;
381
                                end
382
                        endcase
383 7 dgisselq
`endif
384 16 dgisselq
                end else if (i_wb_ctrl_stb) // &&(!i_wb_we))
385 2 dgisselq
                begin
386
                        case(i_wb_addr[1:0])
387
                        2'b00: begin // Read local register
388
                                if (write_in_progress) // Read status
389
                                begin// register, is write still in progress?
390
                                        state <= `WBQSPI_READ_STATUS;
391
                                        spi_wr <= 1'b1;
392
                                        spi_len <= 2'b01;// 8 bits out, 8 bits in
393
                                        spi_in <= { 8'h05, 24'h00};
394
 
395
                                        o_wb_ack <= 1'b0;
396
                                        o_wb_stall <= 1'b1;
397
                                end else begin // Return w/o talking to device
398
                                        o_wb_ack <= 1'b1;
399
                                        o_wb_stall <= 1'b0;
400
                                        o_wb_data <= { write_in_progress,
401
                                                dirty_sector, spi_busy,
402
                                                ~write_protect,
403
                                                quad_mode_enabled,
404 7 dgisselq
                                                {(29-ADDRESS_WIDTH){1'b0}},
405 2 dgisselq
                                                erased_sector, 14'h000 };
406
                                end end
407
                        2'b01: begin // Read configuration register
408
                                state <= `WBQSPI_READ_CONFIG;
409
                                spi_wr <= 1'b1;
410
                                spi_len <= 2'b01;
411
                                spi_in <= { 8'h35, 24'h00};
412
 
413
                                o_wb_ack <= 1'b0;
414
                                o_wb_stall <= 1'b1;
415
                                end
416
                        2'b10: begin // Read status register
417
                                state <= `WBQSPI_READ_STATUS;
418
                                spi_wr <= 1'b1;
419
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
420
                                spi_in <= { 8'h05, 24'h00};
421
 
422
                                o_wb_ack <= 1'b0;
423
                                o_wb_stall <= 1'b1;
424
                                end
425
                        2'b11: begin // Read ID register
426
                                state <= `WBQSPI_READ_ID_CMD;
427
                                spi_wr <= 1'b1;
428
                                spi_len <= 2'b00;
429
                                spi_in <= { 8'h9f, 24'h00};
430
 
431
                                o_wb_ack <= 1'b0;
432
                                o_wb_stall <= 1'b1;
433
                                end
434
                        endcase
435 7 dgisselq
`ifndef READ_ONLY
436 2 dgisselq
                end else if ((~i_wb_cyc)&&(write_in_progress))
437
                begin
438
                        state <= `WBQSPI_IDLE_CHECK_WIP;
439
                        spi_wr <= 1'b1;
440
                        spi_len <= 2'b01; // 8 bits out, 8 bits in
441
                        spi_in <= { 8'h05, 24'h00};
442
 
443
                        o_wb_ack <= 1'b0;
444
                        o_wb_stall <= 1'b1;
445 7 dgisselq
`endif
446 2 dgisselq
                end
447
        end else if (state == `WBQSPI_RDIDLE)
448
        begin
449
                spi_wr <= 1'b0;
450
                o_wb_stall <= 1'b0;
451
                o_wb_ack <= 1'b0;
452
                spif_cmd   <= i_wb_we;
453
                spif_addr  <= i_wb_addr;
454
                spif_data  <= i_wb_data;
455
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
456
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
457
                spi_hold <= 1'b0;
458
                spi_spd<= 1'b1;
459
                spi_dir <= 1'b0; // Write (for now)
460 16 dgisselq
                if ((i_wb_data_stb)&&(!i_wb_we))
461 2 dgisselq
                begin // Continue our read ... send the new address / mode
462
                        o_wb_stall <= 1'b1;
463
                        spi_wr <= 1'b1;
464 4 dgisselq
                        spi_len <= 2'b10; // Write address, but not mode byte
465 14 dgisselq
                        spi_in <= { w_wb_addr, 8'ha0 };
466 2 dgisselq
                        state <= `WBQSPI_QRD_DUMMY;
467 16 dgisselq
                end else if((i_wb_ctrl_stb)&&(!i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
468 2 dgisselq
                begin
469
                        // A local read that doesn't touch the device, so leave
470
                        // the device in its current state
471
                        o_wb_stall <= 1'b0;
472
                        o_wb_ack <= 1'b1;
473
                        o_wb_data <= { write_in_progress,
474
                                        dirty_sector, spi_busy,
475
                                        ~write_protect,
476
                                        quad_mode_enabled,
477 7 dgisselq
                                        {(29-ADDRESS_WIDTH){1'b0}},
478 2 dgisselq
                                        erased_sector, 14'h000 };
479 14 dgisselq
                end else if(((i_wb_ctrl_stb)||(i_wb_data_stb)))
480 2 dgisselq
                begin // Need to release the device from quad mode for all else
481
                        o_wb_ack   <= 1'b0;
482
                        o_wb_stall <= 1'b1;
483
                        spi_wr <= 1'b1;
484
                        spi_len <= 2'b11;
485
                        spi_in <= 32'h00;
486
                        state <= `WBQSPI_WBDECODE;
487
                end
488
        end else if (state == `WBQSPI_WBDECODE)
489
        begin
490
                // We were in quad SPI read mode, and had to get out.
491
                // Now we've got a command (not data read) to read and
492
                // execute.  Accomplish what we would've done while in the
493
                // IDLE state here, save only that we don't have to worry
494
                // about data reads, and we need to operate on a stored
495
                // version of the bus command
496
                o_wb_stall <= 1'b1;
497
                o_wb_ack <= 1'b0;
498
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
499
                spi_hold <= 1'b0;
500
                spi_spd <= 1'b0;
501
                spi_dir <= 1'b0;
502
                spif_req<= (spif_req) && (i_wb_cyc);
503
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
504
                begin
505
                        // Data register access
506
                        if (~spif_ctrl)
507
                        begin
508
                                if (spif_cmd) // Request to write a page
509
                                begin
510 7 dgisselq
`ifdef  READ_ONLY
511
                                        o_wb_ack <= spif_req;
512
                                        o_wb_stall <= 1'b0;
513
                                        state <= `WBQSPI_IDLE;
514
`else
515 2 dgisselq
                                        if((~write_protect)&&(~write_in_progress))
516
                                        begin // 00
517
                                                spi_wr <= 1'b1;
518
                                                spi_len <= 2'b00; // 8 bits
519
                                                // Send a write enable command
520
                                                spi_in <= { 8'h06, 24'h00 };
521
                                                state <= `WBQSPI_WEN;
522
 
523
                                                o_wb_ack <= 1'b0;
524
                                                o_wb_stall <= 1'b1;
525
                                        end else if (write_protect)
526
                                        begin // whether or not write-in_progress ...
527
                                                // Do nothing on a write protect
528
                                                // violation
529
                                                //
530
                                                o_wb_ack <= spif_req;
531
                                                o_wb_stall <= 1'b0;
532
                                                state <= `WBQSPI_IDLE;
533
                                        end else begin // write is in progress, wait
534
                                                // for it to complete
535
                                                state <= `WBQSPI_WAIT_WIP_CLEAR;
536
                                                o_wb_ack <= 1'b0;
537
                                                o_wb_stall <= 1'b1;
538
                                        end
539
                                // end else if (~write_in_progress) // always true
540
                                // but ... we wouldn't get here on a normal read access
541 7 dgisselq
`endif
542 2 dgisselq
                                end else begin
543 7 dgisselq
                                        // Something's wrong, we should never
544
                                        //   get here
545 2 dgisselq
                                        // Attempt to go to idle to recover
546
                                        state <= `WBQSPI_IDLE;
547
                                end
548
                        end else if ((spif_ctrl)&&(spif_cmd))
549
                        begin
550 7 dgisselq
`ifdef  READ_ONLY
551
                                o_wb_ack   <= spif_req;
552
                                o_wb_stall <= 1'b0;
553
                                state <= `WBQSPI_IDLE;
554
`else
555 2 dgisselq
                                o_wb_stall <= 1'b1;
556
                                case(spif_addr[1:0])
557
                                2'b00: begin // Erase command register
558
                                        o_wb_ack   <= spif_req;
559
                                        o_wb_stall <= 1'b0;
560
                                        state <= `WBQSPI_IDLE;
561
                                        write_protect <= ~spif_data[28];
562
                                        // Are we commanding an erase?
563
                                        // We're in read mode, writes cannot
564
                                        // be in progress, so ...
565
                                        if (spif_data[31]) // Command an erase
566
                                        begin
567
                                                // Since we're not going back
568
                                                // to IDLE, we must stall the
569
                                                // bus here
570
                                                o_wb_stall <= 1'b1;
571
                                                spi_wr <= 1'b1;
572
                                                spi_len <= 2'b00;
573
                                                // Send a write enable command
574
                                                spi_in <= { 8'h06, 24'h00 };
575
                                                state <= `WBQSPI_ERASE_CMD;
576
                                        end end
577
                                2'b01: begin
578
                                        // Write the configuration register
579
                                        o_wb_ack <= spif_req;
580
                                        o_wb_stall <= 1'b1;
581
 
582
                                        // Need to send a write enable command first
583
                                        spi_wr <= 1'b1;
584
                                        spi_len <= 2'b00; // 8 bits
585
                                        // Send a write enable command
586
                                        spi_in <= { 8'h06, 24'h00 };
587
                                        state <= `WBQSPI_WRITE_CONFIG;
588
                                        end
589
                                2'b10: begin
590
                                        // Write the status register
591
                                        o_wb_ack <= spif_req; // Ack immediately
592
                                        o_wb_stall <= 1'b1; // Stall other cmds
593
                                        // Need to send a write enable command first
594
                                        spi_wr <= 1'b1;
595
                                        spi_len <= 2'b00; // 8 bits
596
                                        // Send a write enable command
597
                                        spi_in <= { 8'h06, 24'h00 };
598
                                        state <= `WBQSPI_WRITE_STATUS;
599
                                        end
600
                                2'b11: begin // Write the ID register??? makes no sense
601
                                        o_wb_ack <= spif_req;
602
                                        o_wb_stall <= 1'b0;
603
                                        state <= `WBQSPI_IDLE;
604
                                        end
605
                                endcase
606 7 dgisselq
`endif
607 2 dgisselq
                        end else begin // on (~spif_we)
608
                                case(spif_addr[1:0])
609
                                2'b00: begin // Read local register
610
                                        // Nonsense case--would've done this
611
                                        // already
612
                                        state <= `WBQSPI_IDLE;
613
                                        o_wb_ack <= spif_req;
614
                                        o_wb_stall <= 1'b0;
615
                                        end
616
                                2'b01: begin // Read configuration register
617
                                        state <= `WBQSPI_READ_CONFIG;
618
                                        spi_wr <= 1'b1;
619
                                        spi_len <= 2'b01;
620
                                        spi_in <= { 8'h35, 24'h00};
621
 
622
                                        o_wb_ack <= 1'b0;
623
                                        o_wb_stall <= 1'b1;
624
                                        end
625
                                2'b10: begin // Read status register
626
                                        state <= `WBQSPI_READ_STATUS;
627
                                        spi_wr <= 1'b1;
628
                                        spi_len <= 2'b01; // 8 bits out, 8 bits in
629
                                        spi_in <= { 8'h05, 24'h00};
630
 
631
                                        o_wb_ack <= 1'b0;
632
                                        o_wb_stall <= 1'b1;
633
                                        end
634
                                2'b11: begin // Read ID register
635
                                        state <= `WBQSPI_READ_ID_CMD;
636
                                        spi_wr <= 1'b1;
637
                                        spi_len <= 2'b00;
638
                                        spi_in <= { 8'h9f, 24'h00};
639
 
640
                                        o_wb_ack <= 1'b0;
641
                                        o_wb_stall <= 1'b1;
642
                                        end
643
                                endcase
644
                        end
645
                end
646 7 dgisselq
//
647
//
648
//      READ DATA section: for both data and commands
649
//
650 2 dgisselq
        end else if (state == `WBQSPI_RD_DUMMY)
651
        begin
652
                o_wb_ack   <= 1'b0;
653
                o_wb_stall <= 1'b1;
654
 
655
                spi_wr <= 1'b1; // Non-stop
656
                // Need to read one byte of dummy data,
657
                // just to consume 8 clocks
658
                spi_in <= { 8'h00, 24'h00 };
659
                spi_len <= 2'b00; // Read 8 bits
660
                spi_spd <= 1'b0;
661
                spi_hold <= 1'b0;
662
                spif_req<= (spif_req) && (i_wb_cyc);
663
 
664
                if ((~spi_busy)&&(~o_qspi_cs_n))
665
                        // Our command was accepted
666
                        state <= `WBQSPI_READ_CMD;
667
        end else if (state == `WBQSPI_QRD_ADDRESS)
668
        begin
669
                // We come in here immediately upon issuing a QRD read
670
                // command (8-bits), but we have to pause to give the
671
                // address (24-bits) and mode (8-bits) in quad speed.
672
                o_wb_ack   <= 1'b0;
673
                o_wb_stall <= 1'b1;
674
 
675
                spi_wr <= 1'b1; // Non-stop
676 14 dgisselq
                spi_in <= { w_spif_addr, 8'ha0 };
677 4 dgisselq
                spi_len <= 2'b10; // Write address, not mode byte
678 2 dgisselq
                spi_spd <= 1'b1;
679
                spi_dir <= 1'b0; // Still writing
680
                spi_hold <= 1'b0;
681
                spif_req<= (spif_req) && (i_wb_cyc);
682
 
683
                if ((~spi_busy)&&(spi_spd))
684
                        // Our command was accepted
685
                        state <= `WBQSPI_QRD_DUMMY;
686
        end else if (state == `WBQSPI_QRD_DUMMY)
687
        begin
688
                o_wb_ack   <= 1'b0;
689
                o_wb_stall <= 1'b1;
690
 
691
                spi_wr <= 1'b1; // Non-stop
692
                spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
693 9 dgisselq
                spi_len <= 2'b10; // Write 24 bits
694 2 dgisselq
                spi_spd <= 1'b1;
695
                spi_dir <= 1'b0; // Still writing
696
                spi_hold <= 1'b0;
697
                spif_req<= (spif_req) && (i_wb_cyc);
698
 
699
                if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
700
                        // Our command was accepted
701
                        state <= `WBQSPI_READ_CMD;
702
        end else if (state == `WBQSPI_READ_CMD)
703
        begin // Issue our first command to read 32 bits.
704
                o_wb_ack   <= 1'b0;
705
                o_wb_stall <= 1'b1;
706
 
707
                spi_wr <= 1'b1;
708
                spi_in <= { 8'hff, 24'h00 }; // Empty
709
                spi_len <= 2'b11; // Read 32 bits
710
                spi_dir <= 1'b1; // Now reading
711
                spi_hold <= 1'b0;
712
                spif_req<= (spif_req) && (i_wb_cyc);
713
                if ((spi_valid)&&(spi_len == 2'b11))
714
                        state <= `WBQSPI_READ_DATA;
715
        end else if (state == `WBQSPI_READ_DATA)
716
        begin
717
                // Pipelined read support
718 14 dgisselq
                spi_wr <=((i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
719 2 dgisselq
                spi_in <= 32'h00;
720
                spi_len <= 2'b11;
721
                // Don't adjust the speed here, it was set in the setup
722 4 dgisselq
                spi_dir <= 1'b1;        // Now we get to read
723
                // Don't let the device go to idle until the bus cycle ends.
724
                //      This actually prevents a *really* nasty race condition,
725
                //      where the strobe comes in after the lower level device
726
                //      has decided to stop waiting.  The write is then issued,
727
                //      but no one is listening.  By leaving the device open,
728
                //      the device is kept in a state where a valid strobe
729
                //      here will be useful.  Of course, we don't accept
730
                //      all commands, just reads.  Further, the strobe needs
731
                //      to be high for two clocks cycles without changing
732
                //      anything on the bus--one for us to notice it and pull
733
                //      our head out of the sand, and a second for whoever
734
                //      owns the bus to realize their command went through.
735
                spi_hold <= 1'b1;
736 2 dgisselq
                spif_req<= (spif_req) && (i_wb_cyc);
737
                if ((spi_valid)&&(~spi_in[31]))
738
                begin // Single pulse acknowledge and write data out
739
                        o_wb_ack <= spif_req;
740
                        o_wb_stall <= (~spi_wr);
741
                        // adjust endian-ness to match the PC
742 14 dgisselq
                        o_wb_data <= spi_out;
743 2 dgisselq
                        state <= (spi_wr)?`WBQSPI_READ_DATA
744
                                : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
745
                        spif_req <= spi_wr;
746 4 dgisselq
                        spi_hold <= (~spi_wr);
747 2 dgisselq
                        if (spi_wr)
748
                                spif_addr <= i_wb_addr;
749 4 dgisselq
                end else if (~i_wb_cyc)
750
                begin // FAIL SAFE: If the bus cycle ends, forget why we're
751
                        // here, just go back to idle
752
                        state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
753
                        spi_hold <= 1'b0;
754
                        o_wb_ack <= 1'b0;
755
                        o_wb_stall <= 1'b1;
756 2 dgisselq
                end else begin
757
                        o_wb_ack <= 1'b0;
758
                        o_wb_stall <= 1'b1;
759
                end
760
        end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
761
        begin // Wait 'til idle, but then go to fast read idle instead of full
762
                spi_wr     <= 1'b0;     // idle
763
                spi_hold   <= 1'b0;
764
                o_wb_stall <= 1'b1;
765
                o_wb_ack   <= 1'b0;
766
                spif_req   <= 1'b0;
767
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
768
                begin // clearing of the SPI port before moving on
769
                        state <= `WBQSPI_RDIDLE;
770
                        o_wb_stall <= 1'b0;
771
                        o_wb_ack   <= 1'b0;// Shouldn't be acking anything here
772
                end
773
        end else if (state == `WBQSPI_READ_ID_CMD)
774
        begin // We came into here immediately after issuing a 0x9f command
775
                // Now we need to read 32 bits of data.  Result should be
776
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
777
                // by the number of extended bytes available 8'h4d).
778
                o_wb_ack <= 1'b0;
779
                o_wb_stall<= 1'b1;
780
 
781
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
782
                spi_len <= 2'b11; // 32 bits of data are ... useful
783
                spi_in <= 32'h00; // Irrelevant
784
                spi_spd <= 1'b0; // Slow speed
785
                spi_dir <= 1'b1; // Reading
786
                spi_hold <= 1'b0;
787
                spif_req <= (spif_req) && (i_wb_cyc);
788
                if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
789
                        // Our command was accepted, now go read the result
790
                        state <= `WBQSPI_READ_ID;
791
        end else if (state == `WBQSPI_READ_ID)
792
        begin
793
                o_wb_ack <= 1'b0; // Assuming we're still waiting
794
                o_wb_stall <= 1'b1;
795
 
796 4 dgisselq
                spi_wr <= 1'b0; // No more writes, we've already written the cmd
797 2 dgisselq
                spi_hold <= 1'b0;
798
                spif_req <= (spif_req) && (i_wb_cyc);
799
 
800
                // Here, we just wait until the result comes back
801
                // The problem is, the result may be the previous result.
802
                // So we use spi_len as an indicator
803
                spi_len <= 2'b00;
804
                if((spi_valid)&&(spi_len==2'b00))
805
                begin // Put the results out as soon as possible
806
                        o_wb_data <= spi_out[31:0];
807
                        o_wb_ack <= spif_req;
808
                        spif_req <= 1'b0;
809 4 dgisselq
                end else if ((~spi_busy)&&(o_qspi_cs_n))
810 2 dgisselq
                begin
811
                        state <= `WBQSPI_IDLE;
812
                        o_wb_stall <= 1'b0;
813
                end
814
        end else if (state == `WBQSPI_READ_STATUS)
815
        begin // We enter after the command has been given, for now just
816
                // read and return
817
                spi_wr <= 1'b0;
818
                o_wb_ack <= 1'b0;
819
                spi_hold <= 1'b0;
820
                spif_req <= (spif_req) && (i_wb_cyc);
821
                if (spi_valid)
822
                begin
823
                        o_wb_ack <= spif_req;
824
                        o_wb_stall <= 1'b1;
825
                        spif_req <= 1'b0;
826
                        last_status <= spi_out[7:0];
827
                        write_in_progress <= spi_out[0];
828
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
829
                        begin // status, 'cause we're writing
830
                                o_wb_data <= { spi_out[0],
831
                                        dirty_sector, spi_busy,
832
                                        ~write_protect,
833
                                        quad_mode_enabled,
834 7 dgisselq
                                        {(29-ADDRESS_WIDTH){1'b0}},
835 2 dgisselq
                                        erased_sector, 14'h000 };
836
                        end else begin
837
                                o_wb_data <= { 24'h00, spi_out[7:0] };
838
                        end
839
                end
840
 
841
                if ((~spi_busy)&&(~spi_wr))
842
                        state <= `WBQSPI_IDLE;
843
        end else if (state == `WBQSPI_READ_CONFIG)
844
        begin // We enter after the command has been given, for now just
845
                // read and return
846
                spi_wr <= 1'b0;
847
                o_wb_ack <= 1'b0;
848
                o_wb_stall <= 1'b1;
849
                spi_hold <= 1'b0;
850
                spif_req <= (spif_req) && (i_wb_cyc);
851
 
852
                if (spi_valid)
853
                begin
854
                        o_wb_data <= { 24'h00, spi_out[7:0] };
855
                        quad_mode_enabled <= spi_out[1];
856
                end
857
 
858
                if ((~spi_busy)&&(~spi_wr))
859
                begin
860
                        state <= `WBQSPI_IDLE;
861
                        o_wb_ack   <= spif_req;
862
                        o_wb_stall <= 1'b0;
863
                        spif_req <= 1'b0;
864
                end
865 7 dgisselq
 
866
//
867
//
868
//      Write/erase data section
869
//
870
`ifndef READ_ONLY
871
        end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
872
        begin
873
                o_wb_stall <= 1'b1;
874
                o_wb_ack   <= 1'b0;
875
                spi_wr <= 1'b0;
876
                spif_req<= (spif_req) && (i_wb_cyc);
877
                if (~spi_busy)
878
                begin
879
                        spi_wr   <= 1'b1;
880
                        spi_in   <= { 8'h05, 24'h0000 };
881
                        spi_hold <= 1'b1;
882
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
883
                        state <= `WBQSPI_CHECK_WIP_CLEAR;
884
                        spi_spd  <= 1'b0; // Slow speed
885
                        spi_dir  <= 1'b0;
886
                end
887
        end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
888
        begin
889
                o_wb_stall <= 1'b1;
890
                o_wb_ack   <= 1'b0;
891
                // Repeat as often as necessary until we are clear
892
                spi_wr <= 1'b1;
893
                spi_in <= 32'h0000; // Values here are actually irrelevant
894
                spi_hold <= 1'b1;
895
                spi_len <= 2'b00; // One byte at a time
896
                spi_spd  <= 1'b0; // Slow speed
897
                spi_dir  <= 1'b0;
898
                spif_req<= (spif_req) && (i_wb_cyc);
899
                if ((spi_valid)&&(~spi_out[0]))
900
                begin
901
                        state <= `WBQSPI_CHECK_WIP_DONE;
902
                        spi_wr   <= 1'b0;
903
                        spi_hold <= 1'b0;
904
                        write_in_progress <= 1'b0;
905
                        last_status <= spi_out[7:0];
906
                end
907
        end else if (state == `WBQSPI_CHECK_WIP_DONE)
908
        begin
909
                o_wb_stall <= 1'b1;
910
                o_wb_ack   <= 1'b0;
911
                // Let's let the SPI port come back to a full idle,
912
                // and the chip select line go low before continuing
913
                spi_wr   <= 1'b0;
914
                spi_len  <= 2'b00;
915
                spi_hold <= 1'b0;
916
                spi_spd  <= 1'b0; // Slow speed
917
                spi_dir  <= 1'b0;
918
                spif_req<= (spif_req) && (i_wb_cyc);
919
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
920
                begin
921
                        spi_wr   <= 1'b0;
922
                        spi_hold <= 1'b0;
923
 
924
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
925
                        4'b00??: begin // Read data from ... somewhere
926
                                spi_wr     <= 1'b1;     // Write cmd to device
927
                                if (quad_mode_enabled)
928
                                begin
929 14 dgisselq
                                        spi_in <= { 8'heb, w_spif_addr };
930 7 dgisselq
                                        state <= `WBQSPI_QRD_ADDRESS;
931
                                        // spi_len    <= 2'b00; // single byte, cmd only
932
                                end else begin
933 14 dgisselq
                                        spi_in <= { 8'h0b, w_spif_addr };
934 7 dgisselq
                                        state <= `WBQSPI_RD_DUMMY;
935
                                        spi_len    <= 2'b11; // Send cmd and addr
936
                                end end
937
                        4'b10??: begin // Write data to ... anywhere
938
                                spi_wr <= 1'b1;
939
                                spi_len <= 2'b00; // 8 bits
940
                                // Send a write enable command
941
                                spi_in <= { 8'h06, 24'h00 };
942
                                state <= `WBQSPI_WEN;
943
                                end
944
                        4'b0110: begin // Read status register
945
                                state <= `WBQSPI_READ_STATUS;
946
                                spi_wr <= 1'b1;
947
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
948
                                spi_in <= { 8'h05, 24'h00};
949
                                end
950
                        4'b0111: begin
951
                                state <= `WBQSPI_READ_ID_CMD;
952
                                spi_wr <= 1'b1;
953
                                spi_len <= 2'b00;
954
                                spi_in <= { 8'h9f, 24'h00};
955
                                end
956
                        default: begin //
957
                                o_wb_stall <= 1'b1;
958
                                o_wb_ack <= spif_req;
959
                                state <= `WBQSPI_WAIT_TIL_IDLE;
960
                                end
961
                        endcase
962
                // spif_cmd   <= i_wb_we;
963
                // spif_addr  <= i_wb_addr;
964
                // spif_data  <= i_wb_data;
965
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
966
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
967
                end
968
        end else if (state == `WBQSPI_WEN)
969
        begin // We came here after issuing a write enable command
970
                spi_wr <= 1'b0;
971
                o_wb_ack <= 1'b0;
972
                o_wb_stall <= 1'b1;
973
                spif_req<= (spif_req) && (i_wb_cyc);
974
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
975
                        state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
976
                        // state <= `WBQSPI_PP;
977
        end else if (state == `WBQSPI_PP)
978
        begin // We come here under a full stop / full port idle mode
979
                // Issue our command immediately
980
                spi_wr <= 1'b1;
981 14 dgisselq
                spi_in <= { 8'h02, w_spif_addr };
982 7 dgisselq
                spi_len <= 2'b11;
983
                spi_hold <= 1'b1;
984
                spi_spd  <= 1'b0;
985
                spi_dir  <= 1'b0; // Writing
986
                spif_req<= (spif_req) && (i_wb_cyc);
987
 
988
                // Once we get busy, move on
989
                if (spi_busy)
990
                        state <= `WBQSPI_WR_DATA;
991
                if (spif_sector == erased_sector)
992
                        dirty_sector <= 1'b1;
993
        end else if (state == `WBQSPI_QPP)
994
        begin // We come here under a full stop / full port idle mode
995
                // Issue our command immediately
996
                spi_wr <= 1'b1;
997 14 dgisselq
                spi_in <= { 8'h32, w_spif_addr };
998 7 dgisselq
                spi_len <= 2'b11;
999
                spi_hold <= 1'b1;
1000
                spi_spd  <= 1'b0;
1001
                spi_dir  <= 1'b0; // Writing
1002
                spif_req<= (spif_req) && (i_wb_cyc);
1003
 
1004
                // Once we get busy, move on
1005
                if (spi_busy)
1006
                begin
1007
                        // spi_wr is irrelevant here ...
1008
                        // Set the speed value once, but wait til we get busy
1009
                        // to do so.
1010
                        spi_spd <= 1'b1;
1011
                        state <= `WBQSPI_WR_DATA;
1012
                end
1013
                if (spif_sector == erased_sector)
1014
                        dirty_sector <= 1'b1;
1015
        end else if (state == `WBQSPI_WR_DATA)
1016
        begin
1017
                o_wb_stall <= 1'b1;
1018
                o_wb_ack   <= 1'b0;
1019
                spi_wr   <= 1'b1; // write without waiting
1020 14 dgisselq
                spi_in   <= spif_data;
1021 7 dgisselq
                spi_len  <= 2'b11; // Write 4 bytes
1022
                spi_hold <= 1'b1;
1023
                if (~spi_busy)
1024
                begin
1025
                        o_wb_ack <= spif_req; // Ack when command given
1026
                        state <= `WBQSPI_WR_BUS_CYCLE;
1027
                end
1028
                spif_req<= (spif_req) && (i_wb_cyc);
1029
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
1030
        begin
1031
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
1032
                o_wb_stall <= 1'b1;
1033
                spi_wr <= 1'b0;
1034
                spi_hold <= 1'b1;
1035
                write_in_progress <= 1'b1;
1036
                spif_req<= (spif_req) && (i_wb_cyc);
1037
                if (~i_wb_cyc)
1038
                begin
1039
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1040
                        spi_hold <= 1'b0;
1041
                end else if (spi_wr)
1042
                begin // Give the SPI a chance to get busy on the last write
1043
                        // Do nothing here.
1044
                end else if ((i_wb_data_stb)&&(i_wb_we)
1045
                                &&(i_wb_addr == (spif_addr+1))
1046 16 dgisselq
                                &&(i_wb_addr[(AW-1):6]==spif_addr[(AW-1):6]))
1047 7 dgisselq
                begin
1048
                        spif_cmd  <= 1'b1;
1049
                        spif_data <= i_wb_data;
1050
                        spif_addr <= i_wb_addr;
1051
                        spif_ctrl  <= 1'b0;
1052
                        spif_req<= 1'b1;
1053
                        // We'll keep the bus stalled on this request
1054
                        // for a while
1055
                        state <= `WBQSPI_WR_DATA;
1056
                        o_wb_ack   <= 1'b0;
1057
                        o_wb_stall <= 1'b0;
1058
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
1059
                begin
1060
                        spi_hold <= 1'b0;
1061
                        spi_wr   <= 1'b0;
1062
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1063
                end // Otherwise we stay here
1064 2 dgisselq
        end else if (state == `WBQSPI_WRITE_CONFIG)
1065
        begin // We enter immediately after commanding a WEN
1066
                o_wb_ack   <= 1'b0;
1067
                o_wb_stall <= 1'b1;
1068
 
1069
                spi_len <= 2'b10;
1070
                spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
1071
                spi_wr <= 1'b0;
1072
                spi_hold <= 1'b0;
1073
                spif_req <= (spif_req) && (i_wb_cyc);
1074
                if ((~spi_busy)&&(~spi_wr))
1075
                begin
1076
                        spi_wr <= 1'b1;
1077
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1078
                        write_in_progress <= 1'b1;
1079
                        quad_mode_enabled <= spif_data[1];
1080
                end
1081
        end else if (state == `WBQSPI_WRITE_STATUS)
1082
        begin // We enter immediately after commanding a WEN
1083
                o_wb_ack   <= 1'b0;
1084
                o_wb_stall <= 1'b1;
1085
 
1086
                spi_len <= 2'b01;
1087
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
1088
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
1089
                spi_wr <= 1'b0;
1090
                spi_hold <= 1'b0;
1091
                spif_req <= (spif_req) && (i_wb_cyc);
1092
                if ((~spi_busy)&&(~spi_wr))
1093
                begin
1094
                        spi_wr <= 1'b1;
1095
                        last_status <= spif_data[7:0];
1096
                        write_in_progress <= 1'b1;
1097
                        if(((last_status[6])||(last_status[5]))
1098
                                &&((~spif_data[6])&&(~spif_data[5])))
1099
                                state <= `WBQSPI_CLEAR_STATUS;
1100
                        else
1101
                                state <= `WBQSPI_WAIT_TIL_IDLE;
1102
                end
1103
        end else if (state == `WBQSPI_ERASE_CMD)
1104
        begin // Know that WIP is clear on entry, WEN has just been commanded
1105
                spi_wr     <= 1'b0;
1106
                o_wb_ack   <= 1'b0;
1107
                o_wb_stall <= 1'b1;
1108
                spi_hold   <= 1'b0;
1109
                spi_spd <= 1'b0;
1110
                spi_dir <= 1'b0;
1111
                spif_req <= (spif_req) && (i_wb_cyc);
1112
 
1113
                // Here's the erase command
1114
                spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
1115
                spi_len <= 2'b11; // 32 bit write
1116
                // together with setting our copy of the WIP bit
1117
                write_in_progress <= 1'b1;
1118
                // keeping track of which sector we just erased
1119 16 dgisselq
                erased_sector <= spif_data[(AW-1):14];
1120 2 dgisselq
                // and marking this erase sector as no longer dirty
1121
                dirty_sector <= 1'b0;
1122
 
1123
                // Wait for a full stop before issuing this command
1124
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
1125
                begin // When our command is accepted, move to the next state
1126
                        spi_wr <= 1'b1;
1127
                        state <= `WBQSPI_ERASE_BLOCK;
1128
                end
1129
        end else if (state == `WBQSPI_ERASE_BLOCK)
1130
        begin
1131
                spi_wr     <= 1'b0;
1132
                spi_hold   <= 1'b0;
1133
                o_wb_stall <= 1'b1;
1134
                o_wb_ack   <= 1'b0;
1135
                spif_req <= (spif_req) && (i_wb_cyc);
1136
                // When the port clears, we can head back to idle
1137 16 dgisselq
                //      No ack necessary, we ackd before getting
1138
                //      here.
1139 2 dgisselq
                if ((~spi_busy)&&(~spi_wr))
1140
                        state <= `WBQSPI_IDLE;
1141
        end else if (state == `WBQSPI_CLEAR_STATUS)
1142
        begin // Issue a clear status command
1143
                spi_wr <= 1'b1;
1144
                spi_hold <= 1'b0;
1145
                spi_len <= 2'b00; // 8 bit command
1146
                spi_in <= { 8'h30, 24'h00 };
1147
                spi_spd <= 1'b0;
1148
                spi_dir <= 1'b0;
1149
                last_status[6:5] <= 2'b00;
1150
                spif_req <= (spif_req) && (i_wb_cyc);
1151
                if ((spi_wr)&&(~spi_busy))
1152
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1153
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
1154
        begin // We are now in read status register mode
1155
 
1156
                // No bus commands have (yet) been given
1157
                o_wb_stall <= 1'b1;
1158
                o_wb_ack   <= 1'b0;
1159
                spif_req <= (spif_req) && (i_wb_cyc);
1160
 
1161
                // Stay in this mode unless/until we get a command, or
1162
                //      the write is over
1163
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
1164
                                &&(write_in_progress));
1165
                spi_len <= 2'b00; // 8 bit reads
1166
                spi_spd <= 1'b0;  // SPI, not quad
1167
                spi_dir <= 1'b1;  // Read
1168
                if (spi_valid)
1169
                begin
1170
                        write_in_progress <= spi_out[0];
1171
                        if ((~spi_out[0])&&(write_in_progress))
1172
                                o_interrupt <= 1'b1;
1173
                end else
1174
                        o_interrupt <= 1'b0;
1175
 
1176
                if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
1177
                begin // We can now go to idle and process a command
1178
                        o_wb_stall <= 1'b0;
1179
                        o_wb_ack   <= 1'b0;
1180
                        state <= `WBQSPI_IDLE;
1181
                end
1182 7 dgisselq
`endif //       !READ_ONLY
1183 2 dgisselq
        end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
1184
        begin
1185
                spi_wr     <= 1'b0;
1186
                spi_hold   <= 1'b0;
1187
                o_wb_stall <= 1'b1;
1188
                o_wb_ack   <= 1'b0;
1189
                spif_req   <= 1'b0;
1190
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
1191
                begin // clearing of the SPI port before moving on
1192
                        state <= `WBQSPI_IDLE;
1193
                        o_wb_stall <= 1'b0;
1194
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
1195
                end
1196
        end
1197 4 dgisselq
        end
1198 2 dgisselq
 
1199 4 dgisselq
        // Command and control during the reset sequence
1200 16 dgisselq
        assign  o_qspi_cs_n = (spif_override)?alt_cmd :w_qspi_cs_n;
1201
        assign  o_qspi_sck  = (spif_override)?alt_ctrl:w_qspi_sck;
1202
        assign  o_qspi_mod  = (spif_override)?  2'b01 :w_qspi_mod;
1203
        assign  o_qspi_dat  = (spif_override)?  4'b00 :w_qspi_dat;
1204 2 dgisselq
endmodule

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