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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    wbspiflash.v
//
// Project:     Wishbone Controlled Quad SPI Flash Controller
//
// Purpose:     Access a Quad SPI flash via a WISHBONE interface.  This
//              includes both read and write (and erase) commands to the SPI
//              flash.  All read/write commands are accomplished using the
//              high speed (4-bit) interface.  Further, the device will be
//              left/kept in the 4-bit read interface mode between accesses,
//              for a minimum read latency.
//
//      Wishbone Registers (See spec sheet for more detail):
//      0: local config(r) / erase commands(w) / deep power down cmds / etc.
//      R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
//              { last_erased_sector, 14'h00 } if (WIP)
//              else { current_sector_being_erased, 14'h00 }
//              current if write in progress, last if written
//      W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
//      1: Configuration register
//      2: Status register (R/w)
//      3: Read ID (read only)
//      (19 bits): Data (R/w, but expect writes to take a while)
//              
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`include "flashconfig.v"
`default_nettype        none
//
`define WBQSPI_RESET            5'd0
`define WBQSPI_RESET_QUADMODE   5'd1
`define WBQSPI_IDLE             5'd2
`define WBQSPI_RDIDLE           5'd3    // Idle, but in fast read mode
`define WBQSPI_WBDECODE         5'd4
`define WBQSPI_RD_DUMMY         5'd5
`define WBQSPI_QRD_ADDRESS      5'd6
`define WBQSPI_QRD_DUMMY        5'd7
`define WBQSPI_READ_CMD         5'd8
`define WBQSPI_READ_DATA        5'd9
`define WBQSPI_WAIT_TIL_RDIDLE  5'd10
`define WBQSPI_READ_ID_CMD      5'd11
`define WBQSPI_READ_ID          5'd12
`define WBQSPI_READ_STATUS      5'd13
`define WBQSPI_READ_CONFIG      5'd14
`define WBQSPI_WAIT_TIL_IDLE    5'd15
//
//
`ifndef READ_ONLY
//
`define WBQSPI_WAIT_WIP_CLEAR   5'd16
`define WBQSPI_CHECK_WIP_CLEAR  5'd17
`define WBQSPI_CHECK_WIP_DONE   5'd18
`define WBQSPI_WEN              5'd19
`define WBQSPI_PP               5'd20   // Program page
`define WBQSPI_QPP              5'd21   // Program page, 4 bit mode
`define WBQSPI_WR_DATA          5'd22
`define WBQSPI_WR_BUS_CYCLE     5'd23
`define WBQSPI_WRITE_STATUS     5'd24
`define WBQSPI_WRITE_CONFIG     5'd25
`define WBQSPI_ERASE_WEN        5'd26
`define WBQSPI_ERASE_CMD        5'd27
`define WBQSPI_ERASE_BLOCK      5'd28
`define WBQSPI_CLEAR_STATUS     5'd29
`define WBQSPI_IDLE_CHECK_WIP   5'd30
//
`endif
 
module  wbqspiflash(i_clk,
                // Internal wishbone connections
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
                i_wb_addr, i_wb_data,
                // Wishbone return values
                o_wb_ack, o_wb_stall, o_wb_data,
                // Quad Spi connections to the external device
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
                o_interrupt);
        parameter       ADDRESS_WIDTH=22;
        localparam      AW = ADDRESS_WIDTH-2;
        input   wire            i_clk;
        // Wishbone, inputs first
        input   wire            i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
        input   wire    [(AW-1):0]       i_wb_addr;
        input   wire    [31:0]   i_wb_data;
        // then outputs
        output  reg             o_wb_ack;
        output  reg             o_wb_stall;
        output  reg     [31:0]   o_wb_data;
        // Quad SPI control wires
        output  wire            o_qspi_sck, o_qspi_cs_n;
        output  wire    [1:0]    o_qspi_mod;
        output  wire    [3:0]    o_qspi_dat;
        input   wire    [3:0]    i_qspi_dat;
        // Interrupt line
        output  reg             o_interrupt;
        // output       wire    [31:0]  o_debug;
 
        reg             spi_wr, spi_hold, spi_spd, spi_dir;
        reg     [31:0]   spi_in;
        reg     [1:0]    spi_len;
        wire    [31:0]   spi_out;
        wire            spi_valid, spi_busy;
        wire            w_qspi_sck, w_qspi_cs_n;
        wire    [3:0]    w_qspi_dat;
        wire    [1:0]    w_qspi_mod;
        // wire [22:0]  spi_dbg;
        llqspi  lldriver(i_clk,
                        spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
                                spi_out, spi_valid, spi_busy,
                        w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
                                i_qspi_dat);
 
        // Erase status tracking
        reg             write_in_progress, write_protect;
        reg     [(ADDRESS_WIDTH-17):0]   erased_sector;
        reg             dirty_sector;
        initial begin
                write_in_progress = 1'b0;
                erased_sector = 0;
                dirty_sector  = 1'b1;
                write_protect = 1'b1;
        end
 
        wire    [23:0]   w_wb_addr;
        generate
        if (ADDRESS_WIDTH>=24)
                assign w_wb_addr = { i_wb_addr[21:0], 2'b00 };
        else
                assign w_wb_addr = { {(24-ADDRESS_WIDTH){1'b0}}, i_wb_addr, 2'b00 };
        endgenerate
 
        // Repeat for spif_addr
        reg     [(ADDRESS_WIDTH-3):0]    spif_addr;
        wire    [23:0]   w_spif_addr;
        generate
        if (ADDRESS_WIDTH>=24)
                assign w_spif_addr = { spif_addr[21:0], 2'b00 };
        else
                assign w_spif_addr = { {(24-ADDRESS_WIDTH){1'b0}}, spif_addr, 2'b00 };
        endgenerate
 
        reg     [7:0]    last_status;
        reg     [9:0]    reset_counter;
        reg             quad_mode_enabled;
        reg             spif_cmd, spif_override;
        reg     [31:0]   spif_data;
        reg     [4:0]    state;
        reg             spif_ctrl, spif_req;
        reg             alt_cmd, alt_ctrl;
        wire    [(ADDRESS_WIDTH-17):0]   spif_sector;
        assign  spif_sector = spif_addr[(AW-1):14];
 
        // assign       o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
 
        initial state = `WBQSPI_RESET;
        initial o_wb_ack   = 1'b0;
        initial o_wb_stall = 1'b1;
        initial spi_wr     = 1'b0;
        initial spi_len    = 2'b00;
        initial quad_mode_enabled = 1'b0;
        initial o_interrupt = 1'b0;
        initial spif_override = 1'b1;
        initial spif_ctrl     = 1'b0;
        always @(posedge i_clk)
        begin
        spif_override <= 1'b0;
        alt_cmd  <= (reset_counter[9:8]==2'b10)?reset_counter[3]:1'b1; // Toggle CS_n
        alt_ctrl <= (reset_counter[9:8]==2'b10)?reset_counter[0]:1'b1; // Toggle clock too
        if (state == `WBQSPI_RESET)
        begin
                // From a reset, we should
                //      Enable the Quad I/O mode
                //      Disable the Write protection bits in the status register
                //      Chip should already be up and running, so we can start
                //      immediately ....
                o_wb_ack <= 1'b0;
                o_wb_stall <= 1'b1;
                spi_wr   <= 1'b0;
                spi_hold <= 1'b0;
                spi_spd  <= 1'b0;
                spi_dir  <= 1'b0;
                last_status <= 8'h00;
                state <= `WBQSPI_RESET_QUADMODE;
                spif_req <= 1'b0;
                spif_override <= 1'b1;
                last_status   <= 8'h00; //
                reset_counter <= 10'h3fc; //
                        // This guarantees that we aren't starting in quad
                        // I/O mode, where the FPGA configuration scripts may
                        // have left us.
        end else if (state == `WBQSPI_RESET_QUADMODE)
        begin
                // Okay, so here's the problem: we don't know whether or not
                // the Xilinx loader started us up in Quad Read I/O idle mode.
                // So, thus we need to toggle the clock and CS_n, with fewer
                // clocks than are necessary to transmit a word.
                //
                // Not ready to handle the bus yet, so stall any requests
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                // Do something ...
                if (reset_counter == 10'h00)
                begin
                        spif_override <= 1'b0;
                        state <= `WBQSPI_IDLE;
 
                        // Find out if we can use Quad I/O mode ...
                        state <= `WBQSPI_READ_CONFIG;
                        spi_wr <= 1'b1;
                        spi_len <= 2'b01;
                        spi_in <= { 8'h35, 24'h00};
 
                end else begin
                        reset_counter <= reset_counter - 10'h1;
                        spif_override <= 1'b1;
                end
        end else if (state == `WBQSPI_IDLE)
        begin
                o_interrupt <= 1'b0;
                o_wb_stall <= 1'b0;
                o_wb_ack <= 1'b0;
                spif_cmd   <= i_wb_we;
                spif_addr  <= i_wb_addr;
                spif_data  <= i_wb_data;
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
                spi_hold <= 1'b0;
                spi_spd  <= 1'b0;
                spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
                // Data register access
                if (i_wb_data_stb)
                begin
 
                        if (i_wb_we) // Request to write a page
                        begin
`ifdef  READ_ONLY
                                o_wb_ack <= 1'b1;
                                o_wb_stall <= 1'b0;
                        end else
`else
                                if((~write_protect)&&(~write_in_progress))
                                begin // 00
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b00; // 8 bits
                                        // Send a write enable command
                                        spi_in <= { 8'h06, 24'h00 };
                                        state <= `WBQSPI_WEN;
 
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                end else if (write_protect)
                                begin // whether or not write-in_progress ...
                                        // Do nothing on a write protect
                                        // violation
                                        //
                                        o_wb_ack <= 1'b1;
                                        o_wb_stall <= 1'b0;
                                end else begin // write is in progress, wait
                                        // for it to complete
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                end
                        end else if (~write_in_progress)
`endif
                        begin // Read access, normal mode(s)
                                o_wb_ack   <= 1'b0;
                                o_wb_stall <= 1'b1;
                                spi_wr     <= 1'b1;     // Write cmd to device
                                if (quad_mode_enabled)
                                begin
                                        spi_in <= { 8'heb, w_wb_addr };
                                        state <= `WBQSPI_QRD_ADDRESS;
                                        spi_len    <= 2'b00; // single byte, cmd only
                                end else begin
                                        spi_in <= { 8'h0b, w_wb_addr };
                                        state <= `WBQSPI_RD_DUMMY;
                                        spi_len    <= 2'b11; // cmd+addr,32bits
                                end
`ifndef READ_ONLY
                        end else begin
                                // A write is in progress ... need to stall
                                // the bus until the write is complete.
                                state <= `WBQSPI_WAIT_WIP_CLEAR;
                                o_wb_ack   <= 1'b0;
                                o_wb_stall <= 1'b1;
`endif
                        end
                end else if ((i_wb_ctrl_stb)&&(i_wb_we))
                begin
`ifdef  READ_ONLY
                        o_wb_ack   <= 1'b1;
                        o_wb_stall <= 1'b0;
`else
                        o_wb_stall <= 1'b1;
                        case(i_wb_addr[1:0])
                        2'b00: begin // Erase command register
                                write_protect <= !i_wb_data[28];
                                o_wb_stall <= 1'b0;
 
                                if((i_wb_data[31])&&(!write_in_progress))
                                begin
                                        // Command an erase--ack it immediately
 
                                        o_wb_ack <= 1'b1;
                                        o_wb_stall <= 1'b0;
 
                                        if ((i_wb_data[31])&&(~write_protect))
                                        begin
                                                spi_wr <= 1'b1;
                                                spi_len <= 2'b00;
                                                // Send a write enable command
                                                spi_in <= { 8'h06, 24'h00 };
                                                state <= `WBQSPI_ERASE_CMD;
                                                o_wb_stall <= 1'b1;
                                        end
                                end else if (i_wb_data[31])
                                begin
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
                                        o_wb_ack   <= 1'b1;
                                        o_wb_stall <= 1'b1;
                                end else
                                        o_wb_ack   <= 1'b1;
                                        o_wb_stall <= 1'b0;
                                end
                        2'b01: begin
                                // Write the configuration register
                                o_wb_ack <= 1'b1;
                                o_wb_stall <= 1'b1;
 
                                // Need to send a write enable command first
                                spi_wr <= 1'b1;
                                spi_len <= 2'b00; // 8 bits
                                // Send a write enable command
                                spi_in <= { 8'h06, 24'h00 };
                                state <= `WBQSPI_WRITE_CONFIG;
                                end
                        2'b10: begin
                                // Write the status register
                                o_wb_ack <= 1'b1; // Ack immediately
                                o_wb_stall <= 1'b1; // Stall other cmds
                                // Need to send a write enable command first
                                spi_wr <= 1'b1;
                                spi_len <= 2'b00; // 8 bits
                                // Send a write enable command
                                spi_in <= { 8'h06, 24'h00 };
                                state <= `WBQSPI_WRITE_STATUS;
                                end
                        2'b11: begin // Write the ID register??? makes no sense
                                o_wb_ack <= 1'b1;
                                o_wb_stall <= 1'b0;
                                end
                        endcase
`endif
                end else if (i_wb_ctrl_stb) // &&(!i_wb_we))
                begin
                        case(i_wb_addr[1:0])
                        2'b00: begin // Read local register
                                if (write_in_progress) // Read status
                                begin// register, is write still in progress?
                                        state <= `WBQSPI_READ_STATUS;
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b01;// 8 bits out, 8 bits in
                                        spi_in <= { 8'h05, 24'h00};
 
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                end else begin // Return w/o talking to device
                                        o_wb_ack <= 1'b1;
                                        o_wb_stall <= 1'b0;
                                        o_wb_data <= { write_in_progress,
                                                dirty_sector, spi_busy,
                                                ~write_protect,
                                                quad_mode_enabled,
                                                {(29-ADDRESS_WIDTH){1'b0}},
                                                erased_sector, 14'h000 };
                                end end
                        2'b01: begin // Read configuration register
                                state <= `WBQSPI_READ_CONFIG;
                                spi_wr <= 1'b1;
                                spi_len <= 2'b01;
                                spi_in <= { 8'h35, 24'h00};
 
                                o_wb_ack <= 1'b0;
                                o_wb_stall <= 1'b1;
                                end
                        2'b10: begin // Read status register
                                state <= `WBQSPI_READ_STATUS;
                                spi_wr <= 1'b1;
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
                                spi_in <= { 8'h05, 24'h00};
 
                                o_wb_ack <= 1'b0;
                                o_wb_stall <= 1'b1;
                                end
                        2'b11: begin // Read ID register
                                state <= `WBQSPI_READ_ID_CMD;
                                spi_wr <= 1'b1;
                                spi_len <= 2'b00;
                                spi_in <= { 8'h9f, 24'h00};
 
                                o_wb_ack <= 1'b0;
                                o_wb_stall <= 1'b1;
                                end
                        endcase
`ifndef READ_ONLY
                end else if ((~i_wb_cyc)&&(write_in_progress))
                begin
                        state <= `WBQSPI_IDLE_CHECK_WIP;
                        spi_wr <= 1'b1;
                        spi_len <= 2'b01; // 8 bits out, 8 bits in
                        spi_in <= { 8'h05, 24'h00};
 
                        o_wb_ack <= 1'b0;
                        o_wb_stall <= 1'b1;
`endif
                end
        end else if (state == `WBQSPI_RDIDLE)
        begin
                spi_wr <= 1'b0;
                o_wb_stall <= 1'b0;
                o_wb_ack <= 1'b0;
                spif_cmd   <= i_wb_we;
                spif_addr  <= i_wb_addr;
                spif_data  <= i_wb_data;
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
                spi_hold <= 1'b0;
                spi_spd<= 1'b1;
                spi_dir <= 1'b0; // Write (for now)
                if ((i_wb_data_stb)&&(!i_wb_we))
                begin // Continue our read ... send the new address / mode
                        o_wb_stall <= 1'b1;
                        spi_wr <= 1'b1;
                        spi_len <= 2'b10; // Write address, but not mode byte
                        spi_in <= { w_wb_addr, 8'ha0 };
                        state <= `WBQSPI_QRD_DUMMY;
                end else if((i_wb_ctrl_stb)&&(!i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
                begin
                        // A local read that doesn't touch the device, so leave
                        // the device in its current state
                        o_wb_stall <= 1'b0;
                        o_wb_ack <= 1'b1;
                        o_wb_data <= { write_in_progress,
                                        dirty_sector, spi_busy,
                                        ~write_protect,
                                        quad_mode_enabled,
                                        {(29-ADDRESS_WIDTH){1'b0}},
                                        erased_sector, 14'h000 };
                end else if(((i_wb_ctrl_stb)||(i_wb_data_stb)))
                begin // Need to release the device from quad mode for all else
                        o_wb_ack   <= 1'b0;
                        o_wb_stall <= 1'b1;
                        spi_wr <= 1'b1;
                        spi_len <= 2'b11;
                        spi_in <= 32'h00;
                        state <= `WBQSPI_WBDECODE;
                end
        end else if (state == `WBQSPI_WBDECODE)
        begin
                // We were in quad SPI read mode, and had to get out.
                // Now we've got a command (not data read) to read and
                // execute.  Accomplish what we would've done while in the
                // IDLE state here, save only that we don't have to worry
                // about data reads, and we need to operate on a stored
                // version of the bus command
                o_wb_stall <= 1'b1;
                o_wb_ack <= 1'b0;
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
                spi_hold <= 1'b0;
                spi_spd <= 1'b0;
                spi_dir <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
                begin
                        // Data register access
                        if (~spif_ctrl)
                        begin
                                if (spif_cmd) // Request to write a page
                                begin
`ifdef  READ_ONLY
                                        o_wb_ack <= spif_req;
                                        o_wb_stall <= 1'b0;
                                        state <= `WBQSPI_IDLE;
`else
                                        if((~write_protect)&&(~write_in_progress))
                                        begin // 00
                                                spi_wr <= 1'b1;
                                                spi_len <= 2'b00; // 8 bits
                                                // Send a write enable command
                                                spi_in <= { 8'h06, 24'h00 };
                                                state <= `WBQSPI_WEN;
 
                                                o_wb_ack <= 1'b0;
                                                o_wb_stall <= 1'b1;
                                        end else if (write_protect)
                                        begin // whether or not write-in_progress ...
                                                // Do nothing on a write protect
                                                // violation
                                                //
                                                o_wb_ack <= spif_req;
                                                o_wb_stall <= 1'b0;
                                                state <= `WBQSPI_IDLE;
                                        end else begin // write is in progress, wait
                                                // for it to complete
                                                state <= `WBQSPI_WAIT_WIP_CLEAR;
                                                o_wb_ack <= 1'b0;
                                                o_wb_stall <= 1'b1;
                                        end
                                // end else if (~write_in_progress) // always true
                                // but ... we wouldn't get here on a normal read access
`endif
                                end else begin
                                        // Something's wrong, we should never
                                        //   get here
                                        // Attempt to go to idle to recover
                                        state <= `WBQSPI_IDLE;
                                end
                        end else if ((spif_ctrl)&&(spif_cmd))
                        begin
`ifdef  READ_ONLY
                                o_wb_ack   <= spif_req;
                                o_wb_stall <= 1'b0;
                                state <= `WBQSPI_IDLE;
`else
                                o_wb_stall <= 1'b1;
                                case(spif_addr[1:0])
                                2'b00: begin // Erase command register
                                        o_wb_ack   <= spif_req;
                                        o_wb_stall <= 1'b0;
                                        state <= `WBQSPI_IDLE;
                                        write_protect <= ~spif_data[28];
                                        // Are we commanding an erase?
                                        // We're in read mode, writes cannot
                                        // be in progress, so ...
                                        if (spif_data[31]) // Command an erase
                                        begin
                                                // Since we're not going back
                                                // to IDLE, we must stall the
                                                // bus here
                                                o_wb_stall <= 1'b1;
                                                spi_wr <= 1'b1;
                                                spi_len <= 2'b00;
                                                // Send a write enable command
                                                spi_in <= { 8'h06, 24'h00 };
                                                state <= `WBQSPI_ERASE_CMD;
                                        end end
                                2'b01: begin
                                        // Write the configuration register
                                        o_wb_ack <= spif_req;
                                        o_wb_stall <= 1'b1;
 
                                        // Need to send a write enable command first
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b00; // 8 bits
                                        // Send a write enable command
                                        spi_in <= { 8'h06, 24'h00 };
                                        state <= `WBQSPI_WRITE_CONFIG;
                                        end
                                2'b10: begin
                                        // Write the status register
                                        o_wb_ack <= spif_req; // Ack immediately
                                        o_wb_stall <= 1'b1; // Stall other cmds
                                        // Need to send a write enable command first
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b00; // 8 bits
                                        // Send a write enable command
                                        spi_in <= { 8'h06, 24'h00 };
                                        state <= `WBQSPI_WRITE_STATUS;
                                        end
                                2'b11: begin // Write the ID register??? makes no sense
                                        o_wb_ack <= spif_req;
                                        o_wb_stall <= 1'b0;
                                        state <= `WBQSPI_IDLE;
                                        end
                                endcase
`endif
                        end else begin // on (~spif_we)
                                case(spif_addr[1:0])
                                2'b00: begin // Read local register
                                        // Nonsense case--would've done this
                                        // already
                                        state <= `WBQSPI_IDLE;
                                        o_wb_ack <= spif_req;
                                        o_wb_stall <= 1'b0;
                                        end
                                2'b01: begin // Read configuration register
                                        state <= `WBQSPI_READ_CONFIG;
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b01;
                                        spi_in <= { 8'h35, 24'h00};
 
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                        end
                                2'b10: begin // Read status register
                                        state <= `WBQSPI_READ_STATUS;
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b01; // 8 bits out, 8 bits in
                                        spi_in <= { 8'h05, 24'h00};
 
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                        end
                                2'b11: begin // Read ID register
                                        state <= `WBQSPI_READ_ID_CMD;
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b00;
                                        spi_in <= { 8'h9f, 24'h00};
 
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                        end
                                endcase
                        end
                end
//
//
//      READ DATA section: for both data and commands
//
        end else if (state == `WBQSPI_RD_DUMMY)
        begin
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_wr <= 1'b1; // Non-stop
                // Need to read one byte of dummy data,
                // just to consume 8 clocks
                spi_in <= { 8'h00, 24'h00 };
                spi_len <= 2'b00; // Read 8 bits
                spi_spd <= 1'b0;
                spi_hold <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
 
                if ((~spi_busy)&&(~o_qspi_cs_n))
                        // Our command was accepted
                        state <= `WBQSPI_READ_CMD;
        end else if (state == `WBQSPI_QRD_ADDRESS)
        begin
                // We come in here immediately upon issuing a QRD read
                // command (8-bits), but we have to pause to give the
                // address (24-bits) and mode (8-bits) in quad speed.
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_wr <= 1'b1; // Non-stop
                spi_in <= { w_spif_addr, 8'ha0 };
                spi_len <= 2'b10; // Write address, not mode byte
                spi_spd <= 1'b1;
                spi_dir <= 1'b0; // Still writing
                spi_hold <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
 
                if ((~spi_busy)&&(spi_spd))
                        // Our command was accepted
                        state <= `WBQSPI_QRD_DUMMY;
        end else if (state == `WBQSPI_QRD_DUMMY)
        begin
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_wr <= 1'b1; // Non-stop
                spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
                spi_len <= 2'b10; // Write 24 bits
                spi_spd <= 1'b1;
                spi_dir <= 1'b0; // Still writing
                spi_hold <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
 
                if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
                        // Our command was accepted
                        state <= `WBQSPI_READ_CMD;
        end else if (state == `WBQSPI_READ_CMD)
        begin // Issue our first command to read 32 bits.
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_wr <= 1'b1;
                spi_in <= { 8'hff, 24'h00 }; // Empty
                spi_len <= 2'b11; // Read 32 bits
                spi_dir <= 1'b1; // Now reading
                spi_hold <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((spi_valid)&&(spi_len == 2'b11))
                        state <= `WBQSPI_READ_DATA;
        end else if (state == `WBQSPI_READ_DATA)
        begin
                // Pipelined read support
                spi_wr <=((i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
                spi_in <= 32'h00;
                spi_len <= 2'b11;
                // Don't adjust the speed here, it was set in the setup
                spi_dir <= 1'b1;        // Now we get to read
                // Don't let the device go to idle until the bus cycle ends.
                //      This actually prevents a *really* nasty race condition,
                //      where the strobe comes in after the lower level device
                //      has decided to stop waiting.  The write is then issued,
                //      but no one is listening.  By leaving the device open,
                //      the device is kept in a state where a valid strobe
                //      here will be useful.  Of course, we don't accept
                //      all commands, just reads.  Further, the strobe needs
                //      to be high for two clocks cycles without changing
                //      anything on the bus--one for us to notice it and pull
                //      our head out of the sand, and a second for whoever
                //      owns the bus to realize their command went through.
                spi_hold <= 1'b1;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((spi_valid)&&(~spi_in[31]))
                begin // Single pulse acknowledge and write data out
                        o_wb_ack <= spif_req;
                        o_wb_stall <= (~spi_wr);
                        // adjust endian-ness to match the PC
                        o_wb_data <= spi_out;
                        state <= (spi_wr)?`WBQSPI_READ_DATA
                                : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
                        spif_req <= spi_wr;
                        spi_hold <= (~spi_wr);
                        if (spi_wr)
                                spif_addr <= i_wb_addr;
                end else if (~i_wb_cyc)
                begin // FAIL SAFE: If the bus cycle ends, forget why we're
                        // here, just go back to idle
                        state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
                        spi_hold <= 1'b0;
                        o_wb_ack <= 1'b0;
                        o_wb_stall <= 1'b1;
                end else begin
                        o_wb_ack <= 1'b0;
                        o_wb_stall <= 1'b1;
                end
        end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
        begin // Wait 'til idle, but then go to fast read idle instead of full
                spi_wr     <= 1'b0;     // idle
                spi_hold   <= 1'b0;
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spif_req   <= 1'b0;
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
                begin // clearing of the SPI port before moving on
                        state <= `WBQSPI_RDIDLE;
                        o_wb_stall <= 1'b0;
                        o_wb_ack   <= 1'b0;// Shouldn't be acking anything here
                end
        end else if (state == `WBQSPI_READ_ID_CMD)
        begin // We came into here immediately after issuing a 0x9f command
                // Now we need to read 32 bits of data.  Result should be
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
                // by the number of extended bytes available 8'h4d).
                o_wb_ack <= 1'b0;
                o_wb_stall<= 1'b1;
 
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
                spi_len <= 2'b11; // 32 bits of data are ... useful
                spi_in <= 32'h00; // Irrelevant
                spi_spd <= 1'b0; // Slow speed
                spi_dir <= 1'b1; // Reading
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
                if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
                        // Our command was accepted, now go read the result
                        state <= `WBQSPI_READ_ID;
        end else if (state == `WBQSPI_READ_ID)
        begin
                o_wb_ack <= 1'b0; // Assuming we're still waiting
                o_wb_stall <= 1'b1;
 
                spi_wr <= 1'b0; // No more writes, we've already written the cmd
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
 
                // Here, we just wait until the result comes back
                // The problem is, the result may be the previous result.
                // So we use spi_len as an indicator
                spi_len <= 2'b00;
                if((spi_valid)&&(spi_len==2'b00))
                begin // Put the results out as soon as possible
                        o_wb_data <= spi_out[31:0];
                        o_wb_ack <= spif_req;
                        spif_req <= 1'b0;
                end else if ((~spi_busy)&&(o_qspi_cs_n))
                begin
                        state <= `WBQSPI_IDLE;
                        o_wb_stall <= 1'b0;
                end
        end else if (state == `WBQSPI_READ_STATUS)
        begin // We enter after the command has been given, for now just
                // read and return
                spi_wr <= 1'b0;
                o_wb_ack <= 1'b0;
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
                if (spi_valid)
                begin
                        o_wb_ack <= spif_req;
                        o_wb_stall <= 1'b1;
                        spif_req <= 1'b0;
                        last_status <= spi_out[7:0];
                        write_in_progress <= spi_out[0];
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
                        begin // status, 'cause we're writing
                                o_wb_data <= { spi_out[0],
                                        dirty_sector, spi_busy,
                                        ~write_protect,
                                        quad_mode_enabled,
                                        {(29-ADDRESS_WIDTH){1'b0}},
                                        erased_sector, 14'h000 };
                        end else begin
                                o_wb_data <= { 24'h00, spi_out[7:0] };
                        end
                end
 
                if ((~spi_busy)&&(~spi_wr))
                        state <= `WBQSPI_IDLE;
        end else if (state == `WBQSPI_READ_CONFIG)
        begin // We enter after the command has been given, for now just
                // read and return
                spi_wr <= 1'b0;
                o_wb_ack <= 1'b0;
                o_wb_stall <= 1'b1;
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
 
                if (spi_valid)
                begin
                        o_wb_data <= { 24'h00, spi_out[7:0] };
                        quad_mode_enabled <= spi_out[1];
                end
 
                if ((~spi_busy)&&(~spi_wr))
                begin
                        state <= `WBQSPI_IDLE;
                        o_wb_ack   <= spif_req;
                        o_wb_stall <= 1'b0;
                        spif_req <= 1'b0;
                end
 
//
//
//      Write/erase data section
//
`ifndef READ_ONLY
        end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
        begin
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spi_wr <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
                if (~spi_busy)
                begin
                        spi_wr   <= 1'b1;
                        spi_in   <= { 8'h05, 24'h0000 };
                        spi_hold <= 1'b1;
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
                        state <= `WBQSPI_CHECK_WIP_CLEAR;
                        spi_spd  <= 1'b0; // Slow speed
                        spi_dir  <= 1'b0;
                end
        end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
        begin
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                // Repeat as often as necessary until we are clear
                spi_wr <= 1'b1;
                spi_in <= 32'h0000; // Values here are actually irrelevant
                spi_hold <= 1'b1;
                spi_len <= 2'b00; // One byte at a time
                spi_spd  <= 1'b0; // Slow speed
                spi_dir  <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((spi_valid)&&(~spi_out[0]))
                begin
                        state <= `WBQSPI_CHECK_WIP_DONE;
                        spi_wr   <= 1'b0;
                        spi_hold <= 1'b0;
                        write_in_progress <= 1'b0;
                        last_status <= spi_out[7:0];
                end
        end else if (state == `WBQSPI_CHECK_WIP_DONE)
        begin
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                // Let's let the SPI port come back to a full idle,
                // and the chip select line go low before continuing
                spi_wr   <= 1'b0;
                spi_len  <= 2'b00;
                spi_hold <= 1'b0;
                spi_spd  <= 1'b0; // Slow speed
                spi_dir  <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
                begin
                        spi_wr   <= 1'b0;
                        spi_hold <= 1'b0;
 
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
                        4'b00??: begin // Read data from ... somewhere
                                spi_wr     <= 1'b1;     // Write cmd to device
                                if (quad_mode_enabled)
                                begin
                                        spi_in <= { 8'heb, w_spif_addr };
                                        state <= `WBQSPI_QRD_ADDRESS;
                                        // spi_len    <= 2'b00; // single byte, cmd only
                                end else begin
                                        spi_in <= { 8'h0b, w_spif_addr };
                                        state <= `WBQSPI_RD_DUMMY;
                                        spi_len    <= 2'b11; // Send cmd and addr
                                end end
                        4'b10??: begin // Write data to ... anywhere
                                spi_wr <= 1'b1;
                                spi_len <= 2'b00; // 8 bits
                                // Send a write enable command
                                spi_in <= { 8'h06, 24'h00 };
                                state <= `WBQSPI_WEN;
                                end
                        4'b0110: begin // Read status register
                                state <= `WBQSPI_READ_STATUS;
                                spi_wr <= 1'b1;
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
                                spi_in <= { 8'h05, 24'h00};
                                end
                        4'b0111: begin
                                state <= `WBQSPI_READ_ID_CMD;
                                spi_wr <= 1'b1;
                                spi_len <= 2'b00;
                                spi_in <= { 8'h9f, 24'h00};
                                end
                        default: begin //
                                o_wb_stall <= 1'b1;
                                o_wb_ack <= spif_req;
                                state <= `WBQSPI_WAIT_TIL_IDLE;
                                end
                        endcase
                // spif_cmd   <= i_wb_we;
                // spif_addr  <= i_wb_addr;
                // spif_data  <= i_wb_data;
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
                end
        end else if (state == `WBQSPI_WEN)
        begin // We came here after issuing a write enable command
                spi_wr <= 1'b0;
                o_wb_ack <= 1'b0;
                o_wb_stall <= 1'b1;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
                        state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
                        // state <= `WBQSPI_PP;
        end else if (state == `WBQSPI_PP)
        begin // We come here under a full stop / full port idle mode
                // Issue our command immediately
                spi_wr <= 1'b1;
                spi_in <= { 8'h02, w_spif_addr };
                spi_len <= 2'b11;
                spi_hold <= 1'b1;
                spi_spd  <= 1'b0;
                spi_dir  <= 1'b0; // Writing
                spif_req<= (spif_req) && (i_wb_cyc);
 
                // Once we get busy, move on
                if (spi_busy)
                        state <= `WBQSPI_WR_DATA;
                if (spif_sector == erased_sector)
                        dirty_sector <= 1'b1;
        end else if (state == `WBQSPI_QPP)
        begin // We come here under a full stop / full port idle mode
                // Issue our command immediately
                spi_wr <= 1'b1;
                spi_in <= { 8'h32, w_spif_addr };
                spi_len <= 2'b11;
                spi_hold <= 1'b1;
                spi_spd  <= 1'b0;
                spi_dir  <= 1'b0; // Writing
                spif_req<= (spif_req) && (i_wb_cyc);
 
                // Once we get busy, move on
                if (spi_busy)
                begin
                        // spi_wr is irrelevant here ...
                        // Set the speed value once, but wait til we get busy
                        // to do so.
                        spi_spd <= 1'b1;
                        state <= `WBQSPI_WR_DATA;
                end
                if (spif_sector == erased_sector)
                        dirty_sector <= 1'b1;
        end else if (state == `WBQSPI_WR_DATA)
        begin
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spi_wr   <= 1'b1; // write without waiting
                spi_in   <= spif_data;
                spi_len  <= 2'b11; // Write 4 bytes
                spi_hold <= 1'b1;
                if (~spi_busy)
                begin
                        o_wb_ack <= spif_req; // Ack when command given
                        state <= `WBQSPI_WR_BUS_CYCLE;
                end
                spif_req<= (spif_req) && (i_wb_cyc);
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
        begin
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
                o_wb_stall <= 1'b1;
                spi_wr <= 1'b0;
                spi_hold <= 1'b1;
                write_in_progress <= 1'b1;
                spif_req<= (spif_req) && (i_wb_cyc);
                if (~i_wb_cyc)
                begin
                        state <= `WBQSPI_WAIT_TIL_IDLE;
                        spi_hold <= 1'b0;
                end else if (spi_wr)
                begin // Give the SPI a chance to get busy on the last write
                        // Do nothing here.
                end else if ((i_wb_data_stb)&&(i_wb_we)
                                &&(i_wb_addr == (spif_addr+1))
                                &&(i_wb_addr[(AW-1):6]==spif_addr[(AW-1):6]))
                begin
                        spif_cmd  <= 1'b1;
                        spif_data <= i_wb_data;
                        spif_addr <= i_wb_addr;
                        spif_ctrl  <= 1'b0;
                        spif_req<= 1'b1;
                        // We'll keep the bus stalled on this request
                        // for a while
                        state <= `WBQSPI_WR_DATA;
                        o_wb_ack   <= 1'b0;
                        o_wb_stall <= 1'b0;
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
                begin
                        spi_hold <= 1'b0;
                        spi_wr   <= 1'b0;
                        state <= `WBQSPI_WAIT_TIL_IDLE;
                end // Otherwise we stay here
        end else if (state == `WBQSPI_WRITE_CONFIG)
        begin // We enter immediately after commanding a WEN
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_len <= 2'b10;
                spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
                spi_wr <= 1'b0;
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
                if ((~spi_busy)&&(~spi_wr))
                begin
                        spi_wr <= 1'b1;
                        state <= `WBQSPI_WAIT_TIL_IDLE;
                        write_in_progress <= 1'b1;
                        quad_mode_enabled <= spif_data[1];
                end
        end else if (state == `WBQSPI_WRITE_STATUS)
        begin // We enter immediately after commanding a WEN
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_len <= 2'b01;
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
                spi_wr <= 1'b0;
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
                if ((~spi_busy)&&(~spi_wr))
                begin
                        spi_wr <= 1'b1;
                        last_status <= spif_data[7:0];
                        write_in_progress <= 1'b1;
                        if(((last_status[6])||(last_status[5]))
                                &&((~spif_data[6])&&(~spif_data[5])))
                                state <= `WBQSPI_CLEAR_STATUS;
                        else
                                state <= `WBQSPI_WAIT_TIL_IDLE;
                end
        end else if (state == `WBQSPI_ERASE_CMD)
        begin // Know that WIP is clear on entry, WEN has just been commanded
                spi_wr     <= 1'b0;
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
                spi_hold   <= 1'b0;
                spi_spd <= 1'b0;
                spi_dir <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
 
                // Here's the erase command
                spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
                spi_len <= 2'b11; // 32 bit write
                // together with setting our copy of the WIP bit
                write_in_progress <= 1'b1;
                // keeping track of which sector we just erased
                erased_sector <= spif_data[(AW-1):14];
                // and marking this erase sector as no longer dirty
                dirty_sector <= 1'b0;
 
                // Wait for a full stop before issuing this command
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
                begin // When our command is accepted, move to the next state
                        spi_wr <= 1'b1;
                        state <= `WBQSPI_ERASE_BLOCK;
                end
        end else if (state == `WBQSPI_ERASE_BLOCK)
        begin
                spi_wr     <= 1'b0;
                spi_hold   <= 1'b0;
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
                // When the port clears, we can head back to idle
                //      No ack necessary, we ackd before getting
                //      here.
                if ((~spi_busy)&&(~spi_wr))
                        state <= `WBQSPI_IDLE;
        end else if (state == `WBQSPI_CLEAR_STATUS)
        begin // Issue a clear status command
                spi_wr <= 1'b1;
                spi_hold <= 1'b0;
                spi_len <= 2'b00; // 8 bit command
                spi_in <= { 8'h30, 24'h00 };
                spi_spd <= 1'b0;
                spi_dir <= 1'b0;
                last_status[6:5] <= 2'b00;
                spif_req <= (spif_req) && (i_wb_cyc);
                if ((spi_wr)&&(~spi_busy))
                        state <= `WBQSPI_WAIT_TIL_IDLE;
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
        begin // We are now in read status register mode
 
                // No bus commands have (yet) been given
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
 
                // Stay in this mode unless/until we get a command, or
                //      the write is over
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
                                &&(write_in_progress));
                spi_len <= 2'b00; // 8 bit reads
                spi_spd <= 1'b0;  // SPI, not quad
                spi_dir <= 1'b1;  // Read
                if (spi_valid)
                begin
                        write_in_progress <= spi_out[0];
                        if ((~spi_out[0])&&(write_in_progress))
                                o_interrupt <= 1'b1;
                end else
                        o_interrupt <= 1'b0;
 
                if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
                begin // We can now go to idle and process a command
                        o_wb_stall <= 1'b0;
                        o_wb_ack   <= 1'b0;
                        state <= `WBQSPI_IDLE;
                end
`endif //       !READ_ONLY
        end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
        begin
                spi_wr     <= 1'b0;
                spi_hold   <= 1'b0;
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spif_req   <= 1'b0;
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
                begin // clearing of the SPI port before moving on
                        state <= `WBQSPI_IDLE;
                        o_wb_stall <= 1'b0;
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
                end
        end
        end
 
        // Command and control during the reset sequence
        assign  o_qspi_cs_n = (spif_override)?alt_cmd :w_qspi_cs_n;
        assign  o_qspi_sck  = (spif_override)?alt_ctrl:w_qspi_sck;
        assign  o_qspi_mod  = (spif_override)?  2'b01 :w_qspi_mod;
        assign  o_qspi_dat  = (spif_override)?  4'b00 :w_qspi_dat;
endmodule

Line No.	Rev	Author	Line
1	14	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2	2	dgisselq	`//`
3			`// Filename: wbspiflash.v`
4			`//`
5	3	dgisselq	`// Project: Wishbone Controlled Quad SPI Flash Controller`
6	2	dgisselq	`//`
7			`// Purpose: Access a Quad SPI flash via a WISHBONE interface. This`
8			`// includes both read and write (and erase) commands to the SPI`
9			`// flash. All read/write commands are accomplished using the`
10			`// high speed (4-bit) interface. Further, the device will be`
11			`// left/kept in the 4-bit read interface mode between accesses,`
12			`// for a minimum read latency.`
13			`//`
14	3	dgisselq	`// Wishbone Registers (See spec sheet for more detail):`
15	2	dgisselq	`// 0: local config(r) / erase commands(w) / deep power down cmds / etc.`
16			`// R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,`
17			`// { last_erased_sector, 14'h00 } if (WIP)`
18			`// else { current_sector_being_erased, 14'h00 }`
19			`// current if write in progress, last if written`
20			`// W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)`
21	3	dgisselq	`// 1: Configuration register`
22			`// 2: Status register (R/w)`
23			`// 3: Read ID (read only)`
24	2	dgisselq	`// (19 bits): Data (R/w, but expect writes to take a while)`
25			`//`
26			`//`
27	14	dgisselq	`// Creator: Dan Gisselquist, Ph.D.`
28	8	dgisselq	`// Gisselquist Technology, LLC`
29	2	dgisselq	`//`
30	14	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
31	2	dgisselq	`//`
32	20	dgisselq	`// Copyright (C) 2015-2017, Gisselquist Technology, LLC`
33	2	dgisselq	`//`
34	3	dgisselq	`// This program is free software (firmware): you can redistribute it and/or`
35			`// modify it under the terms of the GNU General Public License as published`
36			`// by the Free Software Foundation, either version 3 of the License, or (at`
37			`// your option) any later version.`
38			`//`
39			`// This program is distributed in the hope that it will be useful, but WITHOUT`
40			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
41			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
42			`// for more details.`
43			`//`
44			`// You should have received a copy of the GNU General Public License along`
45	14	dgisselq	`// with this program. (It's in the $(ROOT)/doc directory. Run make with no`
46	3	dgisselq	`// target there if the PDF file isn't present.) If not, see`
47			`// <http://www.gnu.org/licenses/> for a copy.`
48			`//`
49			`// License: GPL, v3, as defined and found on www.gnu.org,`
50			`// http://www.gnu.org/licenses/gpl.html`
51			`//`
52			`//`
53	14	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
54	7	dgisselq	`//`
55	20	dgisselq	`//`
56			`include "flashconfig.v"
57	14	dgisselq	`default_nettype none
58	7	dgisselq	`//`
59	16	dgisselq	`define WBQSPI_RESET 5'd0
60			`define WBQSPI_RESET_QUADMODE 5'd1
61			`define WBQSPI_IDLE 5'd2
62			`define WBQSPI_RDIDLE 5'd3 // Idle, but in fast read mode
63			`define WBQSPI_WBDECODE 5'd4
64			`define WBQSPI_RD_DUMMY 5'd5
65			`define WBQSPI_QRD_ADDRESS 5'd6
66			`define WBQSPI_QRD_DUMMY 5'd7
67			`define WBQSPI_READ_CMD 5'd8
68			`define WBQSPI_READ_DATA 5'd9
69			`define WBQSPI_WAIT_TIL_RDIDLE 5'd10
70			`define WBQSPI_READ_ID_CMD 5'd11
71			`define WBQSPI_READ_ID 5'd12
72			`define WBQSPI_READ_STATUS 5'd13
73			`define WBQSPI_READ_CONFIG 5'd14
74			`define WBQSPI_WAIT_TIL_IDLE 5'd15
75	7	dgisselq	`//`
76			`//`
77			`ifndef READ_ONLY
78			`//`
79	16	dgisselq	`define WBQSPI_WAIT_WIP_CLEAR 5'd16
80			`define WBQSPI_CHECK_WIP_CLEAR 5'd17
81			`define WBQSPI_CHECK_WIP_DONE 5'd18
82			`define WBQSPI_WEN 5'd19
83			`define WBQSPI_PP 5'd20 // Program page
84			`define WBQSPI_QPP 5'd21 // Program page, 4 bit mode
85			`define WBQSPI_WR_DATA 5'd22
86			`define WBQSPI_WR_BUS_CYCLE 5'd23
87			`define WBQSPI_WRITE_STATUS 5'd24
88			`define WBQSPI_WRITE_CONFIG 5'd25
89			`define WBQSPI_ERASE_WEN 5'd26
90			`define WBQSPI_ERASE_CMD 5'd27
91			`define WBQSPI_ERASE_BLOCK 5'd28
92			`define WBQSPI_CLEAR_STATUS 5'd29
93			`define WBQSPI_IDLE_CHECK_WIP 5'd30
94	7	dgisselq	`//`
95			`endif
96	2	dgisselq
97	16	dgisselq	`module wbqspiflash(i_clk,`
98	2	dgisselq	`// Internal wishbone connections`
99			`i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,`
100			`i_wb_addr, i_wb_data,`
101			`// Wishbone return values`
102			`o_wb_ack, o_wb_stall, o_wb_data,`
103			`// Quad Spi connections to the external device`
104			`o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,`
105	3	dgisselq	`o_interrupt);`
106	7	dgisselq	`parameter ADDRESS_WIDTH=22;`
107	16	dgisselq	`localparam AW = ADDRESS_WIDTH-2;`
108			`input wire i_clk;`
109	2	dgisselq	`// Wishbone, inputs first`
110	14	dgisselq	`input wire i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;`
111	16	dgisselq	`input wire [(AW-1):0] i_wb_addr;`
112	14	dgisselq	`input wire [31:0] i_wb_data;`
113	2	dgisselq	`// then outputs`
114			`output reg o_wb_ack;`
115			`output reg o_wb_stall;`
116			`output reg [31:0] o_wb_data;`
117			`// Quad SPI control wires`
118			`output wire o_qspi_sck, o_qspi_cs_n;`
119			`output wire [1:0] o_qspi_mod;`
120			`output wire [3:0] o_qspi_dat;`
121	14	dgisselq	`input wire [3:0] i_qspi_dat;`
122	2	dgisselq	`// Interrupt line`
123			`output reg o_interrupt;`
124	7	dgisselq	`// output wire [31:0] o_debug;`
125	2	dgisselq
126			`reg spi_wr, spi_hold, spi_spd, spi_dir;`
127			`reg [31:0] spi_in;`
128			`reg [1:0] spi_len;`
129			`wire [31:0] spi_out;`
130			`wire spi_valid, spi_busy;`
131	4	dgisselq	`wire w_qspi_sck, w_qspi_cs_n;`
132			`wire [3:0] w_qspi_dat;`
133			`wire [1:0] w_qspi_mod;`
134	7	dgisselq	`// wire [22:0] spi_dbg;`
135	16	dgisselq	`llqspi lldriver(i_clk,`
136	2	dgisselq	`spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,`
137			`spi_out, spi_valid, spi_busy,`
138	4	dgisselq	`w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,`
139	3	dgisselq	`i_qspi_dat);`
140	2	dgisselq
141			`// Erase status tracking`
142			`reg write_in_progress, write_protect;`
143	7	dgisselq	`reg [(ADDRESS_WIDTH-17):0] erased_sector;`
144	2	dgisselq	`reg dirty_sector;`
145			`initial begin`
146			`write_in_progress = 1'b0;`
147	7	dgisselq	`erased_sector = 0;`
148	2	dgisselq	`dirty_sector = 1'b1;`
149			`write_protect = 1'b1;`
150			`end`
151
152	14	dgisselq	`wire [23:0] w_wb_addr;`
153			`generate`
154			`if (ADDRESS_WIDTH>=24)`
155			`assign w_wb_addr = { i_wb_addr[21:0], 2'b00 };`
156			`else`
157			`assign w_wb_addr = { {(24-ADDRESS_WIDTH){1'b0}}, i_wb_addr, 2'b00 };`
158			`endgenerate`
159
160			`// Repeat for spif_addr`
161			`reg [(ADDRESS_WIDTH-3):0] spif_addr;`
162			`wire [23:0] w_spif_addr;`
163			`generate`
164			`if (ADDRESS_WIDTH>=24)`
165			`assign w_spif_addr = { spif_addr[21:0], 2'b00 };`
166			`else`
167			`assign w_spif_addr = { {(24-ADDRESS_WIDTH){1'b0}}, spif_addr, 2'b00 };`
168			`endgenerate`
169
170	2	dgisselq	`reg [7:0] last_status;`
171	16	dgisselq	`reg [9:0] reset_counter;`
172	2	dgisselq	`reg quad_mode_enabled;`
173	4	dgisselq	`reg spif_cmd, spif_override;`
174	2	dgisselq	`reg [31:0] spif_data;`
175	14	dgisselq	`reg [4:0] state;`
176	2	dgisselq	`reg spif_ctrl, spif_req;`
177	16	dgisselq	`reg alt_cmd, alt_ctrl;`
178	7	dgisselq	`wire [(ADDRESS_WIDTH-17):0] spif_sector;`
179	16	dgisselq	`assign spif_sector = spif_addr[(AW-1):14];`
180	2	dgisselq
181	7	dgisselq	`// assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };`
182
183	2	dgisselq	initial state = `WBQSPI_RESET;
184			`initial o_wb_ack = 1'b0;`
185			`initial o_wb_stall = 1'b1;`
186			`initial spi_wr = 1'b0;`
187			`initial spi_len = 2'b00;`
188			`initial quad_mode_enabled = 1'b0;`
189			`initial o_interrupt = 1'b0;`
190	16	dgisselq	`initial spif_override = 1'b1;`
191			`initial spif_ctrl = 1'b0;`
192			`always @(posedge i_clk)`
193	4	dgisselq	`begin`
194			`spif_override <= 1'b0;`
195	16	dgisselq	`alt_cmd <= (reset_counter[9:8]==2'b10)?reset_counter[3]:1'b1; // Toggle CS_n`
196			`alt_ctrl <= (reset_counter[9:8]==2'b10)?reset_counter[0]:1'b1; // Toggle clock too`
197	2	dgisselq	if (state == `WBQSPI_RESET)
198			`begin`
199			`// From a reset, we should`
200			`// Enable the Quad I/O mode`
201			`// Disable the Write protection bits in the status register`
202			`// Chip should already be up and running, so we can start`
203			`// immediately ....`
204			`o_wb_ack <= 1'b0;`
205			`o_wb_stall <= 1'b1;`
206	4	dgisselq	`spi_wr <= 1'b0;`
207	2	dgisselq	`spi_hold <= 1'b0;`
208			`spi_spd <= 1'b0;`
209			`spi_dir <= 1'b0;`
210			`last_status <= 8'h00;`
211	4	dgisselq	state <= `WBQSPI_RESET_QUADMODE;
212	2	dgisselq	`spif_req <= 1'b0;`
213	4	dgisselq	`spif_override <= 1'b1;`
214	16	dgisselq	`last_status <= 8'h00; //`
215			`reset_counter <= 10'h3fc; //`
216	4	dgisselq	`// This guarantees that we aren't starting in quad`
217			`// I/O mode, where the FPGA configuration scripts may`
218			`// have left us.`
219			end else if (state == `WBQSPI_RESET_QUADMODE)
220	2	dgisselq	`begin`
221	4	dgisselq	`// Okay, so here's the problem: we don't know whether or not`
222			`// the Xilinx loader started us up in Quad Read I/O idle mode.`
223	14	dgisselq	`// So, thus we need to toggle the clock and CS_n, with fewer`
224			`// clocks than are necessary to transmit a word.`
225			`//`
226	4	dgisselq	`// Not ready to handle the bus yet, so stall any requests`
227			`o_wb_ack <= 1'b0;`
228			`o_wb_stall <= 1'b1;`
229
230			`// Do something ...`
231	16	dgisselq	`if (reset_counter == 10'h00)`
232	2	dgisselq	`begin`
233	4	dgisselq	`spif_override <= 1'b0;`
234			state <= `WBQSPI_IDLE;
235	16	dgisselq
236			`// Find out if we can use Quad I/O mode ...`
237			state <= `WBQSPI_READ_CONFIG;
238			`spi_wr <= 1'b1;`
239			`spi_len <= 2'b01;`
240			`spi_in <= { 8'h35, 24'h00};`
241
242	4	dgisselq	`end else begin`
243	16	dgisselq	`reset_counter <= reset_counter - 10'h1;`
244	4	dgisselq	`spif_override <= 1'b1;`
245	2	dgisselq	`end`
246			end else if (state == `WBQSPI_IDLE)
247			`begin`
248			`o_interrupt <= 1'b0;`
249			`o_wb_stall <= 1'b0;`
250			`o_wb_ack <= 1'b0;`
251			`spif_cmd <= i_wb_we;`
252			`spif_addr <= i_wb_addr;`
253			`spif_data <= i_wb_data;`
254			`spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);`
255			`spif_req <= (i_wb_ctrl_stb)\|\|(i_wb_data_stb);`
256			`spi_wr <= 1'b0; // Keep the port idle, unless told otherwise`
257			`spi_hold <= 1'b0;`
258			`spi_spd <= 1'b0;`
259			`spi_dir <= 1'b0; // Write (for now, 'cause of cmd)`
260			`// Data register access`
261	14	dgisselq	`if (i_wb_data_stb)`
262	2	dgisselq	`begin`
263
264			`if (i_wb_we) // Request to write a page`
265			`begin`
266	7	dgisselq	`ifdef READ_ONLY
267			`o_wb_ack <= 1'b1;`
268			`o_wb_stall <= 1'b0;`
269			`end else`
270			`else
271	2	dgisselq	`if((~write_protect)&&(~write_in_progress))`
272			`begin // 00`
273			`spi_wr <= 1'b1;`
274			`spi_len <= 2'b00; // 8 bits`
275			`// Send a write enable command`
276			`spi_in <= { 8'h06, 24'h00 };`
277			state <= `WBQSPI_WEN;
278
279			`o_wb_ack <= 1'b0;`
280			`o_wb_stall <= 1'b1;`
281			`end else if (write_protect)`
282			`begin // whether or not write-in_progress ...`
283			`// Do nothing on a write protect`
284			`// violation`
285			`//`
286			`o_wb_ack <= 1'b1;`
287			`o_wb_stall <= 1'b0;`
288			`end else begin // write is in progress, wait`
289			`// for it to complete`
290			state <= `WBQSPI_WAIT_WIP_CLEAR;
291			`o_wb_ack <= 1'b0;`
292			`o_wb_stall <= 1'b1;`
293			`end`
294			`end else if (~write_in_progress)`
295	7	dgisselq	`endif
296	2	dgisselq	`begin // Read access, normal mode(s)`
297			`o_wb_ack <= 1'b0;`
298			`o_wb_stall <= 1'b1;`
299			`spi_wr <= 1'b1; // Write cmd to device`
300			`if (quad_mode_enabled)`
301			`begin`
302	14	dgisselq	`spi_in <= { 8'heb, w_wb_addr };`
303	2	dgisselq	state <= `WBQSPI_QRD_ADDRESS;
304			`spi_len <= 2'b00; // single byte, cmd only`
305			`end else begin`
306	14	dgisselq	`spi_in <= { 8'h0b, w_wb_addr };`
307	2	dgisselq	state <= `WBQSPI_RD_DUMMY;
308			`spi_len <= 2'b11; // cmd+addr,32bits`
309			`end`
310	7	dgisselq	`ifndef READ_ONLY
311	2	dgisselq	`end else begin`
312			`// A write is in progress ... need to stall`
313			`// the bus until the write is complete.`
314			state <= `WBQSPI_WAIT_WIP_CLEAR;
315			`o_wb_ack <= 1'b0;`
316			`o_wb_stall <= 1'b1;`
317	7	dgisselq	`endif
318	2	dgisselq	`end`
319	14	dgisselq	`end else if ((i_wb_ctrl_stb)&&(i_wb_we))`
320	2	dgisselq	`begin`
321	7	dgisselq	`ifdef READ_ONLY
322			`o_wb_ack <= 1'b1;`
323			`o_wb_stall <= 1'b0;`
324			`else
325	2	dgisselq	`o_wb_stall <= 1'b1;`
326			`case(i_wb_addr[1:0])`
327			`2'b00: begin // Erase command register`
328	16	dgisselq	`write_protect <= !i_wb_data[28];`
329	2	dgisselq	`o_wb_stall <= 1'b0;`
330
331	16	dgisselq	`if((i_wb_data[31])&&(!write_in_progress))`
332	2	dgisselq	`begin`
333			`// Command an erase--ack it immediately`
334
335			`o_wb_ack <= 1'b1;`
336			`o_wb_stall <= 1'b0;`
337
338			`if ((i_wb_data[31])&&(~write_protect))`
339			`begin`
340			`spi_wr <= 1'b1;`
341			`spi_len <= 2'b00;`
342			`// Send a write enable command`
343			`spi_in <= { 8'h06, 24'h00 };`
344			state <= `WBQSPI_ERASE_CMD;
345			`o_wb_stall <= 1'b1;`
346			`end`
347			`end else if (i_wb_data[31])`
348			`begin`
349			state <= `WBQSPI_WAIT_WIP_CLEAR;
350			`o_wb_ack <= 1'b1;`
351			`o_wb_stall <= 1'b1;`
352			`end else`
353			`o_wb_ack <= 1'b1;`
354			`o_wb_stall <= 1'b0;`
355			`end`
356			`2'b01: begin`
357			`// Write the configuration register`
358			`o_wb_ack <= 1'b1;`
359			`o_wb_stall <= 1'b1;`
360
361			`// Need to send a write enable command first`
362			`spi_wr <= 1'b1;`
363			`spi_len <= 2'b00; // 8 bits`
364			`// Send a write enable command`
365			`spi_in <= { 8'h06, 24'h00 };`
366			state <= `WBQSPI_WRITE_CONFIG;
367			`end`
368			`2'b10: begin`
369			`// Write the status register`
370			`o_wb_ack <= 1'b1; // Ack immediately`
371			`o_wb_stall <= 1'b1; // Stall other cmds`
372			`// Need to send a write enable command first`
373			`spi_wr <= 1'b1;`
374			`spi_len <= 2'b00; // 8 bits`
375			`// Send a write enable command`
376			`spi_in <= { 8'h06, 24'h00 };`
377			state <= `WBQSPI_WRITE_STATUS;
378			`end`
379			`2'b11: begin // Write the ID register??? makes no sense`
380			`o_wb_ack <= 1'b1;`
381			`o_wb_stall <= 1'b0;`
382			`end`
383			`endcase`
384	7	dgisselq	`endif
385	16	dgisselq	`end else if (i_wb_ctrl_stb) // &&(!i_wb_we))`
386	2	dgisselq	`begin`
387			`case(i_wb_addr[1:0])`
388			`2'b00: begin // Read local register`
389			`if (write_in_progress) // Read status`
390			`begin// register, is write still in progress?`
391			state <= `WBQSPI_READ_STATUS;
392			`spi_wr <= 1'b1;`
393			`spi_len <= 2'b01;// 8 bits out, 8 bits in`
394			`spi_in <= { 8'h05, 24'h00};`
395
396			`o_wb_ack <= 1'b0;`
397			`o_wb_stall <= 1'b1;`
398			`end else begin // Return w/o talking to device`
399			`o_wb_ack <= 1'b1;`
400			`o_wb_stall <= 1'b0;`
401			`o_wb_data <= { write_in_progress,`
402			`dirty_sector, spi_busy,`
403			`~write_protect,`
404			`quad_mode_enabled,`
405	7	dgisselq	`{(29-ADDRESS_WIDTH){1'b0}},`
406	2	dgisselq	`erased_sector, 14'h000 };`
407			`end end`
408			`2'b01: begin // Read configuration register`
409			state <= `WBQSPI_READ_CONFIG;
410			`spi_wr <= 1'b1;`
411			`spi_len <= 2'b01;`
412			`spi_in <= { 8'h35, 24'h00};`
413
414			`o_wb_ack <= 1'b0;`
415			`o_wb_stall <= 1'b1;`
416			`end`
417			`2'b10: begin // Read status register`
418			state <= `WBQSPI_READ_STATUS;
419			`spi_wr <= 1'b1;`
420			`spi_len <= 2'b01; // 8 bits out, 8 bits in`
421			`spi_in <= { 8'h05, 24'h00};`
422
423			`o_wb_ack <= 1'b0;`
424			`o_wb_stall <= 1'b1;`
425			`end`
426			`2'b11: begin // Read ID register`
427			state <= `WBQSPI_READ_ID_CMD;
428			`spi_wr <= 1'b1;`
429			`spi_len <= 2'b00;`
430			`spi_in <= { 8'h9f, 24'h00};`
431
432			`o_wb_ack <= 1'b0;`
433			`o_wb_stall <= 1'b1;`
434			`end`
435			`endcase`
436	7	dgisselq	`ifndef READ_ONLY
437	2	dgisselq	`end else if ((~i_wb_cyc)&&(write_in_progress))`
438			`begin`
439			state <= `WBQSPI_IDLE_CHECK_WIP;
440			`spi_wr <= 1'b1;`
441			`spi_len <= 2'b01; // 8 bits out, 8 bits in`
442			`spi_in <= { 8'h05, 24'h00};`
443
444			`o_wb_ack <= 1'b0;`
445			`o_wb_stall <= 1'b1;`
446	7	dgisselq	`endif
447	2	dgisselq	`end`
448			end else if (state == `WBQSPI_RDIDLE)
449			`begin`
450			`spi_wr <= 1'b0;`
451			`o_wb_stall <= 1'b0;`
452			`o_wb_ack <= 1'b0;`
453			`spif_cmd <= i_wb_we;`
454			`spif_addr <= i_wb_addr;`
455			`spif_data <= i_wb_data;`
456			`spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);`
457			`spif_req <= (i_wb_ctrl_stb)\|\|(i_wb_data_stb);`
458			`spi_hold <= 1'b0;`
459			`spi_spd<= 1'b1;`
460			`spi_dir <= 1'b0; // Write (for now)`
461	16	dgisselq	`if ((i_wb_data_stb)&&(!i_wb_we))`
462	2	dgisselq	`begin // Continue our read ... send the new address / mode`
463			`o_wb_stall <= 1'b1;`
464			`spi_wr <= 1'b1;`
465	4	dgisselq	`spi_len <= 2'b10; // Write address, but not mode byte`
466	14	dgisselq	`spi_in <= { w_wb_addr, 8'ha0 };`
467	2	dgisselq	state <= `WBQSPI_QRD_DUMMY;
468	16	dgisselq	`end else if((i_wb_ctrl_stb)&&(!i_wb_we)&&(i_wb_addr[1:0] == 2'b00))`
469	2	dgisselq	`begin`
470			`// A local read that doesn't touch the device, so leave`
471			`// the device in its current state`
472			`o_wb_stall <= 1'b0;`
473			`o_wb_ack <= 1'b1;`
474			`o_wb_data <= { write_in_progress,`
475			`dirty_sector, spi_busy,`
476			`~write_protect,`
477			`quad_mode_enabled,`
478	7	dgisselq	`{(29-ADDRESS_WIDTH){1'b0}},`
479	2	dgisselq	`erased_sector, 14'h000 };`
480	14	dgisselq	`end else if(((i_wb_ctrl_stb)\|\|(i_wb_data_stb)))`
481	2	dgisselq	`begin // Need to release the device from quad mode for all else`
482			`o_wb_ack <= 1'b0;`
483			`o_wb_stall <= 1'b1;`
484			`spi_wr <= 1'b1;`
485			`spi_len <= 2'b11;`
486			`spi_in <= 32'h00;`
487			state <= `WBQSPI_WBDECODE;
488			`end`
489			end else if (state == `WBQSPI_WBDECODE)
490			`begin`
491			`// We were in quad SPI read mode, and had to get out.`
492			`// Now we've got a command (not data read) to read and`
493			`// execute. Accomplish what we would've done while in the`
494			`// IDLE state here, save only that we don't have to worry`
495			`// about data reads, and we need to operate on a stored`
496			`// version of the bus command`
497			`o_wb_stall <= 1'b1;`
498			`o_wb_ack <= 1'b0;`
499			`spi_wr <= 1'b0; // Keep the port idle, unless told otherwise`
500			`spi_hold <= 1'b0;`

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