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URL https://opencores.org/ocsvn/radiohdl/radiohdl/trunk

Subversion Repositories radiohdl

[/] [radiohdl/] [trunk/] [base/] [qsys_input.qsys] - Blame information for rev 2

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Line No. Rev Author Line
1 2 danv
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   name="$${FILENAME}"
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   displayName="$${FILENAME}"
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   version="1.0"
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   description=""
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   tags=""
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   categories="System" />
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{
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   element $${FILENAME}
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   {
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   }
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   element jtag_uart_0.avalon_jtag_slave
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   {
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      datum baseAddress
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      {
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         value = "272";
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         type = "long";
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      }
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   }
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   element avs_eth_0
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   {
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      datum _sortIndex
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      {
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         value = "0";
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         type = "int";
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      }
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      datum sopceditor_expanded
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      {
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         value = "0";
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         type = "boolean";
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      }
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   }
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   element clk_input
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   {
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      datum _sortIndex
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      {
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         value = "6";
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         type = "int";
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      }
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      datum sopceditor_expanded
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      {
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         value = "0";
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         type = "boolean";
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      }
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   }
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   element cpu_0
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   {
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      datum _sortIndex
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      {
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         value = "1";
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         type = "int";
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      }
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      datum sopceditor_expanded
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      {
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         value = "0";
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         type = "boolean";
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      }
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   }
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   element cpu_0.jtag_debug_module
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   {
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      datum baseAddress
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      {
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         value = "14336";
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         type = "long";
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      }
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   }
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   element jtag_uart_0
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   {
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      datum _sortIndex
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      {
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         value = "3";
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         type = "int";
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      }
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      datum megawizard_uipreferences
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      {
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         value = "{}";
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         type = "String";
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      }
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      datum sopceditor_expanded
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      {
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         value = "0";
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         type = "boolean";
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      }
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   }
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   element avs_eth_0.mms_ram
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   {
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      datum baseAddress
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      {
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         value = "16384";
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         type = "long";
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      }
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   }
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   element avs_eth_0.mms_reg
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   {
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      datum baseAddress
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      {
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         value = "128";
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         type = "long";
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      }
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   }
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   element avs_eth_0.mms_tse
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   {
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      datum baseAddress
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      {
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         value = "8192";
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         type = "long";
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      }
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   }
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   element onchip_memory2_0
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   {
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      datum _sortIndex
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      {
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         value = "2";
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         type = "int";
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      }
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      datum megawizard_uipreferences
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      {
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         value = "{output_language=VHDL, output_directory=D:\\svnroot\\UniBoard_FP7\\UniBoard\\trunk\\Firmware\\designs\\unb_unb1_minimal\\build\\synth\\quartus}";
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         type = "String";
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      }
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      datum sopceditor_expanded
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      {
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         value = "0";
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         type = "boolean";
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      }
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   }
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   element pio_wdi
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   {
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      datum _sortIndex
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      {
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         value = "4";
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         type = "int";
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      }
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      datum megawizard_uipreferences
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      {
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         value = "{}";
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         type = "String";
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      }
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      datum sopceditor_expanded
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      {
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         value = "0";
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         type = "boolean";
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      }
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   }
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   element avs_eth_0.ram_write
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   {
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      datum _tags
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      {
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         value = "";
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         type = "String";
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      }
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   }
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   element onchip_memory2_0.s1
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   {
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      datum _lockedAddress
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      {
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         value = "1";
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         type = "boolean";
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      }
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      datum baseAddress
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      {
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         value = "131072";
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         type = "long";
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      }
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   }
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   element pio_wdi.s1
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   {
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      datum baseAddress
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      {
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         value = "256";
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         type = "long";
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      }
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   }
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   element timer_0.s1
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   {
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      datum baseAddress
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      {
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         value = "192";
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         type = "long";
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      }
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   }
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   element timer_0
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   {
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      datum _sortIndex
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      {
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         value = "5";
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         type = "int";
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      }
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      datum sopceditor_expanded
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      {
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         value = "0";
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         type = "boolean";
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      }
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   }
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}
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]]>
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   name="pio_wdi_external_connection"
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   internal="pio_wdi.external_connection"
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   type="conduit"
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   dir="end">
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   name="eth1g_mm_rst"
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   internal="avs_eth_0.reset"
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   type="conduit"
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   dir="end" />
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   name="eth1g_tse_address"
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   internal="avs_eth_0.tse_address"
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   type="conduit"
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   dir="end" />
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   name="eth1g_tse_write"
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   internal="avs_eth_0.tse_write"
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   type="conduit"
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   dir="end" />
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   name="eth1g_tse_read"
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   internal="avs_eth_0.tse_read"
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   type="conduit"
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   dir="end" />
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   name="eth1g_tse_writedata"
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   internal="avs_eth_0.tse_writedata"
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   type="conduit"
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   dir="end" />
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   name="eth1g_tse_readdata"
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   internal="avs_eth_0.tse_readdata"
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   type="conduit"
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   dir="end" />
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   name="eth1g_tse_waitrequest"
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   internal="avs_eth_0.tse_waitrequest"
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   type="conduit"
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   dir="end" />
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   name="eth1g_reg_address"
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   internal="avs_eth_0.reg_address"
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   type="conduit"
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   dir="end" />
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   name="eth1g_reg_write"
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   internal="avs_eth_0.reg_write"
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   type="conduit"
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   dir="end" />
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   name="eth1g_reg_read"
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   internal="avs_eth_0.reg_read"
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   type="conduit"
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   dir="end" />
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   name="eth1g_reg_writedata"
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   internal="avs_eth_0.reg_writedata"
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   type="conduit"
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   dir="end" />
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   name="eth1g_reg_readdata"
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   internal="avs_eth_0.reg_readdata"
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   type="conduit"
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   dir="end" />
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   name="eth1g_ram_address"
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   internal="avs_eth_0.ram_address"
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   type="conduit"
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   dir="end" />
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   name="eth1g_ram_write"
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   internal="avs_eth_0.ram_write"
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   type="conduit"
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   dir="end" />
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   name="eth1g_ram_read"
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   internal="avs_eth_0.ram_read"
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   type="conduit"
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   dir="end" />
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   name="eth1g_ram_writedata"
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   internal="avs_eth_0.ram_writedata"
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   type="conduit"
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   dir="end" />
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   name="eth1g_ram_readdata"
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   internal="avs_eth_0.ram_readdata"
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   type="conduit"
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   dir="end" />
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   name="reset_in"
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   internal="clk_input.clk_in_reset"
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   type="reset"
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   dir="end" />
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   kind="altera_avalon_onchip_memory2"
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   version="11.1"
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   enabled="1"
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   name="onchip_memory2_0">
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  qsys_input_onchip_memory2_0
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   kind="altera_avalon_jtag_uart"
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   version="11.1"
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   enabled="1"
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   name="jtag_uart_0">
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q]]>
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  INTERACTIVE_ASCII_OUTPUT
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  SIMPLE_PERIODIC_INTERRUPT
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  cpu_0.jtag_debug_module
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  ]]>
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  ]]>
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  ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
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499
   kind="avalon"
500
   version="11.1"
501
   start="cpu_0.instruction_master"
502
   end="cpu_0.jtag_debug_module">
503
  
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506
 
507
   kind="avalon"
508
   version="11.1"
509
   start="cpu_0.data_master"
510
   end="cpu_0.jtag_debug_module">
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514
 
515
   kind="avalon"
516
   version="11.1"
517
   start="cpu_0.instruction_master"
518
   end="onchip_memory2_0.s1">
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523
   kind="avalon"
524
   version="11.1"
525
   start="cpu_0.data_master"
526
   end="onchip_memory2_0.s1">
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531
   kind="avalon"
532
   version="11.1"
533
   start="cpu_0.data_master"
534
   end="jtag_uart_0.avalon_jtag_slave">
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539
   kind="interrupt"
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   version="11.1"
541
   start="cpu_0.d_irq"
542
   end="jtag_uart_0.irq">
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   kind="avalon"
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   version="11.1"
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   start="cpu_0.data_master"
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   end="pio_wdi.s1">
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   kind="avalon"
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   version="11.1"
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   start="cpu_0.data_master"
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   end="timer_0.s1">
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   kind="reset"
566
   version="11.1"
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   start="cpu_0.jtag_debug_module_reset"
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   end="onchip_memory2_0.reset1" />
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   kind="reset"
571
   version="11.1"
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   start="cpu_0.jtag_debug_module_reset"
573
   end="jtag_uart_0.reset" />
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   kind="reset"
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   version="11.1"
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   start="cpu_0.jtag_debug_module_reset"
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   end="pio_wdi.reset" />
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   kind="reset"
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   version="11.1"
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   start="cpu_0.jtag_debug_module_reset"
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   end="timer_0.reset" />
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   kind="reset"
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   version="11.1"
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   start="cpu_0.jtag_debug_module_reset"
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   end="cpu_0.reset_n" />
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   kind="avalon"
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   version="11.1"
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   start="cpu_0.data_master"
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   end="avs_eth_0.mms_tse">
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   kind="avalon"
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   version="11.1"
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   start="cpu_0.data_master"
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   end="avs_eth_0.mms_reg">
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   kind="avalon"
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   version="11.1"
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   start="cpu_0.data_master"
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   end="avs_eth_0.mms_ram">
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   kind="interrupt"
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   version="11.1"
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   start="cpu_0.d_irq"
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   end="avs_eth_0.interrupt">
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   kind="reset"
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   version="11.1"
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   start="cpu_0.jtag_debug_module_reset"
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   end="avs_eth_0.mm_reset" />
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   kind="reset"
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   version="11.1"
628
   start="clk_input.clk_reset"
629
   end="timer_0.reset" />
630
 
631
   kind="reset"
632
   version="11.1"
633
   start="clk_input.clk_reset"
634
   end="pio_wdi.reset" />
635
 
636
   kind="reset"
637
   version="11.1"
638
   start="clk_input.clk_reset"
639
   end="jtag_uart_0.reset" />
640
 
641
   kind="reset"
642
   version="11.1"
643
   start="clk_input.clk_reset"
644
   end="onchip_memory2_0.reset1" />
645
 
646
   kind="reset"
647
   version="11.1"
648
   start="clk_input.clk_reset"
649
   end="cpu_0.reset_n" />
650
 
651
   kind="reset"
652
   version="11.1"
653
   start="clk_input.clk_reset"
654
   end="avs_eth_0.mm_reset" />
655
 
656
 
657
 
658
   kind="clock"
659
   version="11.1"
660
   start="clk_input.clk"
661
   end="jtag_uart_0.clk" />
662
 
663
   kind="clock"
664
   version="11.1"
665
   start="clk_input.clk"
666
   end="onchip_memory2_0.clk1" />
667
 
668
 
669

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