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[/] [ram_wb/] [trunk/] [rtl/] [verilog/] [wb_ram_sc_sw.v] - Blame information for rev 7

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1 7 unneback
module ram (dat_i, dat_o, adr_i, we_i, clk );
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   parameter dat_width = 32;
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   parameter adr_width = 11;
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   parameter mem_size  = 2048;
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   input [dat_width-1:0]      dat_i;
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   input [adr_width-1:0]      adr_i;
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   input                      we_i;
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   output reg [dat_width-1:0] dat_o;
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   input                      clk;
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   reg [dat_width-1:0] ram [0:mem_size - 1] /* synthesis ram_style = no_rw_check */;
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   always @ (posedge clk)
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     begin
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        dat_o <= ram[adr_i];
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        if (we_i)
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          ram[adr_i] <= dat_i;
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     end
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endmodule // ram

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