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[/] [ratpack/] [trunk/] [rtl/] [vhdl/] [ratalu.vhd] - Blame information for rev 5

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1 5 kavi 
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use WORK.ratpack.all;
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entity ratalu is
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  port (
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    a   : in  rational;
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    b   : in  rational;
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    sel : in  std_logic_vector(4 downto 0);
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    y   : out rational
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  );
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end ratalu;
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architecture rtl of ratalu is
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  signal temp : rational;
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  constant OP_ADD : std_logic_vector(4 downto 0) := "00000";
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  constant OP_SUB : std_logic_vector(4 downto 0) := "00001";
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  constant OP_MUL : std_logic_vector(4 downto 0) := "00010";
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  constant OP_DIV : std_logic_vector(4 downto 0) := "00011";
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  constant OP_ABS : std_logic_vector(4 downto 0) := "00100";
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  constant OP_MAX : std_logic_vector(4 downto 0) := "00101";
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  constant OP_MIN : std_logic_vector(4 downto 0) := "00110";
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  constant OP_CGT : std_logic_vector(4 downto 0) := "00111";
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  constant OP_CLT : std_logic_vector(4 downto 0) := "01000";
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  constant OP_CGE : std_logic_vector(4 downto 0) := "01001";
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  constant OP_CLE : std_logic_vector(4 downto 0) := "01010";
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  constant OP_CEQ : std_logic_vector(4 downto 0) := "01011";
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  constant OP_CNE : std_logic_vector(4 downto 0) := "01100";
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  constant OP_MED : std_logic_vector(4 downto 0) := "01101";
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begin
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 process (a, b, sel)
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  begin
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    case sel is
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      when OP_ADD => temp <= a + b;
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      when OP_SUB => temp <= a - b;
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      when OP_MUL => temp <= a * b;
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      when OP_DIV => temp <= a / b;
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      when OP_ABS => temp <= a abs b;
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      when OP_MAX => temp <= a max b;
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      when OP_MIN => temp <= a min b;
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      when OP_CGT =>
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        if (a > b) then
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          temp <= RAT_ONE;
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        else
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          temp <= RAT_ZERO;
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        end if;
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      when OP_CLT =>
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        if (a < b) then
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          temp <= RAT_ONE;
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        else
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          temp <= RAT_ZERO;
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        end if;
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      when OP_CGE =>
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        if (a >= b) then
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          temp <= RAT_ONE;
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        else
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          temp <= RAT_ZERO;
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        end if;
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      when OP_CLE =>
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        if (a <= b) then
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          temp <= RAT_ONE;
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        else
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          temp <= RAT_ZERO;
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        end if;
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      when OP_CEQ =>
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        if (a = b) then
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          temp <= RAT_ONE;
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        else
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          temp <= RAT_ZERO;
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        end if;
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      when OP_CNE =>
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        if (a /= b) then
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          temp <= RAT_ONE;
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        else
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          temp <= RAT_ZERO;
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        end if;
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      when OP_MED => temp <= mediant(a, b);
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      when others => temp <= RAT_ZERO;
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    end case;
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  end process;
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  y <= temp;
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end rtl;

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