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/*
        RC4 PRGA module implementation
        Copyright 2012 - Alfredo Ortega
        aortega@alu.itba.edu.ar
 
 This library is free software: you can redistribute it and/or
 modify it under the terms of the GNU Lesser General Public
 License as published by the Free Software Foundation, either
 version 3 of the License, or (at your option) any later version.
 
 This library is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 Lesser General Public License for more details.
 
 You should have received a copy of the GNU Lesser General Public
 License along with this library.  If not, see <http://www.gnu.org/licenses/>.
*/
 
 
`include "/home/alfred/docto/FPGADesign/rc4-prbs/trunk/rc4.inc"
 
module rc4(clk,rst,output_ready,password_input,K);
 
input clk; // Clock
input rst; // Reset
input [7:0] password_input; // Password input
output output_ready; // Output valid
output [7:0] K; // Output port
 
 
wire clk, rst; // clock, reset
reg output_ready;
wire [7:0] password_input;
 
 
/* RC4 PRGA */
 
// Key
reg [7:0] key[0:`KEY_SIZE-1];
// S array
reg [7:0] S[0:256];
 
// Key-scheduling state
`define KSS_KEYREAD 4'h0
`define KSS_KEYSCHED1 4'h1
`define KSS_KEYSCHED2 4'h2
`define KSS_KEYSCHED3 4'h3
`define KSS_CRYPTO       4'h4
`define KSS_CRYPTO2      4'h5
// Variable names from http://en.wikipedia.org/wiki/RC4
reg [3:0] KSState;
reg [7:0] i; // Counter
reg [7:0] j;
reg [7:0] K;
 
always @ (posedge clk or posedge rst)
        begin
        if (rst)
                begin
                i <= 8'h0;
                KSState <= `KSS_KEYREAD;
                output_ready <= 0;
                j <= 0;
                end
        else
        case (KSState)
                `KSS_KEYREAD:   begin // KSS_KEYREAD state: Read key from input
                                if (i == `KEY_SIZE)
                                        begin
                                        KSState <= `KSS_KEYSCHED1;
                                        i<=8'h00;
                                        end
                                else    begin
                                        i <= i+1;
                                        key[i] <= password_input;
                                        $display ("key[%d] = %08X",i,password_input);
                                        end
                                end
/*
for i from 0 to 255
    S[i] := i
endfor
*/
                `KSS_KEYSCHED1: begin // KSS_KEYSCHED1: Increment counter for S initialization
                                S[i] <= i;
                                if (i == 8'hFF)
                                        begin
                                        KSState <= `KSS_KEYSCHED2;
                                        i <= 8'h00;
                                        end
                                else    i <= i +1;
                                end
/*
j := 0
for i from 0 to 255
    j := (j + S[i] + key[i mod keylength]) mod 256
    swap values of S[i] and S[j]
endfor
*/
                `KSS_KEYSCHED2: begin // KSS_KEYSCHED2: Initialize S array
                                j <= (j + S[i] + key[i % `KEY_SIZE]);
                                KSState <= `KSS_KEYSCHED3;
                                end
                `KSS_KEYSCHED3: begin // KSS_KEYSCHED3: S array permutation
                                S[i]<=S[j];
                                S[j]<=S[i];
                                if (i == 8'hFF)
                                        begin
                                        KSState <= `KSS_CRYPTO;
                                        i <= 8'h01;
                                        j <= 8'h00;
                                        end
                                else    begin
                                        i <= i + 1;
                                        KSState <= `KSS_KEYSCHED2;
                                        end
                                end
/*
i := 0
j := 0
while GeneratingOutput:
    i := (i + 1) mod 256
    j := (j + S[i]) mod 256
    swap values of S[i] and S[j]
    K := S[(S[i] + S[j]) mod 256]
    output K
endwhile
*/
                `KSS_CRYPTO: begin      //KSS_CRYPTO: Output crypto stream
                                j <= (j + S[i]);
                                KSState <= `KSS_CRYPTO2;
                                output_ready <= 0; // K not valid yet
                                end
                `KSS_CRYPTO2: begin
                                S[i] <= S[j];
                                S[j] <= S[i]; // We can do this because of verilog.
                                K <= S[ S[i]+S[j] ];
                                output_ready <= 1; // Valid K at output
                                i <= i+1;
                                KSState <= `KSS_CRYPTO;
                                end
                default:        begin
                                end
        endcase
        end
 
endmodule

Line No.	Rev	Author	Line
1	3	ortegaalfr	`/*`
2			`RC4 PRGA module implementation`
3			`Copyright 2012 - Alfredo Ortega`
4			`aortega@alu.itba.edu.ar`
5
6			`This library is free software: you can redistribute it and/or`
7			`modify it under the terms of the GNU Lesser General Public`
8			`License as published by the Free Software Foundation, either`
9			`version 3 of the License, or (at your option) any later version.`
10
11			`This library is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`Lesser General Public License for more details.`
15
16			`You should have received a copy of the GNU Lesser General Public`
17			`License along with this library. If not, see <http://www.gnu.org/licenses/>.`
18			`*/`
19
20
21	7	ortegaalfr	`include "/home/alfred/docto/FPGADesign/rc4-prbs/trunk/rc4.inc"
22	3	ortegaalfr
23			`module rc4(clk,rst,output_ready,password_input,K);`
24
25			`input clk; // Clock`
26			`input rst; // Reset`
27			`input [7:0] password_input; // Password input`
28			`output output_ready; // Output valid`
29			`output [7:0] K; // Output port`
30
31
32			`wire clk, rst; // clock, reset`
33			`reg output_ready;`
34			`wire [7:0] password_input;`
35
36
37			`/* RC4 PRGA */`
38
39			`// Key`
40			reg [7:0] key[0:`KEY_SIZE-1];
41			`// S array`
42			`reg [7:0] S[0:256];`
43
44			`// Key-scheduling state`
45			`define KSS_KEYREAD 4'h0
46			`define KSS_KEYSCHED1 4'h1
47			`define KSS_KEYSCHED2 4'h2
48			`define KSS_KEYSCHED3 4'h3
49	7	ortegaalfr	`define KSS_CRYPTO 4'h4
50			`define KSS_CRYPTO2 4'h5
51	3	ortegaalfr	`// Variable names from http://en.wikipedia.org/wiki/RC4`
52			`reg [3:0] KSState;`
53			`reg [7:0] i; // Counter`
54			`reg [7:0] j;`
55			`reg [7:0] K;`
56
57			`always @ (posedge clk or posedge rst)`
58			`begin`
59			`if (rst)`
60			`begin`
61			`i <= 8'h0;`
62			KSState <= `KSS_KEYREAD;
63			`output_ready <= 0;`
64			`j <= 0;`
65			`end`
66	7	ortegaalfr	`else`
67	3	ortegaalfr	`case (KSState)`
68			`KSS_KEYREAD: begin // KSS_KEYREAD state: Read key from input
69			if (i == `KEY_SIZE)
70			`begin`
71			KSState <= `KSS_KEYSCHED1;
72			`i<=8'h00;`
73			`end`
74			`else begin`
75			`i <= i+1;`
76			`key[i] <= password_input;`
77			`$display ("key[%d] = %08X",i,password_input);`
78			`end`
79			`end`
80	7	ortegaalfr	`/*`
81			`for i from 0 to 255`
82			`S[i] := i`
83			`endfor`
84			`*/`
85	3	ortegaalfr	`KSS_KEYSCHED1: begin // KSS_KEYSCHED1: Increment counter for S initialization
86			`S[i] <= i;`
87			`if (i == 8'hFF)`
88			`begin`
89			KSState <= `KSS_KEYSCHED2;
90			`i <= 8'h00;`
91			`end`
92			`else i <= i +1;`
93			`end`
94	7	ortegaalfr	`/*`
95			`j := 0`
96			`for i from 0 to 255`
97			`j := (j + S[i] + key[i mod keylength]) mod 256`
98			`swap values of S[i] and S[j]`
99			`endfor`
100			`*/`
101	3	ortegaalfr	`KSS_KEYSCHED2: begin // KSS_KEYSCHED2: Initialize S array
102			j <= (j + S[i] + key[i % `KEY_SIZE]);
103			KSState <= `KSS_KEYSCHED3;
104			`end`
105	5	ortegaalfr	`KSS_KEYSCHED3: begin // KSS_KEYSCHED3: S array permutation
106	3	ortegaalfr	`S[i]<=S[j];`
107			`S[j]<=S[i];`
108			`if (i == 8'hFF)`
109			`begin`
110			KSState <= `KSS_CRYPTO;
111	7	ortegaalfr	`i <= 8'h01;`
112			`j <= 8'h00;`
113	3	ortegaalfr	`end`
114			`else begin`
115			`i <= i + 1;`
116			KSState <= `KSS_KEYSCHED2;
117			`end`
118			`end`
119	7	ortegaalfr	`/*`
120			`i := 0`
121			`j := 0`
122			`while GeneratingOutput:`
123			`i := (i + 1) mod 256`
124			`j := (j + S[i]) mod 256`
125			`swap values of S[i] and S[j]`
126			`K := S[(S[i] + S[j]) mod 256]`
127			`output K`
128			`endwhile`
129			`*/`
130			`KSS_CRYPTO: begin //KSS_CRYPTO: Output crypto stream
131			`j <= (j + S[i]);`
132			KSState <= `KSS_CRYPTO2;
133			`output_ready <= 0; // K not valid yet`
134	3	ortegaalfr	`end`
135	7	ortegaalfr	`KSS_CRYPTO2: begin
136			`S[i] <= S[j];`
137			`S[j] <= S[i]; // We can do this because of verilog.`
138			`K <= S[ S[i]+S[j] ];`
139			`output_ready <= 1; // Valid K at output`
140			`i <= i+1;`
141			KSState <= `KSS_CRYPTO;
142			`end`
143	3	ortegaalfr	`default: begin`
144			`end`
145			`endcase`
146			`end`
147
148			`endmodule`

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[/] [rc4-prbs/] [trunk/] [rc4.v] - Blame information for rev 7