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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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// rf6809.sv
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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import rf6809_pkg::*;
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module rf6809(id, rst_i, clk_i, halt_i, nmi_i, irq_i, firq_i, vec_i, ba_o, bs_o, lic_o, tsc_i,
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rty_i, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, we_o, ack_i, aack_i, atag_i,
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adr_o, dat_i, dat_o, state);
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parameter RESET = 6'd0;
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parameter IFETCH = 6'd1;
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parameter DECODE = 6'd2;
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parameter CALC = 6'd3;
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parameter PULL1 = 6'd4;
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parameter PUSH1 = 6'd5;
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parameter PUSH2 = 6'd6;
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parameter LOAD1 = 6'd7;
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parameter LOAD2 = 6'd8;
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parameter STORE1 = 6'd9;
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parameter STORE2 = 6'd10;
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parameter OUTER_INDEXING = 6'd11;
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parameter OUTER_INDEXING2 = 6'd12;
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parameter ICACHE1 = 6'd31;
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parameter ICACHE2 = 6'd32;
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parameter ICACHE3 = 6'd33;
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parameter ICACHE4 = 6'd34;
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parameter ICACHE5 = 6'd35;
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parameter ICACHE6 = 6'd36;
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parameter ICACHE7 = 6'd37;
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parameter ICACHE8 = 6'd38;
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parameter ICACHE9 = 6'd39;
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parameter IBUF1 = 6'd40;
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parameter IBUF2 = 6'd41;
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parameter IBUF3 = 6'd42;
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parameter IBUF4 = 6'd43;
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parameter IBUF5 = 6'd44;
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parameter IBUF6 = 6'd45;
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input [5:0] id;
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input rst_i;
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input clk_i;
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input halt_i;
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input nmi_i;
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input irq_i;
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input firq_i;
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input [`TRPBYTE] vec_i;
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output reg ba_o;
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output reg bs_o;
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output lic_o;
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input tsc_i;
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input rty_i;
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output reg [1:0] bte_o;
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output reg [2:0] cti_o;
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output reg [5:0] bl_o;
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output reg cyc_o;
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output reg stb_o;
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output reg we_o;
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output reg lock_o;
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input ack_i;
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input aack_i;
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input [3:0] atag_i;
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output reg [`TRPBYTE] adr_o;
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input [`LOBYTE] dat_i;
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output reg [`LOBYTE] dat_o;
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output [5:0] state;
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reg [5:0] state;
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reg [5:0] load_what,store_what,load_what2;
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reg [`TRPBYTE] pc;
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wire [`TRPBYTE] pcp2 = pc + 4'd2;
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wire [`TRPBYTE] pcp16 = pc + 5'd16;
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wire [`HEXBYTE] insn;
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wire icacheOn = 1'b1;
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reg [`TRPBYTE] ibufadr, icwa;
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reg [191:0] ibuf;
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wire ibufhit = ibufadr==pc;
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reg natMd,firqMd;
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reg md32;
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wire [`DBLBYTE] mask = 24'hFFFFFF;
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reg [1:0] ipg;
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reg isFar;
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reg isOuterIndexed;
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reg [`HEXBYTE] ir;
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`ifdef EIGHTBIT
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wire [9:0] ir12 = {ipg,ir[`LOBYTE]};
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`endif
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`ifdef TWELVEBIT
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wire [`LOBYTE] ir12 = ir[`LOBYTE];
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`endif
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reg [`LOBYTE] dpr; // direct page register
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reg [`DBLBYTE] usppg; // user stack pointer page
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wire [`LOBYTE] ndxbyte;
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reg cf,vf,zf,nf,hf,ef;
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wire [`LOBYTE] cfx8 = cf;
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wire [`DBLBYTE] cfx24 = {23'b0,cf};
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reg im,firqim;
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reg sync_state,wait_state;
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wire [`LOBYTE] ccr = {ef,firqim,hf,im,nf,zf,vf,cf};
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reg [`LOBYTE] acca,accb;
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reg [`DBLBYTE] accd;
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reg [`DBLBYTE] xr,yr,usp,ssp;
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wire [`DBLBYTE] prod = acca * accb;
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reg [`DBLBYTE] vect;
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reg [`DBLBYTEP1] res;
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reg [`LOBYTEP1] res12;
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wire res12n = res12[BPBM1];
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wire res12z = res12[`LOBYTE]==12'h000;
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wire res12c = res12[bitsPerByte];
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wire res24n = res[BPBX2M1];
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wire res24z = res[`DBLBYTE]==24'h000000;
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wire res24c = res[BPB*2];
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reg [`TRPBYTE] ia;
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reg ic_invalidate;
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reg first_ifetch;
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reg tsc_latched;
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wire tsc = tsc_i|tsc_latched;
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reg [`LOBYTE] chkpoint;
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reg [15:0] icgot;
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reg [23:0] btocnt;
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reg bto; // bus timed out
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reg [`DBLBYTE] a,b;
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wire [`LOBYTE] b12 = b[`LOBYTE];
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reg [`TRPBYTE] radr,wadr;
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reg [`DBLBYTE] wdat;
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reg nmi1,nmi_edge;
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reg nmi_armed;
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reg isStore;
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reg isPULU,isPULS;
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reg isPSHS,isPSHU;
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reg isRTS,isRTI,isRTF;
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reg isLEA;
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reg isRMW;
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// Data input path multiplexing
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reg [BPB-1:0] dati;
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always_comb
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dati = dat_i;
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// Evaluate the branch conditional
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reg takb;
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always_comb
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case(ir12)
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`BRA,`LBRA: takb <= 1'b1;
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`BRN,`LBRN: takb <= 1'b0;
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`BHI,`LBHI: takb <= !cf & !zf;
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`BLS,`LBLS: takb <= cf | zf;
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`BLO,`LBLO: takb <= cf;
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`BHS,`LBHS: takb <= !cf;
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`BNE,`LBNE: takb <= !zf;
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`BEQ,`LBEQ: takb <= zf;
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`BMI,`LBMI: takb <= nf;
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`BPL,`LBPL: takb <= !nf;
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`BVS,`LBVS: takb <= vf;
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`BVC,`LBVC: takb <= !vf;
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`BGT,`LBGT: takb <= (nf & vf & !zf) | (!nf & !vf & !zf);
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`BGE,`LBGE: takb <= (nf & vf) | (!nf & !vf);
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`BLE,`LBLE: takb <= zf | (nf & !vf) | (!nf & vf);
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`BLT,`LBLT: takb <= (nf & !vf) | (!nf & vf);
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default: takb <= 1'b1;
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endcase
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// This chunk of code takes care of calculating the number of bytes stacked
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// by a push or pull operation.
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//
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reg [4:0] cnt;
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always_comb
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begin
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cnt = (ir[bitsPerByte] ? 5'd1 : 5'd0) +
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(ir[bitsPerByte+1] ? 5'd1 : 5'd0) +
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(ir[bitsPerByte+2] ? 5'd1 : 5'd0) +
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(ir[bitsPerByte+3] ? 5'd1 : 5'd0) +
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(ir[bitsPerByte+4] ? 5'd2 : 5'd0) +
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(ir[bitsPerByte+5] ? 5'd2 : 5'd0) +
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(ir[bitsPerByte+6] ? 5'd2 : 5'd0) +
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(ir[bitsPerByte+7] ? 5'd2 : 5'd0)
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;
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// cnt = 0;
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// if (ir[8]) cnt = cnt + 5'd1; // CC
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// if (ir[9]) cnt = cnt + md32 ? 5'd4 : 5'd1; // A
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// if (ir[10]) cnt = cnt + md32 ? 5'd4 : 5'd1; // B
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// if (ir[BPBM1]) cnt = cnt + 5'd1; // DP
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// if (ir[12]) cnt = cnt + md32 ? 5'd4 : 5'd2; // X
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// if (ir[bitsPerByte+1]) cnt = cnt + md32 ? 5'd4 : 5'd2; // Y
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// if (ir[bitsPerByte+2]) cnt = cnt + md32 ? 5'd4 : 5'd2; // U/S
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// if (ir[bitsPerByte+3]) cnt = cnt + 5'd4; // PC
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end
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wire isRMW1 = ir12==`NEG_DP || ir12==`COM_DP || ir12==`LSR_DP || ir12==`ROR_DP || ir12==`ASR_DP || ir12==`ASL_DP || ir12==`ROL_DP || ir12==`DEC_DP || ir12==`INC_DP ||
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ir12==`NEG_NDX || ir12==`COM_NDX || ir12==`LSR_NDX || ir12==`ROR_NDX || ir12==`ASR_NDX || ir12==`ASL_NDX || ir12==`ROL_NDX || ir12==`DEC_NDX || ir12==`INC_NDX ||
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ir12==`NEG_EXT || ir12==`COM_EXT || ir12==`LSR_EXT || ir12==`ROR_EXT || ir12==`ASR_EXT || ir12==`ASL_EXT || ir12==`ROL_EXT || ir12==`DEC_EXT || ir12==`INC_EXT
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;
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wire isIndexed =
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ir12[7:4]==4'h6 || ir12[7:4]==4'hA || ir12[7:4]==4'hE ||
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ir12==`LEAX_NDX || ir12==`LEAY_NDX || ir12==`LEAS_NDX || ir12==`LEAU_NDX
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;
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reg isDblIndirect;
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wire isIndirect = ndxbyte[BPBM1-3] & ndxbyte[BPBM1];
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assign ndxbyte = ir[`HIBYTE];
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// Detect type of interrupt
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wire isINT = ir12==`INT;
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wire isRST = vect[3:0]==4'hE;
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wire isNMI = vect[3:0]==4'hC;
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wire isSWI = vect[3:0]==4'hA;
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wire isIRQ = vect[3:0]==4'h8;
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wire isFIRQ = vect[3:0]==4'h6;
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wire isSWI2 = vect[3:0]==4'h4;
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wire isSWI3 = vect[3:0]==4'h2;
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wire [`TRPBYTE] far_address = {ir[`HIBYTE],ir[`BYTE3],ir[`BYTE4]};
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wire [`TRPBYTE] address = {ir[`HIBYTE],ir[`BYTE3]};
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wire [`TRPBYTE] dp_address = {dpr,ir[`HIBYTE]};
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wire [`TRPBYTE] ex_address = isFar ? far_address : address;
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wire [`TRPBYTE] offset12 = {{bitsPerByte{ir[bitsPerByte*3-1]}},ir[`BYTE3]};
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wire [`TRPBYTE] offset24 = {ir[`BYTE3],ir[`BYTE4]};
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wire [`TRPBYTE] offset36 = {ir[`BYTE3],ir[`BYTE4],ir[`BYTE5]};
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// Choose the indexing register
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reg [`TRPBYTE] ndxreg;
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always_comb
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if (bitsPerByte==8)
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case(ndxbyte[6:5])
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2'b00: ndxreg <= xr;
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2'b01: ndxreg <= yr;
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2'b10: ndxreg <= {usppg,8'h00} + usp;
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2'b11: ndxreg <= ssp;
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endcase
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else if (bitsPerByte==12)
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case(ndxbyte[10:9])
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2'b00: ndxreg <= xr;
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2'b01: ndxreg <= yr;
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2'b10: ndxreg <= {usppg,8'h00} + usp;
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2'b11: ndxreg <= ssp;
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endcase
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reg [`TRPBYTE] NdxAddr;
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always_comb
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if (bitsPerByte==8)
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casez({isOuterIndexed,ndxbyte})
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9'b00???????: NdxAddr <= ndxreg + {{19{ndxbyte[BPB-4]}},ndxbyte[BPB-4:0]};
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9'b01???0000: NdxAddr <= ndxreg;
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9'b01???0001: NdxAddr <= ndxreg;
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9'b01???0010: NdxAddr <= ndxreg - 2'd1;
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9'b01???0011: NdxAddr <= ndxreg - 2'd2;
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| 282 |
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9'b01???0100: NdxAddr <= ndxreg;
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| 283 |
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9'b01???0101: NdxAddr <= ndxreg + {{BPB*2{accb[BPBM1]}},accb};
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| 284 |
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9'b01???0110: NdxAddr <= ndxreg + {{BPB*2{acca[BPBM1]}},acca};
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| 285 |
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9'b01???1000: NdxAddr <= ndxreg + offset12;
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9'b01???1001: NdxAddr <= ndxreg + offset24;
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9'b01???1010: NdxAddr <= ndxreg + offset36;
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9'b01???1011: NdxAddr <= ndxreg + {acca,accb};
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|
|
9'b01???1100: NdxAddr <= pc + offset12 + 3'd3;
|
| 290 |
|
|
9'b01???1101: NdxAddr <= pc + offset24 + 3'd4;
|
| 291 |
|
|
9'b01???1110: NdxAddr <= pc + offset36 + 3'd5;
|
| 292 |
|
|
9'b01??01111: NdxAddr <= isFar ? offset36 : offset24;
|
| 293 |
|
|
9'b01??11111: NdxAddr <= offset24;
|
| 294 |
|
|
9'b10???????: NdxAddr <= {{11{ndxbyte[BPB-4]}},ndxbyte[BPB-4:0]};
|
| 295 |
|
|
9'b11???0000: NdxAddr <= 24'd0;
|
| 296 |
|
|
9'b11???0001: NdxAddr <= 24'd0;
|
| 297 |
|
|
9'b11???0010: NdxAddr <= 24'd0;
|
| 298 |
|
|
9'b11???0011: NdxAddr <= 24'd0;
|
| 299 |
|
|
9'b11???0100: NdxAddr <= 24'd0;
|
| 300 |
|
|
9'b11???0101: NdxAddr <= {{BPB*2{accb[BPBM1]}},accb};
|
| 301 |
|
|
9'b11???0110: NdxAddr <= {{BPB*2{acca[BPBM1]}},acca};
|
| 302 |
|
|
9'b11???1000: NdxAddr <= offset12;
|
| 303 |
|
|
9'b11???1001: NdxAddr <= offset24;
|
| 304 |
|
|
9'b11???1010: NdxAddr <= offset36;
|
| 305 |
|
|
9'b11???1011: NdxAddr <= {acca,accb};
|
| 306 |
|
|
9'b11???1100: NdxAddr <= pc + offset12 + 3'd3;
|
| 307 |
|
|
9'b11???1101: NdxAddr <= pc + offset24 + 3'd4;
|
| 308 |
|
|
9'b11???1110: NdxAddr <= pc + offset36 + 3'd5;
|
| 309 |
|
|
9'b11??01111: NdxAddr <= isFar ? offset36 : offset24;
|
| 310 |
|
|
9'b11??11111: NdxAddr <= offset24;
|
| 311 |
|
|
default: NdxAddr <= 24'hFFFFFF;
|
| 312 |
|
|
endcase
|
| 313 |
|
|
else if (bitsPerByte==12)
|
| 314 |
|
|
casez({isOuterIndexed,ndxbyte})
|
| 315 |
|
|
13'b00???????????: NdxAddr <= ndxreg + {{27{ndxbyte[BPB-4]}},ndxbyte[BPB-4:0]};
|
| 316 |
|
|
13'b01???00000000: NdxAddr <= ndxreg;
|
| 317 |
|
|
13'b01???00000001: NdxAddr <= ndxreg;
|
| 318 |
|
|
13'b01???00000010: NdxAddr <= ndxreg - 2'd1;
|
| 319 |
|
|
13'b01???00010010: NdxAddr <= ndxreg - 2'd2;
|
| 320 |
|
|
13'b01???00100010: NdxAddr <= ndxreg - 2'd3;
|
| 321 |
|
|
13'b01???00000011: NdxAddr <= ndxreg - 2'd2;
|
| 322 |
|
|
13'b01???00000100: NdxAddr <= ndxreg;
|
| 323 |
|
|
13'b01???00000101: NdxAddr <= ndxreg + {{BPB*2{accb[BPBM1]}},accb};
|
| 324 |
|
|
13'b01???00000110: NdxAddr <= ndxreg + {{BPB*2{acca[BPBM1]}},acca};
|
| 325 |
|
|
13'b01???00001000: NdxAddr <= ndxreg + offset12;
|
| 326 |
|
|
13'b01???00001001: NdxAddr <= ndxreg + offset24;
|
| 327 |
|
|
13'b01???00001010: NdxAddr <= ndxreg + offset36;
|
| 328 |
|
|
13'b01???00001011: NdxAddr <= ndxreg + {acca,accb};
|
| 329 |
|
|
13'b01???00001100: NdxAddr <= pc + offset12 + 3'd3;
|
| 330 |
|
|
13'b01???00001101: NdxAddr <= pc + offset24 + 3'd4;
|
| 331 |
|
|
13'b01???00001110: NdxAddr <= pc + offset36 + 3'd5;
|
| 332 |
|
|
13'b01??000001111: NdxAddr <= isFar ? offset36 : offset24;
|
| 333 |
|
|
13'b01??100001111: NdxAddr <= offset24;
|
| 334 |
|
|
13'b01???10000000: NdxAddr <= 24'd0;
|
| 335 |
|
|
13'b01???10000001: NdxAddr <= 24'd0;
|
| 336 |
|
|
13'b01???10000010: NdxAddr <= 24'd0;
|
| 337 |
|
|
13'b01???10000011: NdxAddr <= 24'd0;
|
| 338 |
|
|
13'b01???10000100: NdxAddr <= 24'd0;
|
| 339 |
|
|
13'b01???10000101: NdxAddr <= {{BPB*2{accb[BPBM1]}},accb};
|
| 340 |
|
|
13'b01???10000110: NdxAddr <= {{BPB*2{acca[BPBM1]}},acca};
|
| 341 |
|
|
13'b01???10001000: NdxAddr <= offset12;
|
| 342 |
|
|
13'b01???10001001: NdxAddr <= offset24;
|
| 343 |
|
|
13'b01???10001010: NdxAddr <= offset24;
|
| 344 |
|
|
13'b01???10001011: NdxAddr <= {acca,accb};
|
| 345 |
|
|
13'b01???10001100: NdxAddr <= pc + offset12 + 3'd3;
|
| 346 |
|
|
13'b01???10001101: NdxAddr <= pc + offset24 + 3'd4;
|
| 347 |
|
|
13'b01???10001110: NdxAddr <= pc + offset36 + 3'd5;
|
| 348 |
|
|
13'b01??010001111: NdxAddr <= isFar ? offset36 : offset24;
|
| 349 |
|
|
13'b01??110001111: NdxAddr <= offset24;
|
| 350 |
|
|
13'b10???????????: NdxAddr <= {{15{ndxbyte[BPB-4]}},ndxbyte[BPB-4:0]};
|
| 351 |
|
|
13'b11???00000000: NdxAddr <= 24'd0;
|
| 352 |
|
|
13'b11???00000001: NdxAddr <= 24'd0;
|
| 353 |
|
|
13'b11???00000010: NdxAddr <= 24'd0;
|
| 354 |
|
|
13'b11???00000011: NdxAddr <= 24'd0;
|
| 355 |
|
|
13'b11???00000100: NdxAddr <= 24'd0;
|
| 356 |
|
|
13'b11???00000101: NdxAddr <= {{BPB*2{accb[BPBM1]}},accb};
|
| 357 |
|
|
13'b11???00000110: NdxAddr <= {{BPB*2{acca[BPBM1]}},acca};
|
| 358 |
|
|
13'b11???00001000: NdxAddr <= offset12;
|
| 359 |
|
|
13'b11???00001001: NdxAddr <= offset24;
|
| 360 |
|
|
13'b11???00001010: NdxAddr <= offset36;
|
| 361 |
|
|
13'b11???00001011: NdxAddr <= {acca,accb};
|
| 362 |
|
|
13'b11???00001100: NdxAddr <= pc + offset12 + 3'd3;
|
| 363 |
|
|
13'b11???00001101: NdxAddr <= pc + offset24 + 3'd4;
|
| 364 |
|
|
13'b11???00001110: NdxAddr <= pc + offset36 + 3'd5;
|
| 365 |
|
|
13'b11??000001111: NdxAddr <= isFar ? offset36 : offset24;
|
| 366 |
|
|
13'b11??000011111: NdxAddr <= offset24;
|
| 367 |
|
|
default: NdxAddr <= 24'hFFFFFF;
|
| 368 |
|
|
endcase
|
| 369 |
|
|
|
| 370 |
|
|
// Compute instruction length depending on indexing byte
|
| 371 |
|
|
reg [2:0] insnsz;
|
| 372 |
|
|
always_comb
|
| 373 |
|
|
if (bitsPerByte==8)
|
| 374 |
|
|
casez(ndxbyte)
|
| 375 |
|
|
8'b0???????: insnsz <= 4'h2;
|
| 376 |
|
|
8'b1??00000: insnsz <= 4'h2;
|
| 377 |
|
|
8'b1??00001: insnsz <= 4'h2;
|
| 378 |
|
|
8'b1??00010: insnsz <= 4'h2;
|
| 379 |
|
|
8'b1??00011: insnsz <= 4'h2;
|
| 380 |
|
|
8'b1??00100: insnsz <= 4'h2;
|
| 381 |
|
|
8'b1??00101: insnsz <= 4'h2;
|
| 382 |
|
|
8'b1??00110: insnsz <= 4'h2;
|
| 383 |
|
|
8'b1??01000: insnsz <= 4'h3;
|
| 384 |
|
|
8'b1??01001: insnsz <= 4'h4;
|
| 385 |
|
|
8'b1??01010: insnsz <= 4'h5;
|
| 386 |
|
|
8'b1??01011: insnsz <= 4'h2;
|
| 387 |
|
|
8'b1??01100: insnsz <= 4'h3;
|
| 388 |
|
|
8'b1??01101: insnsz <= 4'h4;
|
| 389 |
|
|
8'b1??01110: insnsz <= 4'h5;
|
| 390 |
|
|
8'b1??01111: insnsz <= isFar ? 4'h5 : 4'h4;
|
| 391 |
|
|
8'b1??11111: insnsz <= 4'h4;
|
| 392 |
|
|
default: insnsz <= 4'h2;
|
| 393 |
|
|
endcase
|
| 394 |
|
|
else if (bitsPerByte==12)
|
| 395 |
|
|
casez(ndxbyte)
|
| 396 |
|
|
12'b0???????????: insnsz <= 4'h2;
|
| 397 |
|
|
12'b1???00000000: insnsz <= 4'h2;
|
| 398 |
|
|
12'b1???00000001: insnsz <= 4'h2;
|
| 399 |
|
|
12'b1???00000010: insnsz <= 4'h2;
|
| 400 |
|
|
12'b1???00000011: insnsz <= 4'h2;
|
| 401 |
|
|
12'b1???00000100: insnsz <= 4'h2;
|
| 402 |
|
|
12'b1???00000101: insnsz <= 4'h2;
|
| 403 |
|
|
12'b1???00000110: insnsz <= 4'h2;
|
| 404 |
|
|
12'b1???00001000: insnsz <= 4'h3;
|
| 405 |
|
|
12'b1???00001001: insnsz <= 4'h4;
|
| 406 |
|
|
12'b1???00001010: insnsz <= 4'h5;
|
| 407 |
|
|
12'b1???00001011: insnsz <= 4'h2;
|
| 408 |
|
|
12'b1???00001100: insnsz <= 4'h3;
|
| 409 |
|
|
12'b1???00001101: insnsz <= 4'h4;
|
| 410 |
|
|
12'b1???00001110: insnsz <= 4'h5;
|
| 411 |
|
|
12'b1??000001111: insnsz <= isFar ? 4'h5 : 4'h4;
|
| 412 |
|
|
12'b1??000011111: insnsz <= 4'h4;
|
| 413 |
|
|
default: insnsz <= 4'h2;
|
| 414 |
|
|
endcase
|
| 415 |
|
|
|
| 416 |
|
|
// Source registers for transfer or exchange instructions.
|
| 417 |
|
|
reg [`DBLBYTE] src1,src2;
|
| 418 |
|
|
always_comb
|
| 419 |
|
|
case(ir[bitsPerByte+7:bitsPerByte+4])
|
| 420 |
|
|
4'b0000: src1 <= {acca[`LOBYTE],accb[`LOBYTE]};
|
| 421 |
|
|
4'b0001: src1 <= xr;
|
| 422 |
|
|
4'b0010: src1 <= yr;
|
| 423 |
|
|
4'b0011: src1 <= usp;
|
| 424 |
|
|
4'b0100: src1 <= ssp;
|
| 425 |
|
|
4'b0101: src1 <= pcp2;
|
| 426 |
|
|
4'b1000: src1 <= acca[`LOBYTE];
|
| 427 |
|
|
4'b1001: src1 <= accb[`LOBYTE];
|
| 428 |
|
|
4'b1010: src1 <= ccr;
|
| 429 |
|
|
4'b1011: src1 <= dpr;
|
| 430 |
|
|
4'b1100: src1 <= usppg;
|
| 431 |
|
|
4'b1101: src1 <= 24'h0000;
|
| 432 |
|
|
4'b1110: src1 <= 24'h0000;
|
| 433 |
|
|
4'b1111: src1 <= 24'h0000;
|
| 434 |
|
|
default: src1 <= 24'h0000;
|
| 435 |
|
|
endcase
|
| 436 |
|
|
always_comb
|
| 437 |
|
|
case(ir[bitsPerByte+3:bitsPerByte])
|
| 438 |
|
|
4'b0000: src2 <= {acca[`LOBYTE],accb[`LOBYTE]};
|
| 439 |
|
|
4'b0001: src2 <= xr;
|
| 440 |
|
|
4'b0010: src2 <= yr;
|
| 441 |
|
|
4'b0011: src2 <= usp;
|
| 442 |
|
|
4'b0100: src2 <= ssp;
|
| 443 |
|
|
4'b0101: src2 <= pcp2;
|
| 444 |
|
|
4'b1000: src2 <= acca[`LOBYTE];
|
| 445 |
|
|
4'b1001: src2 <= accb[`LOBYTE];
|
| 446 |
|
|
4'b1010: src2 <= ccr;
|
| 447 |
|
|
4'b1011: src2 <= dpr;
|
| 448 |
|
|
4'b1100: src2 <= usppg;
|
| 449 |
|
|
4'b1101: src2 <= 24'h0000;
|
| 450 |
|
|
4'b1110: src2 <= 24'h0000;
|
| 451 |
|
|
4'b1111: src2 <= 24'h0000;
|
| 452 |
|
|
default: src2 <= 24'h0000;
|
| 453 |
|
|
endcase
|
| 454 |
|
|
|
| 455 |
|
|
wire isAcca = ir12==`NEGA || ir12==`COMA || ir12==`LSRA || ir12==`RORA || ir12==`ASRA || ir12==`ASLA ||
|
| 456 |
|
|
ir12==`ROLA || ir12==`DECA || ir12==`INCA || ir12==`TSTA || ir12==`CLRA ||
|
| 457 |
|
|
ir12==`SUBA_IMM || ir12==`CMPA_IMM || ir12==`SBCA_IMM || ir12==`ANDA_IMM || ir12==`BITA_IMM ||
|
| 458 |
|
|
ir12==`LDA_IMM || ir12==`EORA_IMM || ir12==`ADCA_IMM || ir12==`ORA_IMM || ir12==`ADDA_IMM ||
|
| 459 |
|
|
ir12==`SUBA_DP || ir12==`CMPA_DP || ir12==`SBCA_DP || ir12==`ANDA_DP || ir12==`BITA_DP ||
|
| 460 |
|
|
ir12==`LDA_DP || ir12==`EORA_DP || ir12==`ADCA_DP || ir12==`ORA_DP || ir12==`ADDA_DP ||
|
| 461 |
|
|
ir12==`SUBA_NDX || ir12==`CMPA_NDX || ir12==`SBCA_NDX || ir12==`ANDA_NDX || ir12==`BITA_NDX ||
|
| 462 |
|
|
ir12==`LDA_NDX || ir12==`EORA_NDX || ir12==`ADCA_NDX || ir12==`ORA_NDX || ir12==`ADDA_NDX ||
|
| 463 |
|
|
ir12==`SUBA_EXT || ir12==`CMPA_EXT || ir12==`SBCA_EXT || ir12==`ANDA_EXT || ir12==`BITA_EXT ||
|
| 464 |
|
|
ir12==`LDA_EXT || ir12==`EORA_EXT || ir12==`ADCA_EXT || ir12==`ORA_EXT || ir12==`ADDA_EXT
|
| 465 |
|
|
;
|
| 466 |
|
|
|
| 467 |
|
|
wire [`DBLBYTE] acc = isAcca ? acca : accb;
|
| 468 |
|
|
|
| 469 |
|
|
wire [`DBLBYTE] sum12 = src1 + src2;
|
| 470 |
|
|
|
| 471 |
|
|
always_ff @(posedge clk_i)
|
| 472 |
|
|
if (state==DECODE) begin
|
| 473 |
|
|
isStore <= ir12==`STA_DP || ir12==`STB_DP || ir12==`STD_DP || ir12==`STX_DP || ir12==`STY_DP || ir12==`STU_DP || ir12==`STS_DP ||
|
| 474 |
|
|
ir12==`STA_NDX || ir12==`STB_NDX || ir12==`STD_NDX || ir12==`STX_NDX || ir12==`STY_NDX || ir12==`STU_NDX || ir12==`STS_NDX ||
|
| 475 |
|
|
ir12==`STA_EXT || ir12==`STB_EXT || ir12==`STD_EXT || ir12==`STX_EXT || ir12==`STY_EXT || ir12==`STU_EXT || ir12==`STS_EXT
|
| 476 |
|
|
;
|
| 477 |
|
|
isPULU <= ir12==`PULU;
|
| 478 |
|
|
isPULS <= ir12==`PULS;
|
| 479 |
|
|
isPSHS <= ir12==`PSHS;
|
| 480 |
|
|
isPSHU <= ir12==`PSHU;
|
| 481 |
|
|
isRTI <= ir12==`RTI;
|
| 482 |
|
|
isRTS <= ir12==`RTS;
|
| 483 |
|
|
isRTF <= ir12==`RTF;
|
| 484 |
|
|
isLEA <= ir12==`LEAX_NDX || ir12==`LEAY_NDX || ir12==`LEAU_NDX || ir12==`LEAS_NDX;
|
| 485 |
|
|
isRMW <= isRMW1;
|
| 486 |
|
|
end
|
| 487 |
|
|
|
| 488 |
|
|
wire hit0, hit1;
|
| 489 |
|
|
wire ihit = hit0 & hit1;
|
| 490 |
|
|
reg rhit0;
|
| 491 |
|
|
|
| 492 |
|
|
assign lic_o = (state==CALC && !isRMW) ||
|
| 493 |
|
|
(state==DECODE && (
|
| 494 |
|
|
ir12==`NOP || ir12==`ORCC || ir12==`ANDCC || ir12==`DAA || ir12==`LDMD || ir12==`TFR || ir12==`EXG ||
|
| 495 |
|
|
ir12==`NEGA || ir12==`COMA || ir12==`LSRA || ir12==`RORA || ir12==`ASRA || ir12==`ROLA || ir12==`DECA || ir12==`INCA || ir12==`TSTA || ir12==`CLRA ||
|
| 496 |
|
|
ir12==`NEGB || ir12==`COMB || ir12==`LSRB || ir12==`RORB || ir12==`ASRB || ir12==`ROLB || ir12==`DECB || ir12==`INCB || ir12==`TSTB || ir12==`CLRB ||
|
| 497 |
|
|
ir12==`ASLD || ir12==`TSTD || //ir12==`ADDR ||
|
| 498 |
|
|
ir12==`SUBA_IMM || ir12==`CMPA_IMM || ir12==`SBCA_IMM || ir12==`ANDA_IMM || ir12==`BITA_IMM || ir12==`LDA_IMM || ir12==`EORA_IMM || ir12==`ADCA_IMM || ir12==`ORA_IMM || ir12==`ADDA_IMM ||
|
| 499 |
|
|
ir12==`SUBB_IMM || ir12==`CMPB_IMM || ir12==`SBCB_IMM || ir12==`ANDB_IMM || ir12==`BITB_IMM || ir12==`LDB_IMM || ir12==`EORB_IMM || ir12==`ADCB_IMM || ir12==`ORB_IMM || ir12==`ADDB_IMM ||
|
| 500 |
|
|
ir12==`ANDD_IMM || ir12==`ADDD_IMM || ir12==`ADCD_IMM || ir12==`SUBD_IMM || ir12==`SBCD_IMM || ir12==`LDD_IMM ||
|
| 501 |
|
|
ir12==`LDQ_IMM || ir12==`CMPD_IMM || ir12==`CMPX_IMM || ir12==`CMPY_IMM || ir12==`CMPU_IMM || ir12==`CMPS_IMM ||
|
| 502 |
|
|
ir12==`BEQ || ir12==`BNE || ir12==`BMI || ir12==`BPL || ir12==`BVS || ir12==`BVC || ir12==`BRA || ir12==`BRN ||
|
| 503 |
|
|
ir12==`BHI || ir12==`BLS || ir12==`BHS || ir12==`BLO ||
|
| 504 |
|
|
ir12==`BGT || ir12==`BGE || ir12==`BLT || ir12==`BLE ||
|
| 505 |
|
|
ir12==`LBEQ || ir12==`LBNE || ir12==`LBMI || ir12==`LBPL || ir12==`LBVS || ir12==`LBVC || ir12==`LBRA || ir12==`LBRN ||
|
| 506 |
|
|
ir12==`LBHI || ir12==`LBLS || ir12==`LBHS || ir12==`LBLO ||
|
| 507 |
|
|
ir12==`LBGT || ir12==`LBGE || ir12==`LBLT || ir12==`LBLE
|
| 508 |
|
|
)
|
| 509 |
|
|
) ||
|
| 510 |
|
|
(state==STORE2 && (
|
| 511 |
|
|
(store_what==`SW_ACCQ3124 && wadr[1:0]==2'b00) ||
|
| 512 |
|
|
(store_what==`SW_ACCQ70) ||
|
| 513 |
|
|
(store_what==`SW_ACCA && !(isINT || isPSHS || isPSHU)) ||
|
| 514 |
|
|
(store_what==`SW_ACCB && !(isINT || isPSHS || isPSHU)) ||
|
| 515 |
|
|
(store_what==`SW_ACCDH && wadr[1:0]!=2'b11) ||
|
| 516 |
|
|
(store_what==`SW_ACCDL) ||
|
| 517 |
|
|
(store_what==`SW_X3124 && wadr[1:0]==2'b00 && !(isINT || isPSHS || isPSHU)) ||
|
| 518 |
|
|
(store_what==`SW_XL && !(isINT || isPSHS || isPSHU)) ||
|
| 519 |
|
|
(store_what==`SW_YL && !(isINT || isPSHS || isPSHU)) ||
|
| 520 |
|
|
(store_what==`SW_USPL && !(isINT || isPSHS || isPSHU)) ||
|
| 521 |
|
|
(store_what==`SW_SSPL && !(isINT || isPSHS || isPSHU)) ||
|
| 522 |
|
|
(store_what==`SW_PCL && !(isINT || isPSHS || isPSHU) && !(ir12==`JSR_NDX && isIndirect)) ||
|
| 523 |
|
|
(store_what==`SW_ACCA70 && !(isINT || isPSHS || isPSHU)) ||
|
| 524 |
|
|
(store_what==`SW_ACCB70 && !(isINT || isPSHS || isPSHU))
|
| 525 |
|
|
)) ||
|
| 526 |
|
|
(state==PUSH2 && ir[`HIBYTE]==12'h000 && !isINT) ||
|
| 527 |
|
|
(state==PULL1 && ir[`HIBYTE]==12'h000) ||
|
| 528 |
|
|
(state==OUTER_INDEXING2 && isLEA) ||
|
| 529 |
|
|
(state==LOAD2 &&
|
| 530 |
|
|
(load_what==`LW_ACCA && !(isRTI || isPULU || isPULS)) ||
|
| 531 |
|
|
(load_what==`LW_ACCB && !(isRTI || isPULU || isPULS)) ||
|
| 532 |
|
|
(load_what==`LW_DPR && !(isRTI || isPULU || isPULS)) ||
|
| 533 |
|
|
(load_what==`LW_XL && !(isRTI || isPULU || isPULS)) ||
|
| 534 |
|
|
(load_what==`LW_YL && !(isRTI || isPULU || isPULS)) ||
|
| 535 |
|
|
(load_what==`LW_USPL && !(isRTI || isPULU || isPULS)) ||
|
| 536 |
|
|
(load_what==`LW_SSPL && !(isRTI || isPULU || isPULS)) ||
|
| 537 |
|
|
(load_what==`LW_PCL) ||
|
| 538 |
|
|
(load_what==`LW_IAL && !isOuterIndexed && isLEA) ||
|
| 539 |
|
|
(load_what==`LW_IA3124 && radr[1:0]==2'b00 && !isOuterIndexed && isLEA)
|
| 540 |
|
|
)
|
| 541 |
|
|
;
|
| 542 |
|
|
|
| 543 |
|
|
wire lock_bus = load_what==`LW_XH || load_what==`LW_YH || load_what==`LW_USPH || load_what==`LW_SSPH ||
|
| 544 |
|
|
load_what==`LW_PCH || load_what==`LW_BH || load_what==`LW_IAH || load_what==`LW_PC3124 ||
|
| 545 |
|
|
load_what==`LW_IA3124 || load_what==`LW_B3124 ||
|
| 546 |
|
|
load_what==`LW_X3124 || load_what==`LW_Y3124 || load_what==`LW_USP3124 || load_what==`LW_SSP3124 ||
|
| 547 |
|
|
isRMW ||
|
| 548 |
|
|
store_what==`SW_ACCDH || store_what==`SW_XH || store_what==`SW_YH || store_what==`SW_USPH || store_what==`SW_SSPH ||
|
| 549 |
|
|
store_what==`SW_PCH || store_what==`SW_PC3124 || store_what==`SW_ACCQ3124 ||
|
| 550 |
|
|
store_what==`SW_X3124 || store_what==`SW_Y3124 || store_what==`SW_USP3124 || store_what==`SW_SSP3124
|
| 551 |
|
|
;
|
| 552 |
|
|
|
| 553 |
|
|
wire isPrefix = ir12==`PG2 || ir12==`PG3 || ir12==`OUTER;
|
| 554 |
|
|
|
| 555 |
|
|
reg rty;
|
| 556 |
|
|
reg [5:0] waitcnt;
|
| 557 |
|
|
reg [3:0] iccnt;
|
| 558 |
|
|
reg [bitsPerByte-1:0] icbuf [0:15];
|
| 559 |
|
|
reg [bitsPerByte*16-1:0] icbuf2;
|
| 560 |
|
|
reg [15:0] outstanding; // Outstanding async read cycles.
|
| 561 |
|
|
integer n4;
|
| 562 |
|
|
|
| 563 |
|
|
rf6809_icachemem u1
|
| 564 |
|
|
(
|
| 565 |
|
|
.wclk(clk_i),
|
| 566 |
|
|
.wce(1'b1),
|
| 567 |
|
|
.wr(state==ICACHE6),
|
| 568 |
|
|
.wa(icwa[11:0]),
|
| 569 |
|
|
.i(icbuf2),
|
| 570 |
|
|
.rclk(~clk_i),
|
| 571 |
|
|
.rce(1'b1),
|
| 572 |
|
|
.pc(pc[11:0]),
|
| 573 |
|
|
.insn(insn)
|
| 574 |
|
|
);
|
| 575 |
|
|
|
| 576 |
|
|
rf6809_itagmem u2
|
| 577 |
|
|
(
|
| 578 |
|
|
.wclk(clk_i),
|
| 579 |
|
|
.wce(1'b1),
|
| 580 |
|
|
.wr(state==ICACHE6),
|
| 581 |
|
|
.wa(icwa[`TRPBYTE]),
|
| 582 |
|
|
.invalidate(ic_invalidate),
|
| 583 |
|
|
.rclk(~clk_i),
|
| 584 |
|
|
.rce(1'b1),
|
| 585 |
|
|
.pc(pc),
|
| 586 |
|
|
.hit0(hit0),
|
| 587 |
|
|
.hit1(hit1)
|
| 588 |
|
|
);
|
| 589 |
|
|
|
| 590 |
|
|
// For asynchronous reads,
|
| 591 |
|
|
// The read response might come back in any order (the packets could loop
|
| 592 |
|
|
// around in the network.
|
| 593 |
|
|
// We need to buffer and reorder the response correctly.
|
| 594 |
|
|
|
| 595 |
|
|
integer n3;
|
| 596 |
|
|
always_ff @(posedge clk_i)
|
| 597 |
|
|
if (rst_i) begin
|
| 598 |
|
|
icgot <= 16'h0;
|
| 599 |
|
|
for (n3 = 0; n3 < 16; n3 = n3 + 1)
|
| 600 |
|
|
icbuf[n3] <= {bitsPerByte{1'b0}};
|
| 601 |
|
|
end
|
| 602 |
|
|
else begin
|
| 603 |
|
|
if (state==ICACHE1)
|
| 604 |
|
|
icgot <= 16'h0;
|
| 605 |
|
|
`ifdef SUPPORT_AREAD
|
| 606 |
|
|
if (aack_i) begin
|
| 607 |
|
|
icgot[atag_i] <= 1'b1;
|
| 608 |
|
|
icbuf[atag_i] <= dati;
|
| 609 |
|
|
end
|
| 610 |
|
|
`else
|
| 611 |
|
|
if (ack_i) begin
|
| 612 |
|
|
icgot[adr_o[3:0]] <= 1'b1;
|
| 613 |
|
|
icbuf[adr_o[3:0]] <= dati;
|
| 614 |
|
|
end
|
| 615 |
|
|
`endif
|
| 616 |
|
|
end
|
| 617 |
|
|
|
| 618 |
|
|
genvar g;
|
| 619 |
|
|
generate begin : gIcin
|
| 620 |
|
|
for (g = 0; g < 16; g = g + 1)
|
| 621 |
|
|
always_comb
|
| 622 |
|
|
icbuf2[(g+1)*bitsPerByte-1:g*bitsPerByte] <= icbuf[g];
|
| 623 |
|
|
end
|
| 624 |
|
|
endgenerate
|
| 625 |
|
|
|
| 626 |
|
|
// Bus timeout counter
|
| 627 |
|
|
always_ff @(posedge clk_i)
|
| 628 |
|
|
if (rst_i) begin
|
| 629 |
|
|
btocnt <= 24'd0;
|
| 630 |
|
|
end
|
| 631 |
|
|
else begin
|
| 632 |
|
|
if (cyc_o & stb_o)
|
| 633 |
|
|
btocnt <= btocnt + 2'd1;
|
| 634 |
|
|
else
|
| 635 |
|
|
btocnt <= 24'd0;
|
| 636 |
|
|
end
|
| 637 |
|
|
always_comb
|
| 638 |
|
|
bto = btocnt >= 24'd10000;
|
| 639 |
|
|
|
| 640 |
|
|
// Count milliseconds
|
| 641 |
|
|
// Based on a count determined by the clock frequency
|
| 642 |
|
|
// 40MHz is assumed.
|
| 643 |
|
|
reg [23:0] ns_count; // The counter to get to 1ms
|
| 644 |
|
|
reg [35:0] ms_count; // Count of number of milliseconds
|
| 645 |
|
|
|
| 646 |
|
|
always_ff @(posedge clk_i)
|
| 647 |
|
|
if (rst_i) begin
|
| 648 |
|
|
ns_count <= 16'd0;
|
| 649 |
|
|
ms_count <= 36'd0;
|
| 650 |
|
|
end
|
| 651 |
|
|
else begin
|
| 652 |
|
|
ns_count <= ns_count + 2'd1;
|
| 653 |
|
|
if (ns_count>=24'd40000) begin
|
| 654 |
|
|
ns_count <= 24'h0;
|
| 655 |
|
|
ms_count <= ms_count + 2'd1;
|
| 656 |
|
|
end
|
| 657 |
|
|
end
|
| 658 |
|
|
|
| 659 |
|
|
`ifdef SUPPORT_CHECKPOINT
|
| 660 |
|
|
always_ff @(posedge clk_i)
|
| 661 |
|
|
if (rst_i)
|
| 662 |
|
|
chkpoint <= 12'h000;
|
| 663 |
|
|
else begin
|
| 664 |
|
|
if (ns_count==16'd40000) begin
|
| 665 |
|
|
if (ms_count[9:0]==10'h3FF)
|
| 666 |
|
|
chkpoint <= 12'hFFF;
|
| 667 |
|
|
end
|
| 668 |
|
|
if (state==STORE1 && (wadr=={{BPB*3-8{1'b1}},8'hE1}))
|
| 669 |
|
|
chkpoint <= 12'h000;
|
| 670 |
|
|
end
|
| 671 |
|
|
`endif
|
| 672 |
|
|
|
| 673 |
|
|
always_ff @(posedge clk_i)
|
| 674 |
|
|
tsc_latched <= tsc_i;
|
| 675 |
|
|
|
| 676 |
|
|
always_ff @(posedge clk_i)
|
| 677 |
|
|
nmi1 <= nmi_i;
|
| 678 |
|
|
always_ff @(posedge clk_i)
|
| 679 |
|
|
`ifdef SUPPORT_CHECKPOINT
|
| 680 |
|
|
if (ms_count[9:0]==10'h3FF && chkpoint!=12'h000)
|
| 681 |
|
|
nmi_edge <= 1'b1;
|
| 682 |
|
|
else
|
| 683 |
|
|
`endif
|
| 684 |
|
|
if (nmi_i & !nmi1)
|
| 685 |
|
|
nmi_edge <= 1'b1;
|
| 686 |
|
|
else if (state==DECODE && ir12==`INT)
|
| 687 |
|
|
nmi_edge <= 1'b0;
|
| 688 |
|
|
|
| 689 |
|
|
reg [9:0] rst_cnt;
|
| 690 |
|
|
|
| 691 |
|
|
always @(posedge clk_i)
|
| 692 |
|
|
if (rst_i) begin
|
| 693 |
|
|
wb_nack();
|
| 694 |
|
|
rty <= `FALSE;
|
| 695 |
|
|
rst_cnt <= {id,4'd0};
|
| 696 |
|
|
next_state(RESET);
|
| 697 |
|
|
sync_state <= `FALSE;
|
| 698 |
|
|
wait_state <= `FALSE;
|
| 699 |
|
|
md32 <= `FALSE;
|
| 700 |
|
|
ipg <= 2'b00;
|
| 701 |
|
|
isFar <= `FALSE;
|
| 702 |
|
|
isOuterIndexed <= `FALSE;
|
| 703 |
|
|
dpr <= 12'h000;
|
| 704 |
|
|
ibufadr <= {BPB*3{1'b0}};
|
| 705 |
|
|
// pc <= 24'hFFFFFE;
|
| 706 |
|
|
pc <= {{BPB*3-1{1'b1}},1'b0}; // FF...FE
|
| 707 |
|
|
ir <= {4{`NOP}};
|
| 708 |
|
|
ibuf <= {4{`NOP}};
|
| 709 |
|
|
im <= 1'b1;
|
| 710 |
|
|
firqim <= 1'b1;
|
| 711 |
|
|
nmi_armed <= `FALSE;
|
| 712 |
|
|
ic_invalidate <= `TRUE;
|
| 713 |
|
|
first_ifetch <= `TRUE;
|
| 714 |
|
|
acca <= 12'h0;
|
| 715 |
|
|
accb <= 12'h0;
|
| 716 |
|
|
accd <= 24'h0;
|
| 717 |
|
|
xr <= 24'h0;
|
| 718 |
|
|
yr <= 24'h0;
|
| 719 |
|
|
usp <= 24'h0;
|
| 720 |
|
|
ssp <= 24'h0;
|
| 721 |
|
|
if (halt_i) begin
|
| 722 |
|
|
ba_o <= 1'b1;
|
| 723 |
|
|
bs_o <= 1'b1;
|
| 724 |
|
|
end
|
| 725 |
|
|
else begin
|
| 726 |
|
|
ba_o <= 1'b0;
|
| 727 |
|
|
bs_o <= 1'b0;
|
| 728 |
|
|
end
|
| 729 |
|
|
outstanding <= 16'h0;
|
| 730 |
|
|
iccnt <= 4'h0;
|
| 731 |
|
|
end
|
| 732 |
|
|
else begin
|
| 733 |
|
|
|
| 734 |
|
|
// Release any bus lock during the last state of an instruction.
|
| 735 |
|
|
if (lic_o && ack_i && (state==STORE2 || state==LOAD2))
|
| 736 |
|
|
lock_o <= 1'b0;
|
| 737 |
|
|
|
| 738 |
|
|
case(state)
|
| 739 |
|
|
RESET:
|
| 740 |
|
|
if (rst_cnt==10'd0) begin
|
| 741 |
|
|
ic_invalidate <= `FALSE;
|
| 742 |
|
|
ba_o <= 1'b0;
|
| 743 |
|
|
bs_o <= 1'b0;
|
| 744 |
|
|
vect <= `RST_VECT;
|
| 745 |
|
|
radr <= `RST_VECT;
|
| 746 |
|
|
load_what <= `LW_PCH;
|
| 747 |
|
|
next_state(LOAD1);
|
| 748 |
|
|
end
|
| 749 |
|
|
else
|
| 750 |
|
|
rst_cnt <= rst_cnt - 2'd1;
|
| 751 |
|
|
|
| 752 |
|
|
IFETCH:
|
| 753 |
|
|
begin
|
| 754 |
|
|
tIfetch();
|
| 755 |
|
|
tWriteback();
|
| 756 |
|
|
end
|
| 757 |
|
|
DECODE: tDecode();
|
| 758 |
|
|
LOAD1: tLoad1();
|
| 759 |
|
|
LOAD2: tLoad2();
|
| 760 |
|
|
CALC: tExecute();
|
| 761 |
|
|
STORE1: tStore1();
|
| 762 |
|
|
STORE2: tStore2();
|
| 763 |
|
|
|
| 764 |
|
|
// ============================================================================
|
| 765 |
|
|
// ============================================================================
|
| 766 |
|
|
PUSH1:
|
| 767 |
|
|
begin
|
| 768 |
|
|
next_state(PUSH2);
|
| 769 |
|
|
if (isINT | isPSHS) begin
|
| 770 |
|
|
wadr <= (ssp - cnt);
|
| 771 |
|
|
ssp <= (ssp - cnt);
|
| 772 |
|
|
end
|
| 773 |
|
|
else begin // PSHU
|
| 774 |
|
|
wadr <= ({usppg,8'h00} + usp - cnt);
|
| 775 |
|
|
usp <= (usp - cnt);
|
| 776 |
|
|
end
|
| 777 |
|
|
end
|
| 778 |
|
|
PUSH2:
|
| 779 |
|
|
begin
|
| 780 |
|
|
next_state(STORE1);
|
| 781 |
|
|
if (ir[bitsPerByte]) begin
|
| 782 |
|
|
store_what <= `SW_CCR;
|
| 783 |
|
|
ir[bitsPerByte] <= 1'b0;
|
| 784 |
|
|
end
|
| 785 |
|
|
else if (ir[bitsPerByte+1]) begin
|
| 786 |
|
|
store_what <= `SW_ACCA;
|
| 787 |
|
|
ir[bitsPerByte+1] <= 1'b0;
|
| 788 |
|
|
end
|
| 789 |
|
|
else if (ir[bitsPerByte+2]) begin
|
| 790 |
|
|
store_what <= `SW_ACCB;
|
| 791 |
|
|
ir[bitsPerByte+2] <= 1'b0;
|
| 792 |
|
|
end
|
| 793 |
|
|
else if (ir[bitsPerByte+3]) begin
|
| 794 |
|
|
store_what <= `SW_DPR;
|
| 795 |
|
|
ir[bitsPerByte+3] <= 1'b0;
|
| 796 |
|
|
end
|
| 797 |
|
|
else if (ir[bitsPerByte+4]) begin
|
| 798 |
|
|
store_what <= `SW_XH;
|
| 799 |
|
|
ir[bitsPerByte+4] <= 1'b0;
|
| 800 |
|
|
end
|
| 801 |
|
|
else if (ir[bitsPerByte+5]) begin
|
| 802 |
|
|
store_what <= `SW_YH;
|
| 803 |
|
|
ir[bitsPerByte+5] <= 1'b0;
|
| 804 |
|
|
end
|
| 805 |
|
|
else if (ir[bitsPerByte+6]) begin
|
| 806 |
|
|
if (isINT | isPSHS)
|
| 807 |
|
|
store_what <= `SW_USPH;
|
| 808 |
|
|
else
|
| 809 |
|
|
store_what <= `SW_SSPH;
|
| 810 |
|
|
ir[bitsPerByte+6] <= 1'b0;
|
| 811 |
|
|
end
|
| 812 |
|
|
else if (ir[bitsPerByte+7]) begin
|
| 813 |
|
|
store_what <= isFar ? `SW_PC2316 : `SW_PCH;
|
| 814 |
|
|
ir[bitsPerByte+7] <= 1'b0;
|
| 815 |
|
|
end
|
| 816 |
|
|
else begin
|
| 817 |
|
|
if (isINT) begin
|
| 818 |
|
|
radr <= vect;
|
| 819 |
|
|
if (vec_i != 24'h0) begin
|
| 820 |
|
|
$display("vector: %h", vec_i);
|
| 821 |
|
|
pc <= vec_i;
|
| 822 |
|
|
next_state(IFETCH);
|
| 823 |
|
|
end
|
| 824 |
|
|
else begin
|
| 825 |
|
|
pc[`BYTE3] <= 8'h00;
|
| 826 |
|
|
load_what <= `LW_PCH;
|
| 827 |
|
|
next_state(LOAD1);
|
| 828 |
|
|
end
|
| 829 |
|
|
end
|
| 830 |
|
|
else
|
| 831 |
|
|
next_state(IFETCH);
|
| 832 |
|
|
end
|
| 833 |
|
|
end
|
| 834 |
|
|
PULL1:
|
| 835 |
|
|
begin
|
| 836 |
|
|
next_state(LOAD1);
|
| 837 |
|
|
if (ir[bitsPerByte]) begin
|
| 838 |
|
|
load_what <= `LW_CCR;
|
| 839 |
|
|
ir[bitsPerByte] <= 1'b0;
|
| 840 |
|
|
end
|
| 841 |
|
|
else if (ir[bitsPerByte+1]) begin
|
| 842 |
|
|
load_what <= `LW_ACCA;
|
| 843 |
|
|
ir[bitsPerByte+1] <= 1'b0;
|
| 844 |
|
|
end
|
| 845 |
|
|
else if (ir[bitsPerByte+2]) begin
|
| 846 |
|
|
load_what <= `LW_ACCB;
|
| 847 |
|
|
ir[bitsPerByte+2] <= 1'b0;
|
| 848 |
|
|
end
|
| 849 |
|
|
else if (ir[bitsPerByte+3]) begin
|
| 850 |
|
|
load_what <= `LW_DPR;
|
| 851 |
|
|
ir[bitsPerByte+3] <= 1'b0;
|
| 852 |
|
|
end
|
| 853 |
|
|
else if (ir[bitsPerByte+4]) begin
|
| 854 |
|
|
load_what <= `LW_XH;
|
| 855 |
|
|
ir[bitsPerByte+4] <= 1'b0;
|
| 856 |
|
|
end
|
| 857 |
|
|
else if (ir[bitsPerByte+5]) begin
|
| 858 |
|
|
load_what <= `LW_YH;
|
| 859 |
|
|
ir[bitsPerByte+5] <= 1'b0;
|
| 860 |
|
|
end
|
| 861 |
|
|
else if (ir[bitsPerByte+6]) begin
|
| 862 |
|
|
if (ir12==`PULU)
|
| 863 |
|
|
load_what <= `LW_SSPH;
|
| 864 |
|
|
else
|
| 865 |
|
|
load_what <= `LW_USPH;
|
| 866 |
|
|
ir[bitsPerByte+6] <= 1'b0;
|
| 867 |
|
|
end
|
| 868 |
|
|
else if (ir[bitsPerByte+7]) begin
|
| 869 |
|
|
load_what <= isFar ? `LW_PC2316 : `LW_PCH;
|
| 870 |
|
|
ir[bitsPerByte+7] <= 1'b0;
|
| 871 |
|
|
end
|
| 872 |
|
|
else
|
| 873 |
|
|
next_state(IFETCH);
|
| 874 |
|
|
end
|
| 875 |
|
|
|
| 876 |
|
|
// ----------------------------------------------------------------------------
|
| 877 |
|
|
// Outer Indexing Support
|
| 878 |
|
|
// ----------------------------------------------------------------------------
|
| 879 |
|
|
OUTER_INDEXING:
|
| 880 |
|
|
begin
|
| 881 |
|
|
if (bitsPerByte==8) begin
|
| 882 |
|
|
casex(ndxbyte)
|
| 883 |
|
|
8'b0xxxxxxx: radr <= radr + ndxreg;
|
| 884 |
|
|
8'b1xxx0000:
|
| 885 |
|
|
begin
|
| 886 |
|
|
radr <= radr + ndxreg;
|
| 887 |
|
|
case(ndxbyte[6:5])
|
| 888 |
|
|
2'b00: xr <= (xr + 2'd1);
|
| 889 |
|
|
2'b01: yr <= (yr + 2'd1);
|
| 890 |
|
|
2'b10: usp <= (usp + 2'd1);
|
| 891 |
|
|
2'b11: ssp <= (ssp + 2'd1);
|
| 892 |
|
|
endcase
|
| 893 |
|
|
end
|
| 894 |
|
|
8'b1xxx0001: begin
|
| 895 |
|
|
radr <= radr + ndxreg;
|
| 896 |
|
|
case(ndxbyte[6:5])
|
| 897 |
|
|
2'b00: xr <= (xr + 2'd2);
|
| 898 |
|
|
2'b01: yr <= (yr + 2'd2);
|
| 899 |
|
|
2'b10: usp <= (usp + 2'd2);
|
| 900 |
|
|
2'b11: ssp <= (ssp + 2'd2);
|
| 901 |
|
|
endcase
|
| 902 |
|
|
end
|
| 903 |
|
|
8'b1xxx0010: radr <= radr + ndxreg;
|
| 904 |
|
|
8'b1xxx0011: radr <= radr + ndxreg;
|
| 905 |
|
|
8'b1xxx0100: radr <= radr + ndxreg;
|
| 906 |
|
|
8'b1xxx0101: radr <= radr + ndxreg;
|
| 907 |
|
|
8'b1xxx0110: radr <= radr + ndxreg;
|
| 908 |
|
|
8'b1xxx1000: radr <= radr + ndxreg;
|
| 909 |
|
|
8'b1xxx1001: radr <= radr + ndxreg;
|
| 910 |
|
|
8'b1xxx1010: radr <= radr + ndxreg;
|
| 911 |
|
|
8'b1xxx1011: radr <= radr + ndxreg;
|
| 912 |
|
|
default: radr <= radr;
|
| 913 |
|
|
endcase
|
| 914 |
|
|
end
|
| 915 |
|
|
else if (bitsPerByte==12) begin
|
| 916 |
|
|
casex(ndxbyte)
|
| 917 |
|
|
12'b0xxxxxxxxxxx: radr <= radr + ndxreg;
|
| 918 |
|
|
12'b1xxxx0000000:
|
| 919 |
|
|
begin
|
| 920 |
|
|
radr <= radr + ndxreg;
|
| 921 |
|
|
case(ndxbyte[10:9])
|
| 922 |
|
|
2'b00: xr <= (xr + 2'd1);
|
| 923 |
|
|
2'b01: yr <= (yr + 2'd1);
|
| 924 |
|
|
2'b10: usp <= (usp + 2'd1);
|
| 925 |
|
|
2'b11: ssp <= (ssp + 2'd1);
|
| 926 |
|
|
endcase
|
| 927 |
|
|
end
|
| 928 |
|
|
12'b1xxxx0000001: begin
|
| 929 |
|
|
radr <= radr + ndxreg;
|
| 930 |
|
|
case(ndxbyte[10:9])
|
| 931 |
|
|
2'b00: xr <= (xr + 2'd2);
|
| 932 |
|
|
2'b01: yr <= (yr + 2'd2);
|
| 933 |
|
|
2'b10: usp <= (usp + 2'd2);
|
| 934 |
|
|
2'b11: ssp <= (ssp + 2'd2);
|
| 935 |
|
|
endcase
|
| 936 |
|
|
end
|
| 937 |
|
|
12'b1xxxx0000010: radr <= radr + ndxreg;
|
| 938 |
|
|
12'b1xxxx0000011: radr <= radr + ndxreg;
|
| 939 |
|
|
12'b1xxxx0000100: radr <= radr + ndxreg;
|
| 940 |
|
|
12'b1xxxx0000101: radr <= radr + ndxreg;
|
| 941 |
|
|
12'b1xxxx0000110: radr <= radr + ndxreg;
|
| 942 |
|
|
12'b1xxxx0001000: radr <= radr + ndxreg;
|
| 943 |
|
|
12'b1xxxx0001001: radr <= radr + ndxreg;
|
| 944 |
|
|
12'b1xxxx0001010: radr <= radr + ndxreg;
|
| 945 |
|
|
12'b1xxxx0001011: radr <= radr + ndxreg;
|
| 946 |
|
|
default: radr <= radr;
|
| 947 |
|
|
endcase
|
| 948 |
|
|
end
|
| 949 |
|
|
next_state(OUTER_INDEXING2);
|
| 950 |
|
|
end
|
| 951 |
|
|
OUTER_INDEXING2:
|
| 952 |
|
|
begin
|
| 953 |
|
|
wadr <= radr;
|
| 954 |
|
|
res <= radr[`DBLBYTE];
|
| 955 |
|
|
load_what <= load_what2;
|
| 956 |
|
|
if (isLEA)
|
| 957 |
|
|
next_state(IFETCH);
|
| 958 |
|
|
else if (isStore)
|
| 959 |
|
|
next_state(STORE1);
|
| 960 |
|
|
else
|
| 961 |
|
|
next_state(LOAD1);
|
| 962 |
|
|
end
|
| 963 |
|
|
|
| 964 |
|
|
// ============================================================================
|
| 965 |
|
|
// Cache Control
|
| 966 |
|
|
// ============================================================================
|
| 967 |
|
|
ICACHE1:
|
| 968 |
|
|
begin
|
| 969 |
|
|
iccnt <= 4'h0;
|
| 970 |
|
|
outstanding <= 16'h0;
|
| 971 |
|
|
if (hit0 & hit1)
|
| 972 |
|
|
next_state(IFETCH);
|
| 973 |
|
|
else if (!tsc && !ack_i) begin
|
| 974 |
|
|
rhit0 <= hit0;
|
| 975 |
|
|
bte_o <= 2'b00;
|
| 976 |
|
|
cti_o <= 3'b001;
|
| 977 |
|
|
cyc_o <= 1'b1;
|
| 978 |
|
|
bl_o <= 6'd15;
|
| 979 |
|
|
stb_o <= 1'b1;
|
| 980 |
|
|
we_o <= 1'b0;
|
| 981 |
|
|
adr_o <= !hit0 ? {pc[bitsPerByte*3-1:4],4'b00} : {pcp16[bitsPerByte*3-1:4],4'b0000};
|
| 982 |
|
|
dat_o <= 12'd0;
|
| 983 |
|
|
next_state(ICACHE2);
|
| 984 |
|
|
end
|
| 985 |
|
|
end
|
| 986 |
|
|
// If tsc is asserted during an instruction cache fetch, then abort the fetch
|
| 987 |
|
|
// cycle, and wait until tsc deactivates.
|
| 988 |
|
|
// The instruction cache uses asynchronous reading through the network for
|
| 989 |
|
|
// better performance. The read request and the read response are two
|
| 990 |
|
|
// separate things.
|
| 991 |
|
|
ICACHE2:
|
| 992 |
|
|
`ifdef SUPPORT_AREAD
|
| 993 |
|
|
if (tsc) begin
|
| 994 |
|
|
wb_nack();
|
| 995 |
|
|
next_state(ICACHE3);
|
| 996 |
|
|
end
|
| 997 |
|
|
else if (ack_i|rty_i|bto) begin
|
| 998 |
|
|
stb_o <= 1'b0;
|
| 999 |
|
|
iccnt <= iccnt + 2'd1;
|
| 1000 |
|
|
next_state(ICACHE4);
|
| 1001 |
|
|
if (iccnt==4'b1110)
|
| 1002 |
|
|
cti_o <= 3'b111;
|
| 1003 |
|
|
if (iccnt==4'b1111) begin
|
| 1004 |
|
|
icwa <= adr_o;
|
| 1005 |
|
|
wb_nack();
|
| 1006 |
|
|
next_state(ICACHE5);
|
| 1007 |
|
|
end
|
| 1008 |
|
|
end
|
| 1009 |
|
|
`else
|
| 1010 |
|
|
if (tsc|rty_i) begin
|
| 1011 |
|
|
wb_nack();
|
| 1012 |
|
|
next_state(ICACHE3);
|
| 1013 |
|
|
end
|
| 1014 |
|
|
else if (ack_i) begin
|
| 1015 |
|
|
stb_o <= 1'b0;
|
| 1016 |
|
|
iccnt <= iccnt + 2'd1;
|
| 1017 |
|
|
next_state(ICACHE4);
|
| 1018 |
|
|
if (iccnt==4'b1110)
|
| 1019 |
|
|
cti_o <= 3'b111;
|
| 1020 |
|
|
if (iccnt==4'b1111) begin
|
| 1021 |
|
|
icwa <= adr_o;
|
| 1022 |
|
|
wb_nack();
|
| 1023 |
|
|
next_state(ICACHE6);
|
| 1024 |
|
|
end
|
| 1025 |
|
|
end
|
| 1026 |
|
|
`endif
|
| 1027 |
|
|
|
| 1028 |
|
|
ICACHE4:
|
| 1029 |
|
|
if (!ack_i) begin
|
| 1030 |
|
|
adr_o[3:0] <= iccnt;
|
| 1031 |
|
|
stb_o <= 1'b1;
|
| 1032 |
|
|
next_state(ICACHE2);
|
| 1033 |
|
|
end
|
| 1034 |
|
|
|
| 1035 |
|
|
ICACHE6:
|
| 1036 |
|
|
next_state(ICACHE1);
|
| 1037 |
|
|
|
| 1038 |
|
|
// The following states to handle outstanding transfers.
|
| 1039 |
|
|
// The transfer might retry several times if it has not registered.
|
| 1040 |
|
|
`ifdef SUPPORT_AREAD
|
| 1041 |
|
|
ICACHE5:
|
| 1042 |
|
|
// Line loaded?
|
| 1043 |
|
|
if (icgot == 16'hFFFF)
|
| 1044 |
|
|
next_state(ICACHE6);
|
| 1045 |
|
|
else begin
|
| 1046 |
|
|
waitcnt <= 6'd20;
|
| 1047 |
|
|
next_state(ICACHE7);
|
| 1048 |
|
|
end
|
| 1049 |
|
|
ICACHE7:
|
| 1050 |
|
|
if (waitcnt==6'd0) begin
|
| 1051 |
|
|
next_state(ICACHE6);
|
| 1052 |
|
|
adr_o <= icwa;
|
| 1053 |
|
|
for (n4 = 15; n4 >= 0; n4 = n4 - 1)
|
| 1054 |
|
|
if (~icgot[n4] & ~outstanding[n4]) begin
|
| 1055 |
|
|
cti_o <= 3'b001;
|
| 1056 |
|
|
cyc_o <= TRUE;
|
| 1057 |
|
|
stb_o <= TRUE;
|
| 1058 |
|
|
adr_o[3:0] <= n4[3:0];
|
| 1059 |
|
|
outstanding[n4[3:0]] <= 1'b1;
|
| 1060 |
|
|
next_state(ICACHE9);
|
| 1061 |
|
|
end
|
| 1062 |
|
|
end
|
| 1063 |
|
|
else
|
| 1064 |
|
|
waitcnt <= waitcnt - 2'd1;
|
| 1065 |
|
|
ICACHE9:
|
| 1066 |
|
|
begin
|
| 1067 |
|
|
if (bto)
|
| 1068 |
|
|
outstanding <= 16'h0;
|
| 1069 |
|
|
if (aack_i)
|
| 1070 |
|
|
outstanding[adr_o[3:0]] <= 1'b0;
|
| 1071 |
|
|
if (ack_i|rty_i|bto) begin
|
| 1072 |
|
|
wb_nack();
|
| 1073 |
|
|
waitcnt <= 6'd20;
|
| 1074 |
|
|
next_state(ICACHE7);
|
| 1075 |
|
|
end
|
| 1076 |
|
|
end
|
| 1077 |
|
|
`endif
|
| 1078 |
|
|
|
| 1079 |
|
|
// Restart a cache load aborted by the TSC signal. A registered version of the
|
| 1080 |
|
|
// hit signal must be used as the cache may be partially updated.
|
| 1081 |
|
|
ICACHE3:
|
| 1082 |
|
|
if (!tsc) begin
|
| 1083 |
|
|
bte_o <= 2'b00;
|
| 1084 |
|
|
cti_o <= 3'b001;
|
| 1085 |
|
|
cyc_o <= 1'b1;
|
| 1086 |
|
|
bl_o <= 6'd15;
|
| 1087 |
|
|
stb_o <= 1'b1;
|
| 1088 |
|
|
we_o <= 1'b0;
|
| 1089 |
|
|
adr_o <= !rhit0 ? {pc[bitsPerByte*3-1:4],4'b00} : {pcp16[bitsPerByte*3-1:4],4'b0000};
|
| 1090 |
|
|
dat_o <= 12'd0;
|
| 1091 |
|
|
next_state(ICACHE2);
|
| 1092 |
|
|
end
|
| 1093 |
|
|
|
| 1094 |
|
|
`ifdef SUPPORT_IBUF
|
| 1095 |
|
|
IBUF1:
|
| 1096 |
|
|
if (!tsc) begin
|
| 1097 |
|
|
bte_o <= 2'b00;
|
| 1098 |
|
|
cti_o <= 3'b001;
|
| 1099 |
|
|
cyc_o <= 1'b1;
|
| 1100 |
|
|
bl_o <= 6'd2;
|
| 1101 |
|
|
stb_o <= 1'b1;
|
| 1102 |
|
|
we_o <= 1'b0;
|
| 1103 |
|
|
adr_o <= pc[`DBLBYTE];
|
| 1104 |
|
|
dat_o <= 12'd0;
|
| 1105 |
|
|
next_state(IBUF2);
|
| 1106 |
|
|
end
|
| 1107 |
|
|
IBUF2:
|
| 1108 |
|
|
if (tsc|rty_i) begin
|
| 1109 |
|
|
wb_nack();
|
| 1110 |
|
|
next_state(IBUF1);
|
| 1111 |
|
|
end
|
| 1112 |
|
|
else if (ack_i) begin
|
| 1113 |
|
|
adr_o <= adr_o + 2'd1;
|
| 1114 |
|
|
ibuf <= dat_i;
|
| 1115 |
|
|
next_state(IBUF3);
|
| 1116 |
|
|
end
|
| 1117 |
|
|
IBUF3:
|
| 1118 |
|
|
if (tsc|rty_i) begin
|
| 1119 |
|
|
wb_nack();
|
| 1120 |
|
|
next_state(IBUF1);
|
| 1121 |
|
|
end
|
| 1122 |
|
|
else if (ack_i) begin
|
| 1123 |
|
|
cti_o <= 3'b111;
|
| 1124 |
|
|
adr_o <= adr_o + 2'd1;
|
| 1125 |
|
|
ibuf[`HIBYTE] <= dat_i;
|
| 1126 |
|
|
next_state(IBUF4);
|
| 1127 |
|
|
end
|
| 1128 |
|
|
IBUF4:
|
| 1129 |
|
|
if (tsc|rty_i) begin
|
| 1130 |
|
|
wb_nack();
|
| 1131 |
|
|
next_state(IBUF1);
|
| 1132 |
|
|
end
|
| 1133 |
|
|
else if (ack_i) begin
|
| 1134 |
|
|
wb_nack();
|
| 1135 |
|
|
ibuf[`BYTE3] <= dat_i;
|
| 1136 |
|
|
next_state(IBUF5);
|
| 1137 |
|
|
end
|
| 1138 |
|
|
IBUF5:
|
| 1139 |
|
|
if (tsc|rty_i) begin
|
| 1140 |
|
|
wb_nack();
|
| 1141 |
|
|
next_state(IBUF1);
|
| 1142 |
|
|
end
|
| 1143 |
|
|
else if (ack_i) begin
|
| 1144 |
|
|
wb_nack();
|
| 1145 |
|
|
ibuf[`BYTE4] <= dat_i;
|
| 1146 |
|
|
next_state(IBUF6);
|
| 1147 |
|
|
end
|
| 1148 |
|
|
IBUF6:
|
| 1149 |
|
|
if (tsc|rty_i) begin
|
| 1150 |
|
|
wb_nack();
|
| 1151 |
|
|
next_state(IBUF1);
|
| 1152 |
|
|
end
|
| 1153 |
|
|
else if (ack_i) begin
|
| 1154 |
|
|
wb_nack();
|
| 1155 |
|
|
ibuf[`BYTE5] <= dat_i;
|
| 1156 |
|
|
ibufadr <= pc;
|
| 1157 |
|
|
next_state(IFETCH);
|
| 1158 |
|
|
end
|
| 1159 |
|
|
`endif
|
| 1160 |
|
|
|
| 1161 |
|
|
endcase
|
| 1162 |
|
|
end
|
| 1163 |
|
|
|
| 1164 |
|
|
// ============================================================================
|
| 1165 |
|
|
// ============================================================================
|
| 1166 |
|
|
// Supporting Tasks
|
| 1167 |
|
|
// ============================================================================
|
| 1168 |
|
|
// ============================================================================
|
| 1169 |
|
|
|
| 1170 |
|
|
// ============================================================================
|
| 1171 |
|
|
// IFETCH
|
| 1172 |
|
|
//
|
| 1173 |
|
|
// Fetch instructions.
|
| 1174 |
|
|
// ============================================================================
|
| 1175 |
|
|
|
| 1176 |
|
|
task tIfetch;
|
| 1177 |
|
|
begin
|
| 1178 |
|
|
if (halt_i) begin
|
| 1179 |
|
|
ba_o <= 1'b1;
|
| 1180 |
|
|
bs_o <= 1'b1;
|
| 1181 |
|
|
end
|
| 1182 |
|
|
else begin
|
| 1183 |
|
|
ba_o <= 1'b0;
|
| 1184 |
|
|
bs_o <= 1'b0;
|
| 1185 |
|
|
next_state(DECODE);
|
| 1186 |
|
|
isFar <= `FALSE;
|
| 1187 |
|
|
isOuterIndexed <= `FALSE;
|
| 1188 |
|
|
ipg <= 2'b00;
|
| 1189 |
|
|
ia <= 24'd0;
|
| 1190 |
|
|
res <= 24'd0;
|
| 1191 |
|
|
load_what <= `LW_NOTHING;
|
| 1192 |
|
|
store_what <= `SW_NOTHING;
|
| 1193 |
|
|
if (nmi_edge | firq_i | irq_i)
|
| 1194 |
|
|
sync_state <= `FALSE;
|
| 1195 |
|
|
if (nmi_edge & nmi_armed) begin
|
| 1196 |
|
|
bs_o <= 1'b1;
|
| 1197 |
|
|
ir[`LOBYTE] <= `INT;
|
| 1198 |
|
|
ipg <= 2'b11;
|
| 1199 |
|
|
vect <= `NMI_VECT;
|
| 1200 |
|
|
end
|
| 1201 |
|
|
else if (firq_i & !firqim & !sync_state) begin
|
| 1202 |
|
|
bs_o <= 1'b1;
|
| 1203 |
|
|
ir[`LOBYTE] <= `INT;
|
| 1204 |
|
|
ipg <= 2'b11;
|
| 1205 |
|
|
vect <= `FIRQ_VECT;
|
| 1206 |
|
|
end
|
| 1207 |
|
|
else if (irq_i & !im & !sync_state) begin
|
| 1208 |
|
|
$display("**************************************");
|
| 1209 |
|
|
$display("****** Interrupt *********************");
|
| 1210 |
|
|
$display("**************************************");
|
| 1211 |
|
|
bs_o <= 1'b1;
|
| 1212 |
|
|
ir[`LOBYTE] <= `INT;
|
| 1213 |
|
|
ipg <= 2'b11;
|
| 1214 |
|
|
vect <= `IRQ_VECT;
|
| 1215 |
|
|
end
|
| 1216 |
|
|
else begin
|
| 1217 |
|
|
if (sync_state) begin
|
| 1218 |
|
|
ba_o <= 1'b1;
|
| 1219 |
|
|
next_state(IFETCH);
|
| 1220 |
|
|
end
|
| 1221 |
|
|
else if (icacheOn) begin
|
| 1222 |
|
|
if (ihit) begin
|
| 1223 |
|
|
ir <= insn;
|
| 1224 |
|
|
end
|
| 1225 |
|
|
else begin
|
| 1226 |
|
|
ipg <= ipg;
|
| 1227 |
|
|
isFar <= isFar;
|
| 1228 |
|
|
isOuterIndexed <= isOuterIndexed;
|
| 1229 |
|
|
next_state(ICACHE1);
|
| 1230 |
|
|
end
|
| 1231 |
|
|
end
|
| 1232 |
|
|
`ifdef SUPPORT_IBUF
|
| 1233 |
|
|
else begin
|
| 1234 |
|
|
if (ibufhit)
|
| 1235 |
|
|
ir <= ibuf;
|
| 1236 |
|
|
else begin
|
| 1237 |
|
|
ipg <= ipg;
|
| 1238 |
|
|
isFar <= isFar;
|
| 1239 |
|
|
isOuterIndexed <= isOuterIndexed;
|
| 1240 |
|
|
next_state(IBUF1);
|
| 1241 |
|
|
end
|
| 1242 |
|
|
end
|
| 1243 |
|
|
`endif
|
| 1244 |
|
|
end
|
| 1245 |
|
|
end
|
| 1246 |
|
|
end
|
| 1247 |
|
|
endtask
|
| 1248 |
|
|
|
| 1249 |
|
|
// ============================================================================
|
| 1250 |
|
|
// DECODE
|
| 1251 |
|
|
//
|
| 1252 |
|
|
// Decode instruction and fetch register file values.
|
| 1253 |
|
|
// ============================================================================
|
| 1254 |
|
|
|
| 1255 |
|
|
task tDecode;
|
| 1256 |
|
|
begin
|
| 1257 |
|
|
first_ifetch <= `TRUE;
|
| 1258 |
|
|
next_state(IFETCH); // default: move to IFETCH
|
| 1259 |
|
|
pc <= pc + 2'd1; // default: increment PC by one
|
| 1260 |
|
|
a <= 24'd0;
|
| 1261 |
|
|
b <= 24'd0;
|
| 1262 |
|
|
ia <= 24'd0;
|
| 1263 |
|
|
isDblIndirect <= `FALSE;//ndxbyte[11:4]==8'h8F;
|
| 1264 |
|
|
if (isIndexed) begin
|
| 1265 |
|
|
if (bitsPerByte==8) begin
|
| 1266 |
|
|
casez(ndxbyte)
|
| 1267 |
|
|
8'b1??00000:
|
| 1268 |
|
|
if (!isOuterIndexed)
|
| 1269 |
|
|
case(ndxbyte[6:5])
|
| 1270 |
|
|
2'b00: xr <= (xr + 4'd1);
|
| 1271 |
|
|
2'b01: yr <= (yr + 4'd1);
|
| 1272 |
|
|
2'b10: usp <= (usp + 4'd1);
|
| 1273 |
|
|
2'b11: ssp <= (ssp + 4'd1);
|
| 1274 |
|
|
endcase
|
| 1275 |
|
|
8'b1??00001:
|
| 1276 |
|
|
if (!isOuterIndexed)
|
| 1277 |
|
|
case(ndxbyte[6:5])
|
| 1278 |
|
|
2'b00: xr <= (xr + 4'd2);
|
| 1279 |
|
|
2'b01: yr <= (yr + 4'd2);
|
| 1280 |
|
|
2'b10: usp <= (usp + 4'd2);
|
| 1281 |
|
|
2'b11: ssp <= (ssp + 4'd2);
|
| 1282 |
|
|
endcase
|
| 1283 |
|
|
8'b1??00010:
|
| 1284 |
|
|
case(ndxbyte[6:5])
|
| 1285 |
|
|
2'b00: xr <= (xr - 2'd1);
|
| 1286 |
|
|
2'b01: yr <= (yr - 2'd1);
|
| 1287 |
|
|
2'b10: usp <= (usp - 2'd1);
|
| 1288 |
|
|
2'b11: ssp <= (ssp - 2'd1);
|
| 1289 |
|
|
endcase
|
| 1290 |
|
|
8'b1??00011:
|
| 1291 |
|
|
case(ndxbyte[6:5])
|
| 1292 |
|
|
2'b00: xr <= (xr - 2'd2);
|
| 1293 |
|
|
2'b01: yr <= (yr - 2'd2);
|
| 1294 |
|
|
2'b10: usp <= (usp - 2'd2);
|
| 1295 |
|
|
2'b11: ssp <= (ssp - 2'd2);
|
| 1296 |
|
|
endcase
|
| 1297 |
|
|
endcase
|
| 1298 |
|
|
end
|
| 1299 |
|
|
else if (bitsPerByte==12) begin
|
| 1300 |
|
|
casez(ndxbyte)
|
| 1301 |
|
|
12'b1??000000000:
|
| 1302 |
|
|
if (!isOuterIndexed && ndxbyte[7]==1'b0)
|
| 1303 |
|
|
case(ndxbyte[10:9])
|
| 1304 |
|
|
2'b00: xr <= (xr + 4'd1);
|
| 1305 |
|
|
2'b01: yr <= (yr + 4'd1);
|
| 1306 |
|
|
2'b10: usp <= (usp + 4'd1);
|
| 1307 |
|
|
2'b11: ssp <= (ssp + 4'd1);
|
| 1308 |
|
|
endcase
|
| 1309 |
|
|
12'b1??000000001:
|
| 1310 |
|
|
if (!isOuterIndexed && ndxbyte[7]==1'b0)
|
| 1311 |
|
|
case(ndxbyte[10:9])
|
| 1312 |
|
|
2'b00: xr <= (xr + 4'd2);
|
| 1313 |
|
|
2'b01: yr <= (yr + 4'd2);
|
| 1314 |
|
|
2'b10: usp <= (usp + 4'd2);
|
| 1315 |
|
|
2'b11: ssp <= (ssp + 4'd2);
|
| 1316 |
|
|
endcase
|
| 1317 |
|
|
12'b1??0x0000010:
|
| 1318 |
|
|
case(ndxbyte[10:9])
|
| 1319 |
|
|
2'b00: xr <= (xr - 2'd1);
|
| 1320 |
|
|
2'b01: yr <= (yr - 2'd1);
|
| 1321 |
|
|
2'b10: usp <= (usp - 2'd1);
|
| 1322 |
|
|
2'b11: ssp <= (ssp - 2'd1);
|
| 1323 |
|
|
endcase
|
| 1324 |
|
|
12'b1??0x0000011:
|
| 1325 |
|
|
case(ndxbyte[10:9])
|
| 1326 |
|
|
2'b00: xr <= (xr - 2'd2);
|
| 1327 |
|
|
2'b01: yr <= (yr - 2'd2);
|
| 1328 |
|
|
2'b10: usp <= (usp - 2'd2);
|
| 1329 |
|
|
2'b11: ssp <= (ssp - 2'd2);
|
| 1330 |
|
|
endcase
|
| 1331 |
|
|
endcase
|
| 1332 |
|
|
end
|
| 1333 |
|
|
end
|
| 1334 |
|
|
case(ir12)
|
| 1335 |
|
|
`NOP: ;
|
| 1336 |
|
|
`SYNC: sync_state <= `TRUE;
|
| 1337 |
|
|
`ORCC: begin
|
| 1338 |
|
|
cf <= cf | ir[bitsPerByte];
|
| 1339 |
|
|
vf <= vf | ir[bitsPerByte+1];
|
| 1340 |
|
|
zf <= zf | ir[bitsPerByte+2];
|
| 1341 |
|
|
nf <= nf | ir[bitsPerByte+3];
|
| 1342 |
|
|
im <= im | ir[bitsPerByte+4];
|
| 1343 |
|
|
hf <= hf | ir[bitsPerByte+5];
|
| 1344 |
|
|
firqim <= firqim | ir[bitsPerByte+6];
|
| 1345 |
|
|
ef <= ef | ir[bitsPerByte+7];
|
| 1346 |
|
|
pc <= pcp2;
|
| 1347 |
|
|
end
|
| 1348 |
|
|
`ANDCC:
|
| 1349 |
|
|
begin
|
| 1350 |
|
|
cf <= cf & ir[bitsPerByte];
|
| 1351 |
|
|
vf <= vf & ir[bitsPerByte+1];
|
| 1352 |
|
|
zf <= zf & ir[bitsPerByte+2];
|
| 1353 |
|
|
nf <= nf & ir[bitsPerByte+3];
|
| 1354 |
|
|
im <= im & ir[bitsPerByte+4];
|
| 1355 |
|
|
hf <= hf & ir[bitsPerByte+5];
|
| 1356 |
|
|
firqim <= firqim & ir[bitsPerByte+6];
|
| 1357 |
|
|
ef <= ef & ir[bitsPerByte+7];
|
| 1358 |
|
|
pc <= pcp2;
|
| 1359 |
|
|
end
|
| 1360 |
|
|
`DAA:
|
| 1361 |
|
|
begin
|
| 1362 |
|
|
if (hf || acca[3:0] > 4'd9)
|
| 1363 |
|
|
res12[3:0] <= acca[3:0] + 4'd6;
|
| 1364 |
|
|
if (cf || acca[7:4] > 4'd9 || (acca[7:4] > 4'd8 && acca[3:0] > 4'd9))
|
| 1365 |
|
|
res12[8:4] <= acca[7:4] + 4'd6;
|
| 1366 |
|
|
end
|
| 1367 |
|
|
`CWAI:
|
| 1368 |
|
|
begin
|
| 1369 |
|
|
cf <= cf & ir[bitsPerByte];
|
| 1370 |
|
|
vf <= vf & ir[bitsPerByte+1];
|
| 1371 |
|
|
zf <= zf & ir[bitsPerByte+2];
|
| 1372 |
|
|
nf <= nf & ir[bitsPerByte+3];
|
| 1373 |
|
|
im <= im & ir[bitsPerByte+4];
|
| 1374 |
|
|
hf <= hf & ir[bitsPerByte+5];
|
| 1375 |
|
|
firqim <= firqim & ir[bitsPerByte+6];
|
| 1376 |
|
|
ef <= 1'b1;
|
| 1377 |
|
|
pc <= pc + 2'd2;
|
| 1378 |
|
|
ir[`HIBYTE] <= -1;
|
| 1379 |
|
|
isFar <= `TRUE;
|
| 1380 |
|
|
wait_state <= `TRUE;
|
| 1381 |
|
|
next_state(PUSH1);
|
| 1382 |
|
|
end
|
| 1383 |
|
|
`LDMD: begin
|
| 1384 |
|
|
natMd <= ir[bitsPerByte];
|
| 1385 |
|
|
firqMd <= ir[bitsPerByte+1];
|
| 1386 |
|
|
pc <= pc + 2'd2;
|
| 1387 |
|
|
end
|
| 1388 |
|
|
`TFR: pc <= pc + 2'd2;
|
| 1389 |
|
|
`EXG: pc <= pc + 2'd2;
|
| 1390 |
|
|
`ABX: res <= xr + accb;
|
| 1391 |
|
|
`SEX: res <= {{bitsPerByte{accb[BPBM1]}},accb[`LOBYTE]};
|
| 1392 |
|
|
`PG2: begin ipg <= 2'b01; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
|
| 1393 |
|
|
`PG3: begin ipg <= 2'b10; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
|
| 1394 |
|
|
`FAR: begin isFar <= `TRUE; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
|
| 1395 |
|
|
`OUTER: begin isOuterIndexed <= `TRUE; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
|
| 1396 |
|
|
|
| 1397 |
|
|
`NEGA,`NEGB: begin res12 <= -acc[`LOBYTE]; a <= 24'h00; b <= acc; end
|
| 1398 |
|
|
`COMA,`COMB: begin res12 <= ~acc[`LOBYTE]; end
|
| 1399 |
|
|
`LSRA,`LSRB: begin res12 <= {acc[0],1'b0,acc[BPBM1:1]}; end
|
| 1400 |
|
|
`RORA,`RORB: begin res12 <= {acc[0],cf,acc[BPBM1:1]}; end
|
| 1401 |
|
|
`ASRA,`ASRB: begin res12 <= {acc[0],acc[BPBM1],acc[BPBM1:1]}; end
|
| 1402 |
|
|
`ASLA,`ASLB: begin res12 <= {acc[`LOBYTE],1'b0}; end
|
| 1403 |
|
|
`ROLA,`ROLB: begin res12 <= {acc[`LOBYTE],cf}; end
|
| 1404 |
|
|
`DECA,`DECB: begin res12 <= acc[`LOBYTE] - 2'd1; end
|
| 1405 |
|
|
`INCA,`INCB: begin res12 <= acc[`LOBYTE] + 2'd1; end
|
| 1406 |
|
|
`TSTA,`TSTB: begin res12 <= acc[`LOBYTE]; end
|
| 1407 |
|
|
`CLRA,`CLRB: begin res12 <= 13'h000; end
|
| 1408 |
|
|
|
| 1409 |
|
|
// Immediate mode instructions
|
| 1410 |
|
|
`SUBA_IMM,`SUBB_IMM,`CMPA_IMM,`CMPB_IMM:
|
| 1411 |
|
|
begin res12 <= acc[`LOBYTE] - ir[`HIBYTE]; pc <= pc + 4'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
| 1412 |
|
|
`SBCA_IMM,`SBCB_IMM:
|
| 1413 |
|
|
begin res12 <= acc[`LOBYTE] - ir[`HIBYTE] - cf; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
| 1414 |
|
|
`ANDA_IMM,`ANDB_IMM,`BITA_IMM,`BITB_IMM:
|
| 1415 |
|
|
begin res12 <= acc[`LOBYTE] & ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
| 1416 |
|
|
`LDA_IMM,`LDB_IMM:
|
| 1417 |
|
|
begin res12 <= ir[`HIBYTE]; pc <= pc + 2'd2; end
|
| 1418 |
|
|
`EORA_IMM,`EORB_IMM:
|
| 1419 |
|
|
begin res12 <= acc[`LOBYTE] ^ ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
| 1420 |
|
|
`ADCA_IMM,`ADCB_IMM:
|
| 1421 |
|
|
begin res12 <= acc[`LOBYTE] + ir[`HIBYTE] + cf; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
| 1422 |
|
|
`ORA_IMM,`ORB_IMM:
|
| 1423 |
|
|
begin res12 <= acc[`LOBYTE] | ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
| 1424 |
|
|
`ADDA_IMM,`ADDB_IMM:
|
| 1425 |
|
|
begin res12 <= acc[`LOBYTE] + ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
| 1426 |
|
|
`ADDD_IMM:
|
| 1427 |
|
|
begin
|
| 1428 |
|
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + {ir[`HIBYTE],ir[`BYTE3]};
|
| 1429 |
|
|
pc <= pc + 2'd3;
|
| 1430 |
|
|
end
|
| 1431 |
|
|
`SUBD_IMM:
|
| 1432 |
|
|
begin
|
| 1433 |
|
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - {ir[`HIBYTE],ir[`BYTE3]};
|
| 1434 |
|
|
pc <= pc + 2'd3;
|
| 1435 |
|
|
end
|
| 1436 |
|
|
`LDD_IMM:
|
| 1437 |
|
|
begin
|
| 1438 |
|
|
res <= {ir[`HIBYTE],ir[`BYTE3]};
|
| 1439 |
|
|
pc <= pc + 2'd3;
|
| 1440 |
|
|
end
|
| 1441 |
|
|
`LDX_IMM,`LDY_IMM,`LDU_IMM,`LDS_IMM:
|
| 1442 |
|
|
begin
|
| 1443 |
|
|
res <= {ir[`HIBYTE],ir[`BYTE3]};
|
| 1444 |
|
|
pc <= pc + 2'd3;
|
| 1445 |
|
|
end
|
| 1446 |
|
|
|
| 1447 |
|
|
`CMPD_IMM:
|
| 1448 |
|
|
begin
|
| 1449 |
|
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - {ir[`HIBYTE],ir[`BYTE3]};
|
| 1450 |
|
|
pc <= pc + 2'd3;
|
| 1451 |
|
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
| 1452 |
|
|
b <= {ir[`HIBYTE],ir[`BYTE3]};
|
| 1453 |
|
|
end
|
| 1454 |
|
|
`CMPX_IMM:
|
| 1455 |
|
|
begin
|
| 1456 |
|
|
res <= xr[`DBLBYTE] - {ir[`HIBYTE],ir[`BYTE3]};
|
| 1457 |
|
|
pc <= pc + 2'd3;
|
| 1458 |
|
|
a <= xr[`DBLBYTE];
|
| 1459 |
|
|
b <= {ir[`HIBYTE],ir[`BYTE3]};
|
| 1460 |
|
|
end
|
| 1461 |
|
|
`CMPY_IMM:
|
| 1462 |
|
|
begin
|
| 1463 |
|
|
res <= yr[`DBLBYTE] - {ir[`HIBYTE],ir[`BYTE3]};
|
| 1464 |
|
|
pc <= pc + 2'd3;
|
| 1465 |
|
|
a <= yr[`DBLBYTE];
|
| 1466 |
|
|
b <= {ir[`HIBYTE],ir[`BYTE3]};
|
| 1467 |
|
|
end
|
| 1468 |
|
|
`CMPU_IMM:
|
| 1469 |
|
|
begin
|
| 1470 |
|
|
res <= usp[`DBLBYTE] - {ir[`HIBYTE],ir[`BYTE3]};
|
| 1471 |
|
|
pc <= pc + 2'd3;
|
| 1472 |
|
|
a <= usp[`DBLBYTE];
|
| 1473 |
|
|
b <= {ir[`HIBYTE],ir[`BYTE3]};
|
| 1474 |
|
|
end
|
| 1475 |
|
|
`CMPS_IMM:
|
| 1476 |
|
|
begin
|
| 1477 |
|
|
res <= ssp[`DBLBYTE] - {ir[`HIBYTE],ir[`BYTE3]};
|
| 1478 |
|
|
pc <= pc + 2'd3;
|
| 1479 |
|
|
a <= ssp[`DBLBYTE];
|
| 1480 |
|
|
b <= {ir[`HIBYTE],ir[`BYTE3]};
|
| 1481 |
|
|
end
|
| 1482 |
|
|
|
| 1483 |
|
|
// Direct mode instructions
|
| 1484 |
|
|
`NEG_DP,`COM_DP,`LSR_DP,`ROR_DP,`ASR_DP,`ASL_DP,`ROL_DP,`DEC_DP,`INC_DP,`TST_DP:
|
| 1485 |
|
|
begin
|
| 1486 |
|
|
load_what <= `LW_BL;
|
| 1487 |
|
|
radr <= dp_address;
|
| 1488 |
|
|
pc <= pc + 2'd2;
|
| 1489 |
|
|
next_state(LOAD1);
|
| 1490 |
|
|
end
|
| 1491 |
|
|
`SUBA_DP,`CMPA_DP,`SBCA_DP,`ANDA_DP,`BITA_DP,`LDA_DP,`EORA_DP,`ADCA_DP,`ORA_DP,`ADDA_DP,
|
| 1492 |
|
|
`SUBB_DP,`CMPB_DP,`SBCB_DP,`ANDB_DP,`BITB_DP,`LDB_DP,`EORB_DP,`ADCB_DP,`ORB_DP,`ADDB_DP:
|
| 1493 |
|
|
begin
|
| 1494 |
|
|
load_what <= `LW_BL;
|
| 1495 |
|
|
radr <= dp_address;
|
| 1496 |
|
|
pc <= pc + 2'd2;
|
| 1497 |
|
|
next_state(LOAD1);
|
| 1498 |
|
|
end
|
| 1499 |
|
|
`SUBD_DP,`ADDD_DP,`LDD_DP,`CMPD_DP,`ADCD_DP,`SBCD_DP:
|
| 1500 |
|
|
begin
|
| 1501 |
|
|
load_what <= `LW_BH;
|
| 1502 |
|
|
pc <= pc + 2'd2;
|
| 1503 |
|
|
radr <= dp_address;
|
| 1504 |
|
|
next_state(LOAD1);
|
| 1505 |
|
|
end
|
| 1506 |
|
|
`CMPX_DP,`LDX_DP,`LDU_DP,`LDS_DP,
|
| 1507 |
|
|
`CMPY_DP,`CMPS_DP,`CMPU_DP,`LDY_DP:
|
| 1508 |
|
|
begin
|
| 1509 |
|
|
load_what <= `LW_BH;
|
| 1510 |
|
|
pc <= pc + 2'd2;
|
| 1511 |
|
|
radr <= dp_address;
|
| 1512 |
|
|
next_state(LOAD1);
|
| 1513 |
|
|
end
|
| 1514 |
|
|
`CLR_DP:
|
| 1515 |
|
|
begin
|
| 1516 |
|
|
dp_store(`SW_RES8);
|
| 1517 |
|
|
res12 <= 13'h000;
|
| 1518 |
|
|
end
|
| 1519 |
|
|
`STA_DP: dp_store(`SW_ACCA);
|
| 1520 |
|
|
`STB_DP: dp_store(`SW_ACCB);
|
| 1521 |
|
|
`STD_DP: dp_store(`SW_ACCDH);
|
| 1522 |
|
|
`STU_DP: dp_store(`SW_USPH);
|
| 1523 |
|
|
`STS_DP: dp_store(`SW_SSPH);
|
| 1524 |
|
|
`STX_DP: dp_store(`SW_XH);
|
| 1525 |
|
|
`STY_DP: dp_store(`SW_YH);
|
| 1526 |
|
|
// Indexed mode instructions
|
| 1527 |
|
|
`NEG_NDX,`COM_NDX,`LSR_NDX,`ROR_NDX,`ASR_NDX,`ASL_NDX,`ROL_NDX,`DEC_NDX,`INC_NDX,`TST_NDX:
|
| 1528 |
|
|
begin
|
| 1529 |
|
|
pc <= pc + insnsz;
|
| 1530 |
|
|
if (isIndirect) begin
|
| 1531 |
|
|
load_what <= isFar ? `LW_IA2316 : `LW_IAH;
|
| 1532 |
|
|
load_what2 <= `LW_BL;
|
| 1533 |
|
|
radr <= NdxAddr;
|
| 1534 |
|
|
next_state(LOAD1);
|
| 1535 |
|
|
end
|
| 1536 |
|
|
else begin
|
| 1537 |
|
|
b <= 24'd0;
|
| 1538 |
|
|
load_what <= `LW_BL;
|
| 1539 |
|
|
radr <= NdxAddr;
|
| 1540 |
|
|
next_state(LOAD1);
|
| 1541 |
|
|
end
|
| 1542 |
|
|
end
|
| 1543 |
|
|
`SUBA_NDX,`CMPA_NDX,`SBCA_NDX,`ANDA_NDX,`BITA_NDX,`LDA_NDX,`EORA_NDX,`ADCA_NDX,`ORA_NDX,`ADDA_NDX,
|
| 1544 |
|
|
`SUBB_NDX,`CMPB_NDX,`SBCB_NDX,`ANDB_NDX,`BITB_NDX,`LDB_NDX,`EORB_NDX,`ADCB_NDX,`ORB_NDX,`ADDB_NDX:
|
| 1545 |
|
|
begin
|
| 1546 |
|
|
pc <= pc + insnsz;
|
| 1547 |
|
|
if (isIndirect) begin
|
| 1548 |
|
|
load_what <= isFar ? `LW_IA2316 : `LW_IAH;
|
| 1549 |
|
|
load_what2 <= `LW_BL;
|
| 1550 |
|
|
radr <= NdxAddr;
|
| 1551 |
|
|
next_state(LOAD1);
|
| 1552 |
|
|
end
|
| 1553 |
|
|
else begin
|
| 1554 |
|
|
b <= 24'd0;
|
| 1555 |
|
|
load_what <= `LW_BL;
|
| 1556 |
|
|
radr <= NdxAddr;
|
| 1557 |
|
|
next_state(LOAD1);
|
| 1558 |
|
|
end
|
| 1559 |
|
|
end
|
| 1560 |
|
|
`SUBD_NDX,`ADDD_NDX,`LDD_NDX,`CMPD_NDX,`ADCD_NDX,`SBCD_NDX:
|
| 1561 |
|
|
begin
|
| 1562 |
|
|
pc <= pc + insnsz;
|
| 1563 |
|
|
if (isIndirect) begin
|
| 1564 |
|
|
load_what <= isFar ? `LW_IA2316 : `LW_IAH;
|
| 1565 |
|
|
load_what2 <= `LW_BH;
|
| 1566 |
|
|
radr <= NdxAddr;
|
| 1567 |
|
|
next_state(LOAD1);
|
| 1568 |
|
|
end
|
| 1569 |
|
|
else begin
|
| 1570 |
|
|
load_what <= `LW_BH;
|
| 1571 |
|
|
radr <= NdxAddr;
|
| 1572 |
|
|
next_state(LOAD1);
|
| 1573 |
|
|
end
|
| 1574 |
|
|
end
|
| 1575 |
|
|
`CMPX_NDX,`LDX_NDX,`LDU_NDX,`LDS_NDX,
|
| 1576 |
|
|
`CMPY_NDX,`CMPS_NDX,`CMPU_NDX,`LDY_NDX:
|
| 1577 |
|
|
begin
|
| 1578 |
|
|
pc <= pc + insnsz;
|
| 1579 |
|
|
if (isIndirect) begin
|
| 1580 |
|
|
load_what <= isFar ? `LW_IA2316 : `LW_IAH;
|
| 1581 |
|
|
load_what2 <= `LW_BH;
|
| 1582 |
|
|
radr <= NdxAddr;
|
| 1583 |
|
|
next_state(LOAD1);
|
| 1584 |
|
|
end
|
| 1585 |
|
|
else begin
|
| 1586 |
|
|
load_what <= `LW_BH;
|
| 1587 |
|
|
radr <= NdxAddr;
|
| 1588 |
|
|
next_state(LOAD1);
|
| 1589 |
|
|
end
|
| 1590 |
|
|
end
|
| 1591 |
|
|
`CLR_NDX:
|
| 1592 |
|
|
begin
|
| 1593 |
|
|
res12 <= 13'h000;
|
| 1594 |
|
|
indexed_store(`SW_RES8);
|
| 1595 |
|
|
end
|
| 1596 |
|
|
`STA_NDX: indexed_store(`SW_ACCA);
|
| 1597 |
|
|
`STB_NDX: indexed_store(`SW_ACCB);
|
| 1598 |
|
|
`STD_NDX: indexed_store(`SW_ACCDH);
|
| 1599 |
|
|
`STU_NDX: indexed_store(`SW_USPH);
|
| 1600 |
|
|
`STS_NDX: indexed_store(`SW_SSPH);
|
| 1601 |
|
|
`STX_NDX: indexed_store(`SW_XH);
|
| 1602 |
|
|
`STY_NDX: indexed_store(`SW_YH);
|
| 1603 |
|
|
|
| 1604 |
|
|
// Extended mode instructions
|
| 1605 |
|
|
`NEG_EXT,`COM_EXT,`LSR_EXT,`ROR_EXT,`ASR_EXT,`ASL_EXT,`ROL_EXT,`DEC_EXT,`INC_EXT,`TST_EXT:
|
| 1606 |
|
|
begin
|
| 1607 |
|
|
load_what <= `LW_BL;
|
| 1608 |
|
|
radr <= ex_address;
|
| 1609 |
|
|
pc <= pc + (isFar ? 32'd4 : 32'd3);
|
| 1610 |
|
|
next_state(LOAD1);
|
| 1611 |
|
|
end
|
| 1612 |
|
|
`SUBA_EXT,`CMPA_EXT,`SBCA_EXT,`ANDA_EXT,`BITA_EXT,`LDA_EXT,`EORA_EXT,`ADCA_EXT,`ORA_EXT,`ADDA_EXT,
|
| 1613 |
|
|
`SUBB_EXT,`CMPB_EXT,`SBCB_EXT,`ANDB_EXT,`BITB_EXT,`LDB_EXT,`EORB_EXT,`ADCB_EXT,`ORB_EXT,`ADDB_EXT:
|
| 1614 |
|
|
begin
|
| 1615 |
|
|
load_what <= `LW_BL;
|
| 1616 |
|
|
radr <= ex_address;
|
| 1617 |
|
|
pc <= pc + (isFar ? 32'd4 : 32'd3);
|
| 1618 |
|
|
next_state(LOAD1);
|
| 1619 |
|
|
end
|
| 1620 |
|
|
`SUBD_EXT,`ADDD_EXT,`LDD_EXT,`CMPD_EXT,`ADCD_EXT,`SBCD_EXT:
|
| 1621 |
|
|
begin
|
| 1622 |
|
|
load_what <= `LW_BH;
|
| 1623 |
|
|
radr <= ex_address;
|
| 1624 |
|
|
pc <= pc + (isFar ? 32'd4 : 32'd3);
|
| 1625 |
|
|
next_state(LOAD1);
|
| 1626 |
|
|
end
|
| 1627 |
|
|
`CMPX_EXT,`LDX_EXT,`LDU_EXT,`LDS_EXT,
|
| 1628 |
|
|
`CMPY_EXT,`CMPS_EXT,`CMPU_EXT,`LDY_EXT:
|
| 1629 |
|
|
begin
|
| 1630 |
|
|
load_what <= `LW_BH;
|
| 1631 |
|
|
radr <= ex_address;
|
| 1632 |
|
|
pc <= pc + (isFar ? 32'd4 : 32'd3);
|
| 1633 |
|
|
next_state(LOAD1);
|
| 1634 |
|
|
end
|
| 1635 |
|
|
`CLR_EXT:
|
| 1636 |
|
|
begin
|
| 1637 |
|
|
ex_store(`SW_RES8);
|
| 1638 |
|
|
res12 <= 13'h000;
|
| 1639 |
|
|
end
|
| 1640 |
|
|
`STA_EXT: ex_store(`SW_ACCA);
|
| 1641 |
|
|
`STB_EXT: ex_store(`SW_ACCB);
|
| 1642 |
|
|
`STD_EXT: ex_store(`SW_ACCDH);
|
| 1643 |
|
|
`STU_EXT: ex_store(`SW_USPH);
|
| 1644 |
|
|
`STS_EXT: ex_store(`SW_SSPH);
|
| 1645 |
|
|
`STX_EXT: ex_store(`SW_XH);
|
| 1646 |
|
|
`STY_EXT: ex_store(`SW_YH);
|
| 1647 |
|
|
|
| 1648 |
|
|
`BSR:
|
| 1649 |
|
|
begin
|
| 1650 |
|
|
store_what <= `SW_PCH;
|
| 1651 |
|
|
wadr <= ssp - 2'd2;
|
| 1652 |
|
|
ssp <= ssp - 2'd2;
|
| 1653 |
|
|
pc <= pc + 2'd2;
|
| 1654 |
|
|
next_state(STORE1);
|
| 1655 |
|
|
end
|
| 1656 |
|
|
`LBSR:
|
| 1657 |
|
|
begin
|
| 1658 |
|
|
store_what <= `SW_PCH;
|
| 1659 |
|
|
wadr <= ssp - 2'd2;
|
| 1660 |
|
|
ssp <= ssp - 2'd2;
|
| 1661 |
|
|
pc <= pc + 2'd3;
|
| 1662 |
|
|
next_state(STORE1);
|
| 1663 |
|
|
end
|
| 1664 |
|
|
`JSR_DP:
|
| 1665 |
|
|
begin
|
| 1666 |
|
|
store_what <= `SW_PCH;
|
| 1667 |
|
|
wadr <= ssp - 2'd2;
|
| 1668 |
|
|
ssp <= ssp - 2'd2;
|
| 1669 |
|
|
pc <= pc + 2'd2;
|
| 1670 |
|
|
next_state(STORE1);
|
| 1671 |
|
|
end
|
| 1672 |
|
|
`JSR_NDX:
|
| 1673 |
|
|
begin
|
| 1674 |
|
|
begin
|
| 1675 |
|
|
store_what <= `SW_PCH;
|
| 1676 |
|
|
wadr <= ssp - 2'd2;
|
| 1677 |
|
|
ssp <= ssp - 2'd2;
|
| 1678 |
|
|
end
|
| 1679 |
|
|
pc <= pc + insnsz;
|
| 1680 |
|
|
next_state(STORE1);
|
| 1681 |
|
|
end
|
| 1682 |
|
|
`JSR_EXT:
|
| 1683 |
|
|
begin
|
| 1684 |
|
|
begin
|
| 1685 |
|
|
store_what <= `SW_PCH;
|
| 1686 |
|
|
wadr <= ssp - 2'd2;
|
| 1687 |
|
|
ssp <= ssp - 2'd2;
|
| 1688 |
|
|
end
|
| 1689 |
|
|
pc <= pc + 2'd3;
|
| 1690 |
|
|
next_state(STORE1);
|
| 1691 |
|
|
end
|
| 1692 |
|
|
`JSR_FAR:
|
| 1693 |
|
|
begin
|
| 1694 |
|
|
store_what <= `SW_PC2316;
|
| 1695 |
|
|
wadr <= ssp - 16'd4;
|
| 1696 |
|
|
ssp <= ssp - 16'd4;
|
| 1697 |
|
|
pc <= pc + 32'd4;
|
| 1698 |
|
|
next_state(STORE1);
|
| 1699 |
|
|
end
|
| 1700 |
|
|
`RTS:
|
| 1701 |
|
|
begin
|
| 1702 |
|
|
load_what <= `LW_PCH;
|
| 1703 |
|
|
radr <= ssp;
|
| 1704 |
|
|
next_state(LOAD1);
|
| 1705 |
|
|
end
|
| 1706 |
|
|
`RTF:
|
| 1707 |
|
|
begin
|
| 1708 |
|
|
load_what <= `LW_PC2316;
|
| 1709 |
|
|
radr <= ssp;
|
| 1710 |
|
|
next_state(LOAD1);
|
| 1711 |
|
|
end
|
| 1712 |
|
|
`JMP_DP: pc <= dp_address;
|
| 1713 |
|
|
`JMP_EXT: pc <= address;
|
| 1714 |
|
|
`JMP_FAR: pc <= far_address;
|
| 1715 |
|
|
`JMP_NDX:
|
| 1716 |
|
|
begin
|
| 1717 |
|
|
if (isIndirect) begin
|
| 1718 |
|
|
radr <= NdxAddr;
|
| 1719 |
|
|
if (isFar)
|
| 1720 |
|
|
load_what <= `LW_PC2316;
|
| 1721 |
|
|
else
|
| 1722 |
|
|
load_what <= `LW_PCH;
|
| 1723 |
|
|
next_state(LOAD1);
|
| 1724 |
|
|
end
|
| 1725 |
|
|
else
|
| 1726 |
|
|
pc <= isFar ? NdxAddr : {pc[`BYTE3],NdxAddr[`DBLBYTE]};
|
| 1727 |
|
|
end
|
| 1728 |
|
|
`LEAX_NDX,`LEAY_NDX,`LEAS_NDX,`LEAU_NDX:
|
| 1729 |
|
|
begin
|
| 1730 |
|
|
pc <= pc + insnsz;
|
| 1731 |
|
|
if (isIndirect) begin
|
| 1732 |
|
|
load_what <= `LW_IAH;
|
| 1733 |
|
|
radr <= NdxAddr;
|
| 1734 |
|
|
state <= LOAD1;
|
| 1735 |
|
|
end
|
| 1736 |
|
|
else
|
| 1737 |
|
|
res <= NdxAddr[`DBLBYTE];
|
| 1738 |
|
|
end
|
| 1739 |
|
|
`PSHU,`PSHS:
|
| 1740 |
|
|
begin
|
| 1741 |
|
|
next_state(PUSH1);
|
| 1742 |
|
|
pc <= pc + 2'd2;
|
| 1743 |
|
|
end
|
| 1744 |
|
|
`PULS:
|
| 1745 |
|
|
begin
|
| 1746 |
|
|
radr <= ssp;
|
| 1747 |
|
|
next_state(PULL1);
|
| 1748 |
|
|
pc <= pc + 2'd2;
|
| 1749 |
|
|
end
|
| 1750 |
|
|
`PULU:
|
| 1751 |
|
|
begin
|
| 1752 |
|
|
radr <= {usppg,8'h00} + usp;
|
| 1753 |
|
|
next_state(PULL1);
|
| 1754 |
|
|
pc <= pc + 2'd2;
|
| 1755 |
|
|
end
|
| 1756 |
|
|
`BEQ,`BNE,`BMI,`BPL,`BVS,`BVC,`BHI,`BLS,`BHS,`BLO,`BGT,`BGE,`BLT,`BLE,`BRA,`BRN:
|
| 1757 |
|
|
if (takb)
|
| 1758 |
|
|
pc <= pc + {{24{ir[BPBX2M1]}},ir[`HIBYTE]} + 2'd2;
|
| 1759 |
|
|
else
|
| 1760 |
|
|
pc <= pc + 2'd2;
|
| 1761 |
|
|
// PC is already incremented by one due to the PG10 prefix.
|
| 1762 |
|
|
`LBEQ,`LBNE,`LBMI,`LBPL,`LBVS,`LBVC,`LBHI,`LBLS,`LBHS,`LBLO,`LBGT,`LBGE,`LBLT,`LBLE,`LBRN:
|
| 1763 |
|
|
if (takb)
|
| 1764 |
|
|
pc <= pc + {{12{ir[BPB*3-1]}},ir[`HIBYTE],ir[`BYTE3]} + 2'd3;
|
| 1765 |
|
|
else
|
| 1766 |
|
|
pc <= pc + 2'd3;
|
| 1767 |
|
|
`LBRA: pc <= pc + {{12{ir[BPB*3-1]}},ir[`HIBYTE],ir[`BYTE3]} + 2'd3;
|
| 1768 |
|
|
`RTI:
|
| 1769 |
|
|
begin
|
| 1770 |
|
|
load_what <= `LW_CCR;
|
| 1771 |
|
|
radr <= ssp;
|
| 1772 |
|
|
isFar <= `TRUE;
|
| 1773 |
|
|
next_state(LOAD1);
|
| 1774 |
|
|
end
|
| 1775 |
|
|
`SWI:
|
| 1776 |
|
|
begin
|
| 1777 |
|
|
im <= 1'b1;
|
| 1778 |
|
|
firqim <= 1'b1;
|
| 1779 |
|
|
ir[`LOBYTE] <= `INT;
|
| 1780 |
|
|
ipg <= 2'b11;
|
| 1781 |
|
|
vect <= `SWI_VECT;
|
| 1782 |
|
|
next_state(DECODE);
|
| 1783 |
|
|
end
|
| 1784 |
|
|
`SWI2:
|
| 1785 |
|
|
begin
|
| 1786 |
|
|
ir[`LOBYTE] <= `INT;
|
| 1787 |
|
|
ipg <= 2'b11;
|
| 1788 |
|
|
vect <= `SWI2_VECT;
|
| 1789 |
|
|
next_state(DECODE);
|
| 1790 |
|
|
end
|
| 1791 |
|
|
`SWI3:
|
| 1792 |
|
|
begin
|
| 1793 |
|
|
ir[`LOBYTE] <= `INT;
|
| 1794 |
|
|
ipg <= 2'b11;
|
| 1795 |
|
|
vect <= `SWI3_VECT;
|
| 1796 |
|
|
next_state(DECODE);
|
| 1797 |
|
|
end
|
| 1798 |
|
|
// If the processor was in the wait state before the interrupt occurred
|
| 1799 |
|
|
// the registers will have already been pushed. All that needs to be
|
| 1800 |
|
|
// done is to vector to the interrupt routine.
|
| 1801 |
|
|
`INT:
|
| 1802 |
|
|
begin
|
| 1803 |
|
|
if (wait_state) begin
|
| 1804 |
|
|
wait_state <= `FALSE;
|
| 1805 |
|
|
if (vec_i != 24'h0) begin
|
| 1806 |
|
|
pc <= vec_i;
|
| 1807 |
|
|
next_state(IFETCH);
|
| 1808 |
|
|
end
|
| 1809 |
|
|
else begin
|
| 1810 |
|
|
radr <= vect;
|
| 1811 |
|
|
load_what <= `LW_PCH;
|
| 1812 |
|
|
pc <= 32'hFFFFFFFE;
|
| 1813 |
|
|
next_state(LOAD1);
|
| 1814 |
|
|
end
|
| 1815 |
|
|
end
|
| 1816 |
|
|
else begin
|
| 1817 |
|
|
if (isNMI | isIRQ | isSWI | isSWI2 | isSWI3) begin
|
| 1818 |
|
|
ir[`HIBYTE] <= 16'hFFFF;
|
| 1819 |
|
|
ef <= 1'b1;
|
| 1820 |
|
|
end
|
| 1821 |
|
|
else if (isFIRQ) begin
|
| 1822 |
|
|
if (natMd) begin
|
| 1823 |
|
|
ef <= firqMd;
|
| 1824 |
|
|
ir[`HIBYTE] <= firqMd ? 16'hFFFF : 12'h81;
|
| 1825 |
|
|
end
|
| 1826 |
|
|
else begin
|
| 1827 |
|
|
ir[`HIBYTE] <= 12'h81;
|
| 1828 |
|
|
ef <= 1'b0;
|
| 1829 |
|
|
end
|
| 1830 |
|
|
end
|
| 1831 |
|
|
pc <= pc;
|
| 1832 |
|
|
isFar <= `TRUE;
|
| 1833 |
|
|
next_state(PUSH1);
|
| 1834 |
|
|
end
|
| 1835 |
|
|
end
|
| 1836 |
|
|
default: ;
|
| 1837 |
|
|
endcase
|
| 1838 |
|
|
end
|
| 1839 |
|
|
endtask
|
| 1840 |
|
|
|
| 1841 |
|
|
// ============================================================================
|
| 1842 |
|
|
// MEMORY LOAD
|
| 1843 |
|
|
// ============================================================================
|
| 1844 |
|
|
task tLoad1;
|
| 1845 |
|
|
begin
|
| 1846 |
|
|
`ifdef SUPPORT_DCACHE
|
| 1847 |
|
|
if (unCachedData)
|
| 1848 |
|
|
`endif
|
| 1849 |
|
|
case(radr)
|
| 1850 |
|
|
{{BPB*3-8{1'b1}},8'hE0}: load_tsk({2'b0,id});
|
| 1851 |
|
|
{{BPB*3-8{1'b1}},8'hE1}: load_tsk(chkpoint);
|
| 1852 |
|
|
{{BPB*3-8{1'b1}},8'hE4}: load_tsk(12'h0);
|
| 1853 |
|
|
{{BPB*3-8{1'b1}},8'hE5}: load_tsk(ms_count[35:24]);
|
| 1854 |
|
|
{{BPB*3-8{1'b1}},8'hE6}: load_tsk(ms_count[23:12]);
|
| 1855 |
|
|
{{BPB*3-8{1'b1}},8'hE7}: load_tsk(ms_count[11: 0]);
|
| 1856 |
|
|
default:
|
| 1857 |
|
|
if (~ack_i) begin
|
| 1858 |
|
|
lock_o <= lock_bus;
|
| 1859 |
|
|
wb_read(radr);
|
| 1860 |
|
|
if (!tsc)
|
| 1861 |
|
|
next_state(LOAD2);
|
| 1862 |
|
|
end
|
| 1863 |
|
|
`ifdef SUPPORT_DCACHE
|
| 1864 |
|
|
else if (dhit)
|
| 1865 |
|
|
load_tsk(rdat);
|
| 1866 |
|
|
else begin
|
| 1867 |
|
|
retstate <= LOAD1;
|
| 1868 |
|
|
state <= DCACHE1;
|
| 1869 |
|
|
end
|
| 1870 |
|
|
`endif
|
| 1871 |
|
|
endcase
|
| 1872 |
|
|
end
|
| 1873 |
|
|
endtask
|
| 1874 |
|
|
|
| 1875 |
|
|
task tLoad2;
|
| 1876 |
|
|
begin
|
| 1877 |
|
|
// On a tri-state condition abort the bus cycle and retry the load.
|
| 1878 |
|
|
if (tsc|rty_i|bto) begin
|
| 1879 |
|
|
wb_nack();
|
| 1880 |
|
|
next_state(LOAD1);
|
| 1881 |
|
|
end
|
| 1882 |
|
|
else if (ack_i) begin
|
| 1883 |
|
|
wb_nack();
|
| 1884 |
|
|
load_tsk(dati);
|
| 1885 |
|
|
end
|
| 1886 |
|
|
`ifdef SUPPORT_BERR
|
| 1887 |
|
|
else if (err_i) begin
|
| 1888 |
|
|
lock_o <= 1'b0;
|
| 1889 |
|
|
wb_nack();
|
| 1890 |
|
|
derr_address <= adr_o;
|
| 1891 |
|
|
// intno <= 9'd508;
|
| 1892 |
|
|
state <= BUS_ERROR;
|
| 1893 |
|
|
end
|
| 1894 |
|
|
`endif
|
| 1895 |
|
|
end
|
| 1896 |
|
|
endtask
|
| 1897 |
|
|
|
| 1898 |
|
|
// ============================================================================
|
| 1899 |
|
|
// EXECUTE
|
| 1900 |
|
|
//
|
| 1901 |
|
|
// Perform calculations
|
| 1902 |
|
|
// ============================================================================
|
| 1903 |
|
|
task tExecute;
|
| 1904 |
|
|
begin
|
| 1905 |
|
|
next_state(IFETCH);
|
| 1906 |
|
|
case(ir12)
|
| 1907 |
|
|
`SUBD_DP,`SUBD_NDX,`SUBD_EXT,
|
| 1908 |
|
|
`CMPD_DP,`CMPD_NDX,`CMPD_EXT:
|
| 1909 |
|
|
begin
|
| 1910 |
|
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
| 1911 |
|
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - b[`DBLBYTE];
|
| 1912 |
|
|
end
|
| 1913 |
|
|
`SBCD_DP,`SBCD_NDX,`SBCD_EXT:
|
| 1914 |
|
|
begin
|
| 1915 |
|
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
| 1916 |
|
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - b[`DBLBYTE] - {23'b0,cf};
|
| 1917 |
|
|
end
|
| 1918 |
|
|
`ADDD_DP,`ADDD_NDX,`ADDD_EXT:
|
| 1919 |
|
|
begin
|
| 1920 |
|
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
| 1921 |
|
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + b[`DBLBYTE];
|
| 1922 |
|
|
end
|
| 1923 |
|
|
`ADCD_DP,`ADCD_NDX,`ADCD_EXT:
|
| 1924 |
|
|
begin
|
| 1925 |
|
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
| 1926 |
|
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + b[`DBLBYTE] + {23'b0,cf};
|
| 1927 |
|
|
end
|
| 1928 |
|
|
`LDD_DP,`LDD_NDX,`LDD_EXT:
|
| 1929 |
|
|
res <= b[`DBLBYTE];
|
| 1930 |
|
|
|
| 1931 |
|
|
`CMPA_DP,`CMPA_NDX,`CMPA_EXT,
|
| 1932 |
|
|
`SUBA_DP,`SUBA_NDX,`SUBA_EXT,
|
| 1933 |
|
|
`CMPB_DP,`CMPB_NDX,`CMPB_EXT,
|
| 1934 |
|
|
`SUBB_DP,`SUBB_NDX,`SUBB_EXT:
|
| 1935 |
|
|
begin
|
| 1936 |
|
|
a <= acc;
|
| 1937 |
|
|
res12 <= acc[`LOBYTE] - b12;
|
| 1938 |
|
|
end
|
| 1939 |
|
|
|
| 1940 |
|
|
`SBCA_DP,`SBCA_NDX,`SBCA_EXT,
|
| 1941 |
|
|
`SBCB_DP,`SBCB_NDX,`SBCB_EXT:
|
| 1942 |
|
|
begin
|
| 1943 |
|
|
a <= acc;
|
| 1944 |
|
|
res12 <= acc[`LOBYTE] - b12 - cf;
|
| 1945 |
|
|
end
|
| 1946 |
|
|
`BITA_DP,`BITA_NDX,`BITA_EXT,
|
| 1947 |
|
|
`ANDA_DP,`ANDA_NDX,`ANDA_EXT,
|
| 1948 |
|
|
`BITB_DP,`BITB_NDX,`BITB_EXT,
|
| 1949 |
|
|
`ANDB_DP,`ANDB_NDX,`ANDB_EXT:
|
| 1950 |
|
|
res12 <= acc[`LOBYTE] & b12;
|
| 1951 |
|
|
`LDA_DP,`LDA_NDX,`LDA_EXT,
|
| 1952 |
|
|
`LDB_DP,`LDB_NDX,`LDB_EXT:
|
| 1953 |
|
|
res12 <= b12;
|
| 1954 |
|
|
`EORA_DP,`EORA_NDX,`EORA_EXT,
|
| 1955 |
|
|
`EORB_DP,`EORB_NDX,`EORB_EXT:
|
| 1956 |
|
|
res12 <= acc[`LOBYTE] ^ b12;
|
| 1957 |
|
|
`ADCA_DP,`ADCA_NDX,`ADCA_EXT,
|
| 1958 |
|
|
`ADCB_DP,`ADCB_NDX,`ADCB_EXT:
|
| 1959 |
|
|
begin
|
| 1960 |
|
|
a <= acc;
|
| 1961 |
|
|
res12 <= acc[`LOBYTE] + b12 + cf;
|
| 1962 |
|
|
end
|
| 1963 |
|
|
`ORA_DP,`ORA_NDX,`ORA_EXT,
|
| 1964 |
|
|
`ORB_DP,`ORB_NDX,`ORB_EXT:
|
| 1965 |
|
|
res12 <= acc[`LOBYTE] | b12;
|
| 1966 |
|
|
`ADDA_DP,`ADDA_NDX,`ADDA_EXT,
|
| 1967 |
|
|
`ADDB_DP,`ADDB_NDX,`ADDB_EXT:
|
| 1968 |
|
|
begin
|
| 1969 |
|
|
a <= acc;
|
| 1970 |
|
|
res12 <= acc[`LOBYTE] + b12;
|
| 1971 |
|
|
end
|
| 1972 |
|
|
|
| 1973 |
|
|
`LDU_DP,`LDS_DP,`LDX_DP,`LDY_DP,
|
| 1974 |
|
|
`LDU_NDX,`LDS_NDX,`LDX_NDX,`LDY_NDX,
|
| 1975 |
|
|
`LDU_EXT,`LDS_EXT,`LDX_EXT,`LDY_EXT: res <= b[`DBLBYTE];
|
| 1976 |
|
|
`CMPX_DP,`CMPX_NDX,`CMPX_EXT: begin a <= xr; res <= xr[`DBLBYTE] - b[`DBLBYTE]; end
|
| 1977 |
|
|
`CMPY_DP,`CMPY_NDX,`CMPY_EXT: begin a <= yr; res <= yr[`DBLBYTE] - b[`DBLBYTE]; end
|
| 1978 |
|
|
`CMPS_DP,`CMPS_NDX,`CMPS_EXT: begin a <= ssp; res <= ssp[`DBLBYTE] - b[`DBLBYTE]; end
|
| 1979 |
|
|
`CMPU_DP,`CMPU_NDX,`CMPU_EXT: begin a <= usp; res <= usp[`DBLBYTE] - b[`DBLBYTE]; end
|
| 1980 |
|
|
|
| 1981 |
|
|
`NEG_DP,`NEG_NDX,`NEG_EXT: begin res12 <= -b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
| 1982 |
|
|
`COM_DP,`COM_NDX,`COM_EXT: begin res12 <= ~b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
| 1983 |
|
|
`LSR_DP,`LSR_NDX,`LSR_EXT: begin res12 <= {b[0],1'b0,b[BPBM1:1]}; store_what <= `SW_RES8; wadr <= radr; next_state(STORE1); end
|
| 1984 |
|
|
`ROR_DP,`ROR_NDX,`ROR_EXT: begin res12 <= {b[0],cf,b[BPBM1:1]}; store_what <= `SW_RES8; wadr <= radr; next_state(STORE1); end
|
| 1985 |
|
|
`ASR_DP,`ASR_NDX,`ASR_EXT: begin res12 <= {b[0],b[BPBM1],b[BPBM1:1]}; store_what <= `SW_RES8; wadr <= radr; next_state(STORE1); end
|
| 1986 |
|
|
`ASL_DP,`ASL_NDX,`ASL_EXT: begin res12 <= {b12,1'b0}; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
| 1987 |
|
|
`ROL_DP,`ROL_NDX,`ROL_EXT: begin res12 <= {b12,cf}; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
| 1988 |
|
|
`DEC_DP,`DEC_NDX,`DEC_EXT: begin res12 <= b12 - 2'd1; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
| 1989 |
|
|
`INC_DP,`INC_NDX,`INC_EXT: begin res12 <= b12 + 2'd1; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
| 1990 |
|
|
`TST_DP,`TST_NDX,`TST_EXT: res12 <= b12;
|
| 1991 |
|
|
/*
|
| 1992 |
|
|
`AIM_DP,`AIM_NDX,`AIM_EXT: begin res12 <= ir[`HIBYTE] & b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
| 1993 |
|
|
`OIM_DP,`OIM_NDX,`OIM_EXT: begin res12 <= ir[`HIBYTE] | b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
| 1994 |
|
|
`EIM_DP,`EIM_NDX,`OIM_EXT: begin res12 <= ir[`HIBYTE] ^ b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
| 1995 |
|
|
`TIM_DP,`TIM_NDX,`TIM_EXT: begin res12 <= ir[`HIBYTE] & b12; end
|
| 1996 |
|
|
*/
|
| 1997 |
|
|
default: ;
|
| 1998 |
|
|
endcase
|
| 1999 |
|
|
end
|
| 2000 |
|
|
endtask
|
| 2001 |
|
|
|
| 2002 |
|
|
// ============================================================================
|
| 2003 |
|
|
// MEMORY STORE
|
| 2004 |
|
|
// ============================================================================
|
| 2005 |
|
|
|
| 2006 |
|
|
task tStore1;
|
| 2007 |
|
|
begin
|
| 2008 |
|
|
if (!ack_i) begin
|
| 2009 |
|
|
lock_o <= lock_bus;
|
| 2010 |
|
|
`ifdef SUPPORT_CHECKPOINT
|
| 2011 |
|
|
if (wadr=={{BPB*3-8{1'b1}},8'hE1})
|
| 2012 |
|
|
next_state(IFETCH);
|
| 2013 |
|
|
else
|
| 2014 |
|
|
`endif
|
| 2015 |
|
|
begin
|
| 2016 |
|
|
case(store_what)
|
| 2017 |
|
|
`SW_ACCDH: wb_write(wadr,acca[`LOBYTE]);
|
| 2018 |
|
|
`SW_ACCDL: wb_write(wadr,accb[`LOBYTE]);
|
| 2019 |
|
|
`SW_ACCA: wb_write(wadr,acca[`LOBYTE]);
|
| 2020 |
|
|
`SW_ACCB: wb_write(wadr,accb[`LOBYTE]);
|
| 2021 |
|
|
`SW_DPR: wb_write(wadr,dpr);
|
| 2022 |
|
|
`SW_XL: wb_write(wadr,xr[`LOBYTE]);
|
| 2023 |
|
|
`SW_XH: wb_write(wadr,xr[`HIBYTE]);
|
| 2024 |
|
|
`SW_YL: wb_write(wadr,yr[`LOBYTE]);
|
| 2025 |
|
|
`SW_YH: wb_write(wadr,yr[`HIBYTE]);
|
| 2026 |
|
|
`SW_USPL: wb_write(wadr,usp[`LOBYTE]);
|
| 2027 |
|
|
`SW_USPH: wb_write(wadr,usp[`HIBYTE]);
|
| 2028 |
|
|
`SW_SSPL: wb_write(wadr,ssp[`LOBYTE]);
|
| 2029 |
|
|
`SW_SSPH: wb_write(wadr,ssp[`HIBYTE]);
|
| 2030 |
|
|
`SW_PC2316: wb_write(wadr,pc[`BYTE3]);
|
| 2031 |
|
|
`SW_PCH: wb_write(wadr,pc[`HIBYTE]);
|
| 2032 |
|
|
`SW_PCL: wb_write(wadr,pc[`LOBYTE]);
|
| 2033 |
|
|
`SW_CCR: wb_write(wadr,ccr);
|
| 2034 |
|
|
`SW_RES8: wb_write(wadr,res12[`LOBYTE]);
|
| 2035 |
|
|
`SW_RES16H: wb_write(wadr,res[`HIBYTE]);
|
| 2036 |
|
|
`SW_RES16L: wb_write(wadr,res[`LOBYTE]);
|
| 2037 |
|
|
`SW_DEF8: wb_write(wadr,wdat);
|
| 2038 |
|
|
default: wb_write(wadr,wdat);
|
| 2039 |
|
|
endcase
|
| 2040 |
|
|
`ifdef SUPPORT_DCACHE
|
| 2041 |
|
|
radr <= wadr; // Do a cache read to test the hit
|
| 2042 |
|
|
`endif
|
| 2043 |
|
|
if (!tsc)
|
| 2044 |
|
|
next_state(STORE2);
|
| 2045 |
|
|
end
|
| 2046 |
|
|
end
|
| 2047 |
|
|
end
|
| 2048 |
|
|
endtask
|
| 2049 |
|
|
|
| 2050 |
|
|
// Terminal state for stores. Update the data cache if there was a cache hit.
|
| 2051 |
|
|
// Clear any previously set lock status
|
| 2052 |
|
|
task tStore2;
|
| 2053 |
|
|
begin
|
| 2054 |
|
|
// On a tri-state condition abort the bus cycle and retry the store.
|
| 2055 |
|
|
if (tsc|rty_i|bto) begin
|
| 2056 |
|
|
wb_nack();
|
| 2057 |
|
|
next_state(STORE1);
|
| 2058 |
|
|
end
|
| 2059 |
|
|
else if (ack_i) begin
|
| 2060 |
|
|
wb_nack();
|
| 2061 |
|
|
wdat <= dat_o;
|
| 2062 |
|
|
wadr <= wadr + 2'd1;
|
| 2063 |
|
|
next_state(IFETCH);
|
| 2064 |
|
|
case(store_what)
|
| 2065 |
|
|
`SW_CCR:
|
| 2066 |
|
|
begin
|
| 2067 |
|
|
if (isINT) begin
|
| 2068 |
|
|
im <= 1'b1;
|
| 2069 |
|
|
firqim <= 1'b1;
|
| 2070 |
|
|
end
|
| 2071 |
|
|
next_state(PUSH2);
|
| 2072 |
|
|
end
|
| 2073 |
|
|
`SW_ACCA:
|
| 2074 |
|
|
if (isINT | isPSHS | isPSHU)
|
| 2075 |
|
|
next_state(PUSH2);
|
| 2076 |
|
|
else // STA
|
| 2077 |
|
|
next_state(IFETCH);
|
| 2078 |
|
|
`SW_ACCB:
|
| 2079 |
|
|
if (isINT | isPSHS | isPSHU)
|
| 2080 |
|
|
next_state(PUSH2);
|
| 2081 |
|
|
else // STB
|
| 2082 |
|
|
next_state(IFETCH);
|
| 2083 |
|
|
`SW_ACCDH:
|
| 2084 |
|
|
begin
|
| 2085 |
|
|
store_what <= `SW_ACCDL;
|
| 2086 |
|
|
next_state(STORE1);
|
| 2087 |
|
|
end
|
| 2088 |
|
|
`SW_ACCDL: next_state(IFETCH);
|
| 2089 |
|
|
`SW_DPR: next_state(PUSH2);
|
| 2090 |
|
|
`SW_XH:
|
| 2091 |
|
|
begin
|
| 2092 |
|
|
store_what <= `SW_XL;
|
| 2093 |
|
|
next_state(STORE1);
|
| 2094 |
|
|
end
|
| 2095 |
|
|
`SW_XL:
|
| 2096 |
|
|
if (isINT | isPSHS | isPSHU)
|
| 2097 |
|
|
next_state(PUSH2);
|
| 2098 |
|
|
else // STX
|
| 2099 |
|
|
next_state(IFETCH);
|
| 2100 |
|
|
`SW_YH:
|
| 2101 |
|
|
begin
|
| 2102 |
|
|
store_what <= `SW_YL;
|
| 2103 |
|
|
next_state(STORE1);
|
| 2104 |
|
|
end
|
| 2105 |
|
|
`SW_YL:
|
| 2106 |
|
|
if (isINT | isPSHS | isPSHU)
|
| 2107 |
|
|
next_state(PUSH2);
|
| 2108 |
|
|
else // STY
|
| 2109 |
|
|
next_state(IFETCH);
|
| 2110 |
|
|
`SW_USPH:
|
| 2111 |
|
|
begin
|
| 2112 |
|
|
store_what <= `SW_USPL;
|
| 2113 |
|
|
next_state(STORE1);
|
| 2114 |
|
|
end
|
| 2115 |
|
|
`SW_USPL:
|
| 2116 |
|
|
if (isINT | isPSHS | isPSHU)
|
| 2117 |
|
|
next_state(PUSH2);
|
| 2118 |
|
|
else // STU
|
| 2119 |
|
|
next_state(IFETCH);
|
| 2120 |
|
|
`SW_SSPH:
|
| 2121 |
|
|
begin
|
| 2122 |
|
|
store_what <= `SW_SSPL;
|
| 2123 |
|
|
next_state(STORE1);
|
| 2124 |
|
|
end
|
| 2125 |
|
|
`SW_SSPL:
|
| 2126 |
|
|
if (isINT | isPSHS | isPSHU)
|
| 2127 |
|
|
next_state(PUSH2);
|
| 2128 |
|
|
else // STS
|
| 2129 |
|
|
next_state(IFETCH);
|
| 2130 |
|
|
`SW_PC2316:
|
| 2131 |
|
|
begin
|
| 2132 |
|
|
store_what <= `SW_PCH;
|
| 2133 |
|
|
next_state(STORE1);
|
| 2134 |
|
|
end
|
| 2135 |
|
|
`SW_PCH:
|
| 2136 |
|
|
begin
|
| 2137 |
|
|
store_what <= `SW_PCL;
|
| 2138 |
|
|
next_state(STORE1);
|
| 2139 |
|
|
end
|
| 2140 |
|
|
`SW_PCL:
|
| 2141 |
|
|
if (isINT | isPSHS | isPSHU)
|
| 2142 |
|
|
next_state(PUSH2);
|
| 2143 |
|
|
else begin // JSR
|
| 2144 |
|
|
next_state(IFETCH);
|
| 2145 |
|
|
case(ir12)
|
| 2146 |
|
|
`BSR: pc <= pc + {{24{ir[BPBX2M1]}},ir[`HIBYTE]};
|
| 2147 |
|
|
`LBSR: pc <= pc + {{12{ir[BPB*3-1]}},ir[`HIBYTE],ir[`BYTE3]};
|
| 2148 |
|
|
`JSR_DP: pc <= {dpr,ir[`HIBYTE]};
|
| 2149 |
|
|
`JSR_EXT: pc <= {pc[`BYTE3],address[`DBLBYTE]};
|
| 2150 |
|
|
`JSR_FAR:
|
| 2151 |
|
|
begin
|
| 2152 |
|
|
pc <= far_address;
|
| 2153 |
|
|
$display("Loading PC with %h", far_address);
|
| 2154 |
|
|
end
|
| 2155 |
|
|
`JSR_NDX:
|
| 2156 |
|
|
begin
|
| 2157 |
|
|
if (isIndirect) begin
|
| 2158 |
|
|
radr <= NdxAddr;
|
| 2159 |
|
|
load_what <= isFar ? `LW_PC2316 : `LW_PCH;
|
| 2160 |
|
|
next_state(LOAD1);
|
| 2161 |
|
|
end
|
| 2162 |
|
|
else
|
| 2163 |
|
|
pc <= isFar ? NdxAddr : {pc[`BYTE3],NdxAddr[`DBLBYTE]};
|
| 2164 |
|
|
end
|
| 2165 |
|
|
endcase
|
| 2166 |
|
|
end
|
| 2167 |
|
|
endcase
|
| 2168 |
|
|
`ifdef SUPPORT_DCACHE
|
| 2169 |
|
|
if (!dhit && write_allocate) begin
|
| 2170 |
|
|
state <= DCACHE1;
|
| 2171 |
|
|
end
|
| 2172 |
|
|
`endif
|
| 2173 |
|
|
end
|
| 2174 |
|
|
`ifdef SUPPORT_BERR
|
| 2175 |
|
|
else if (err_i) begin
|
| 2176 |
|
|
lock_o <= 1'b0;
|
| 2177 |
|
|
wb_nack();
|
| 2178 |
|
|
state <= BUS_ERROR;
|
| 2179 |
|
|
end
|
| 2180 |
|
|
`endif
|
| 2181 |
|
|
end
|
| 2182 |
|
|
endtask
|
| 2183 |
|
|
|
| 2184 |
|
|
// ============================================================================
|
| 2185 |
|
|
// WRITEBACK
|
| 2186 |
|
|
//
|
| 2187 |
|
|
// Write results back to the register file and status flags.
|
| 2188 |
|
|
// Which registers and flags get updated depend on the instruction.
|
| 2189 |
|
|
// ============================================================================
|
| 2190 |
|
|
|
| 2191 |
|
|
task tWriteback;
|
| 2192 |
|
|
begin
|
| 2193 |
|
|
if (first_ifetch) begin
|
| 2194 |
|
|
first_ifetch <= `FALSE;
|
| 2195 |
|
|
case(ir12)
|
| 2196 |
|
|
`ABX: xr <= res;
|
| 2197 |
|
|
`ADDA_IMM,`ADDA_DP,`ADDA_NDX,`ADDA_EXT,
|
| 2198 |
|
|
`ADCA_IMM,`ADCA_DP,`ADCA_NDX,`ADCA_EXT:
|
| 2199 |
|
|
begin
|
| 2200 |
|
|
cf <= (a[BPBM1]&b[BPBM1])|(a[BPBM1]&~res12[BPBM1])|(b[BPBM1]&~res12[BPBM1]);
|
| 2201 |
|
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
| 2202 |
|
|
vf <= (res12[BPBM1] ^ b[BPBM1]) & (1'b1 ^ a[BPBM1] ^ b[BPBM1]);
|
| 2203 |
|
|
nf <= res12[BPBM1];
|
| 2204 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2205 |
|
|
acca <= res12[`LOBYTE];
|
| 2206 |
|
|
end
|
| 2207 |
|
|
`ADDB_IMM,`ADDB_DP,`ADDB_NDX,`ADDB_EXT,
|
| 2208 |
|
|
`ADCB_IMM,`ADCB_DP,`ADCB_NDX,`ADCB_EXT:
|
| 2209 |
|
|
begin
|
| 2210 |
|
|
cf <= (a[BPBM1]&b[BPBM1])|(a[BPBM1]&~res12[BPBM1])|(b[BPBM1]&~res12[BPBM1]);
|
| 2211 |
|
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
| 2212 |
|
|
vf <= (res12[BPBM1] ^ b[BPBM1]) & (1'b1 ^ a[BPBM1] ^ b[BPBM1]);
|
| 2213 |
|
|
nf <= res12[BPBM1];
|
| 2214 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2215 |
|
|
accb <= res12[`LOBYTE];
|
| 2216 |
|
|
end
|
| 2217 |
|
|
`ADDD_IMM,`ADDD_DP,`ADDD_NDX,`ADDD_EXT:
|
| 2218 |
|
|
begin
|
| 2219 |
|
|
cf <= (a[BPBX2M1]&b[BPBX2M1])|(a[BPBX2M1]&~res[BPBX2M1])|(b[BPBX2M1]&~res[BPBX2M1]);
|
| 2220 |
|
|
vf <= (res[BPBX2M1] ^ b[BPBX2M1]) & (1'b1 ^ a[BPBX2M1] ^ b[BPBX2M1]);
|
| 2221 |
|
|
nf <= res[BPBX2M1];
|
| 2222 |
|
|
zf <= res[`DBLBYTE]==24'h000000;
|
| 2223 |
|
|
acca <= res[`HIBYTE];
|
| 2224 |
|
|
accb <= res[`LOBYTE];
|
| 2225 |
|
|
end
|
| 2226 |
|
|
`ANDA_IMM,`ANDA_DP,`ANDA_NDX,`ANDA_EXT:
|
| 2227 |
|
|
begin
|
| 2228 |
|
|
nf <= res12n;
|
| 2229 |
|
|
zf <= res12z;
|
| 2230 |
|
|
vf <= 1'b0;
|
| 2231 |
|
|
acca <= res12[`LOBYTE];
|
| 2232 |
|
|
end
|
| 2233 |
|
|
`ANDB_IMM,`ANDB_DP,`ANDB_NDX,`ANDB_EXT:
|
| 2234 |
|
|
begin
|
| 2235 |
|
|
nf <= res12n;
|
| 2236 |
|
|
zf <= res12z;
|
| 2237 |
|
|
vf <= 1'b0;
|
| 2238 |
|
|
accb <= res12[`LOBYTE];
|
| 2239 |
|
|
end
|
| 2240 |
|
|
`ASLA:
|
| 2241 |
|
|
begin
|
| 2242 |
|
|
cf <= res12c;
|
| 2243 |
|
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
| 2244 |
|
|
vf <= res12[BPBM1] ^ res12[bitsPerByte];
|
| 2245 |
|
|
nf <= res12[BPBM1];
|
| 2246 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2247 |
|
|
acca <= res12[`LOBYTE];
|
| 2248 |
|
|
end
|
| 2249 |
|
|
`ASLB:
|
| 2250 |
|
|
begin
|
| 2251 |
|
|
cf <= res12c;
|
| 2252 |
|
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
| 2253 |
|
|
vf <= res12[BPBM1] ^ res12[bitsPerByte];
|
| 2254 |
|
|
nf <= res12[BPBM1];
|
| 2255 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2256 |
|
|
accb <= res12[`LOBYTE];
|
| 2257 |
|
|
end
|
| 2258 |
|
|
`ASL_DP,`ASL_NDX,`ASL_EXT:
|
| 2259 |
|
|
begin
|
| 2260 |
|
|
cf <= res12c;
|
| 2261 |
|
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
| 2262 |
|
|
vf <= res12[BPBM1] ^ res12[bitsPerByte];
|
| 2263 |
|
|
nf <= res12[BPBM1];
|
| 2264 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2265 |
|
|
end
|
| 2266 |
|
|
`ASRA:
|
| 2267 |
|
|
begin
|
| 2268 |
|
|
cf <= res12c;
|
| 2269 |
|
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
| 2270 |
|
|
nf <= res12[BPBM1];
|
| 2271 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2272 |
|
|
acca <= res12[`LOBYTE];
|
| 2273 |
|
|
end
|
| 2274 |
|
|
`ASRB:
|
| 2275 |
|
|
begin
|
| 2276 |
|
|
cf <= res12c;
|
| 2277 |
|
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
| 2278 |
|
|
nf <= res12[BPBM1];
|
| 2279 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2280 |
|
|
accb <= res12[`LOBYTE];
|
| 2281 |
|
|
end
|
| 2282 |
|
|
`ASR_DP,`ASR_NDX,`ASR_EXT:
|
| 2283 |
|
|
begin
|
| 2284 |
|
|
cf <= res12c;
|
| 2285 |
|
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
| 2286 |
|
|
nf <= res12[BPBM1];
|
| 2287 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2288 |
|
|
end
|
| 2289 |
|
|
`BITA_IMM,`BITA_DP,`BITA_NDX,`BITA_EXT,
|
| 2290 |
|
|
`BITB_IMM,`BITB_DP,`BITB_NDX,`BITB_EXT:
|
| 2291 |
|
|
begin
|
| 2292 |
|
|
vf <= 1'b0;
|
| 2293 |
|
|
nf <= res12[BPBM1];
|
| 2294 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2295 |
|
|
end
|
| 2296 |
|
|
`CLRA:
|
| 2297 |
|
|
begin
|
| 2298 |
|
|
vf <= 1'b0;
|
| 2299 |
|
|
cf <= 1'b0;
|
| 2300 |
|
|
nf <= 1'b0;
|
| 2301 |
|
|
zf <= 1'b1;
|
| 2302 |
|
|
acca <= 12'h000;
|
| 2303 |
|
|
end
|
| 2304 |
|
|
`CLRB:
|
| 2305 |
|
|
begin
|
| 2306 |
|
|
vf <= 1'b0;
|
| 2307 |
|
|
cf <= 1'b0;
|
| 2308 |
|
|
nf <= 1'b0;
|
| 2309 |
|
|
zf <= 1'b1;
|
| 2310 |
|
|
accb <= 12'h000;
|
| 2311 |
|
|
end
|
| 2312 |
|
|
`CLR_DP,`CLR_NDX,`CLR_EXT:
|
| 2313 |
|
|
begin
|
| 2314 |
|
|
vf <= 1'b0;
|
| 2315 |
|
|
cf <= 1'b0;
|
| 2316 |
|
|
nf <= 1'b0;
|
| 2317 |
|
|
zf <= 1'b1;
|
| 2318 |
|
|
end
|
| 2319 |
|
|
`CMPA_IMM,`CMPA_DP,`CMPA_NDX,`CMPA_EXT,
|
| 2320 |
|
|
`CMPB_IMM,`CMPB_DP,`CMPB_NDX,`CMPB_EXT:
|
| 2321 |
|
|
begin
|
| 2322 |
|
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
| 2323 |
|
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
| 2324 |
|
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
| 2325 |
|
|
nf <= res12[BPBM1];
|
| 2326 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2327 |
|
|
end
|
| 2328 |
|
|
`CMPD_IMM,`CMPD_DP,`CMPD_NDX,`CMPD_EXT:
|
| 2329 |
|
|
begin
|
| 2330 |
|
|
cf <= (~a[BPBX2M1]&b[BPBX2M1])|(res[BPBX2M1]&~a[BPBX2M1])|(res[BPBX2M1]&b[BPBX2M1]);
|
| 2331 |
|
|
vf <= (1'b1 ^ res[BPBX2M1] ^ b[BPBX2M1]) & (a[BPBX2M1] ^ b[BPBX2M1]);
|
| 2332 |
|
|
nf <= res[BPBX2M1];
|
| 2333 |
|
|
zf <= res[`DBLBYTE]==24'h000000;
|
| 2334 |
|
|
end
|
| 2335 |
|
|
`CMPS_IMM,`CMPS_DP,`CMPS_NDX,`CMPS_EXT,
|
| 2336 |
|
|
`CMPU_IMM,`CMPU_DP,`CMPU_NDX,`CMPU_EXT,
|
| 2337 |
|
|
`CMPX_IMM,`CMPX_DP,`CMPX_NDX,`CMPX_EXT,
|
| 2338 |
|
|
`CMPY_IMM,`CMPY_DP,`CMPY_NDX,`CMPY_EXT:
|
| 2339 |
|
|
begin
|
| 2340 |
|
|
cf <= (~a[BPBX2M1]&b[BPBX2M1])|(res[BPBX2M1]&~a[BPBX2M1])|(res[BPBX2M1]&b[BPBX2M1]);
|
| 2341 |
|
|
vf <= (1'b1 ^ res[BPBX2M1] ^ b[BPBX2M1]) & (a[BPBX2M1] ^ b[BPBX2M1]);
|
| 2342 |
|
|
nf <= res[BPBX2M1];
|
| 2343 |
|
|
zf <= res[`DBLBYTE]==24'h000000;
|
| 2344 |
|
|
end
|
| 2345 |
|
|
`COMA:
|
| 2346 |
|
|
begin
|
| 2347 |
|
|
cf <= 1'b1;
|
| 2348 |
|
|
vf <= 1'b0;
|
| 2349 |
|
|
nf <= res12n;
|
| 2350 |
|
|
zf <= res12z;
|
| 2351 |
|
|
acca <= res12[`LOBYTE];
|
| 2352 |
|
|
end
|
| 2353 |
|
|
`COMB:
|
| 2354 |
|
|
begin
|
| 2355 |
|
|
cf <= 1'b1;
|
| 2356 |
|
|
vf <= 1'b0;
|
| 2357 |
|
|
nf <= res12n;
|
| 2358 |
|
|
zf <= res12z;
|
| 2359 |
|
|
accb <= res12[`LOBYTE];
|
| 2360 |
|
|
end
|
| 2361 |
|
|
`COM_DP,`COM_NDX,`COM_EXT:
|
| 2362 |
|
|
begin
|
| 2363 |
|
|
cf <= 1'b1;
|
| 2364 |
|
|
vf <= 1'b0;
|
| 2365 |
|
|
nf <= res12n;
|
| 2366 |
|
|
zf <= res12z;
|
| 2367 |
|
|
end
|
| 2368 |
|
|
`DAA:
|
| 2369 |
|
|
begin
|
| 2370 |
|
|
cf <= res12c;
|
| 2371 |
|
|
zf <= res12z;
|
| 2372 |
|
|
nf <= res12n;
|
| 2373 |
|
|
vf <= (res12[BPBM1] ^ b[BPBM1]) & (1'b1 ^ a[BPBM1] ^ b[BPBM1]);
|
| 2374 |
|
|
acca <= res12[`LOBYTE];
|
| 2375 |
|
|
end
|
| 2376 |
|
|
`DECA:
|
| 2377 |
|
|
begin
|
| 2378 |
|
|
nf <= res12n;
|
| 2379 |
|
|
zf <= res12z;
|
| 2380 |
|
|
vf <= res12[BPBM1] != acca[BPBM1];
|
| 2381 |
|
|
acca <= res12[`LOBYTE];
|
| 2382 |
|
|
end
|
| 2383 |
|
|
`DECB:
|
| 2384 |
|
|
begin
|
| 2385 |
|
|
nf <= res12n;
|
| 2386 |
|
|
zf <= res12z;
|
| 2387 |
|
|
vf <= res12[BPBM1] != accb[BPBM1];
|
| 2388 |
|
|
accb <= res12[`LOBYTE];
|
| 2389 |
|
|
end
|
| 2390 |
|
|
`DEC_DP,`DEC_NDX,`DEC_EXT:
|
| 2391 |
|
|
begin
|
| 2392 |
|
|
nf <= res12n;
|
| 2393 |
|
|
zf <= res12z;
|
| 2394 |
|
|
vf <= res12[BPBM1] != b[BPBM1];
|
| 2395 |
|
|
end
|
| 2396 |
|
|
`EORA_IMM,`EORA_DP,`EORA_NDX,`EORA_EXT,
|
| 2397 |
|
|
`ORA_IMM,`ORA_DP,`ORA_NDX,`ORA_EXT:
|
| 2398 |
|
|
begin
|
| 2399 |
|
|
nf <= res12n;
|
| 2400 |
|
|
zf <= res12z;
|
| 2401 |
|
|
vf <= 1'b0;
|
| 2402 |
|
|
acca <= res12[`LOBYTE];
|
| 2403 |
|
|
end
|
| 2404 |
|
|
`EORB_IMM,`EORB_DP,`EORB_NDX,`EORB_EXT,
|
| 2405 |
|
|
`ORB_IMM,`ORB_DP,`ORB_NDX,`ORB_EXT:
|
| 2406 |
|
|
begin
|
| 2407 |
|
|
nf <= res12n;
|
| 2408 |
|
|
zf <= res12z;
|
| 2409 |
|
|
vf <= 1'b0;
|
| 2410 |
|
|
accb <= res12[`LOBYTE];
|
| 2411 |
|
|
end
|
| 2412 |
|
|
`EXG:
|
| 2413 |
|
|
begin
|
| 2414 |
|
|
case(ir[bitsPerByte+3:bitsPerByte])
|
| 2415 |
|
|
4'b0000:
|
| 2416 |
|
|
begin
|
| 2417 |
|
|
acca <= src1[`HIBYTE];
|
| 2418 |
|
|
accb <= src1[`LOBYTE];
|
| 2419 |
|
|
end
|
| 2420 |
|
|
4'b0001: xr <= src1;
|
| 2421 |
|
|
4'b0010: yr <= src1;
|
| 2422 |
|
|
4'b0011: usp <= src1;
|
| 2423 |
|
|
4'b0100: begin ssp <= src1; nmi_armed <= `TRUE; end
|
| 2424 |
|
|
4'b0101: pc <= src1[`DBLBYTE];
|
| 2425 |
|
|
4'b1000: acca <= src1[`LOBYTE];
|
| 2426 |
|
|
4'b1001: accb <= src1[`LOBYTE];
|
| 2427 |
|
|
4'b1010:
|
| 2428 |
|
|
begin
|
| 2429 |
|
|
cf <= src1[0];
|
| 2430 |
|
|
vf <= src1[1];
|
| 2431 |
|
|
zf <= src1[2];
|
| 2432 |
|
|
nf <= src1[3];
|
| 2433 |
|
|
im <= src1[4];
|
| 2434 |
|
|
hf <= src1[5];
|
| 2435 |
|
|
firqim <= src1[6];
|
| 2436 |
|
|
ef <= src1[7];
|
| 2437 |
|
|
end
|
| 2438 |
|
|
4'b1011: dpr <= src1[`LOBYTE];
|
| 2439 |
|
|
4'b1110: usppg <= src1[`DBLBYTE];
|
| 2440 |
|
|
4'b1111: ;
|
| 2441 |
|
|
default: ;
|
| 2442 |
|
|
endcase
|
| 2443 |
|
|
case(ir[bitsPerByte+7:bitsPerByte+4])
|
| 2444 |
|
|
4'b0000:
|
| 2445 |
|
|
begin
|
| 2446 |
|
|
acca <= src2[`HIBYTE];
|
| 2447 |
|
|
accb <= src2[`LOBYTE];
|
| 2448 |
|
|
end
|
| 2449 |
|
|
4'b0001: xr <= src2;
|
| 2450 |
|
|
4'b0010: yr <= src2;
|
| 2451 |
|
|
4'b0011: usp <= src2;
|
| 2452 |
|
|
4'b0100: begin ssp <= src2; nmi_armed <= `TRUE; end
|
| 2453 |
|
|
4'b0101: pc <= src2[`DBLBYTE];
|
| 2454 |
|
|
4'b1000: acca <= src2[`LOBYTE];
|
| 2455 |
|
|
4'b1001: accb <= src2[`LOBYTE];
|
| 2456 |
|
|
4'b1010:
|
| 2457 |
|
|
begin
|
| 2458 |
|
|
cf <= src2[0];
|
| 2459 |
|
|
vf <= src2[1];
|
| 2460 |
|
|
zf <= src2[2];
|
| 2461 |
|
|
nf <= src2[3];
|
| 2462 |
|
|
im <= src2[4];
|
| 2463 |
|
|
hf <= src2[5];
|
| 2464 |
|
|
firqim <= src2[6];
|
| 2465 |
|
|
ef <= src2[7];
|
| 2466 |
|
|
end
|
| 2467 |
|
|
4'b1011: dpr <= src2[`LOBYTE];
|
| 2468 |
|
|
4'b1110: usppg <= src2[`DBLBYTE];
|
| 2469 |
|
|
4'b1111: ;
|
| 2470 |
|
|
default: ;
|
| 2471 |
|
|
endcase
|
| 2472 |
|
|
end
|
| 2473 |
|
|
`INCA:
|
| 2474 |
|
|
begin
|
| 2475 |
|
|
nf <= res12n;
|
| 2476 |
|
|
zf <= res12z;
|
| 2477 |
|
|
vf <= res12[BPBM1] != acca[BPBM1];
|
| 2478 |
|
|
acca <= res12[`LOBYTE];
|
| 2479 |
|
|
end
|
| 2480 |
|
|
`INCB:
|
| 2481 |
|
|
begin
|
| 2482 |
|
|
nf <= res12n;
|
| 2483 |
|
|
zf <= res12z;
|
| 2484 |
|
|
vf <= res12[BPBM1] != accb[BPBM1];
|
| 2485 |
|
|
accb <= res12[`LOBYTE];
|
| 2486 |
|
|
end
|
| 2487 |
|
|
`INC_DP,`INC_NDX,`INC_EXT:
|
| 2488 |
|
|
begin
|
| 2489 |
|
|
nf <= res12n;
|
| 2490 |
|
|
zf <= res12z;
|
| 2491 |
|
|
vf <= res12[BPBM1] != b[BPBM1];
|
| 2492 |
|
|
end
|
| 2493 |
|
|
`LDA_IMM,`LDA_DP,`LDA_NDX,`LDA_EXT:
|
| 2494 |
|
|
begin
|
| 2495 |
|
|
vf <= 1'b0;
|
| 2496 |
|
|
zf <= res12z;
|
| 2497 |
|
|
nf <= res12n;
|
| 2498 |
|
|
acca <= res12[`LOBYTE];
|
| 2499 |
|
|
end
|
| 2500 |
|
|
`LDB_IMM,`LDB_DP,`LDB_NDX,`LDB_EXT:
|
| 2501 |
|
|
begin
|
| 2502 |
|
|
vf <= 1'b0;
|
| 2503 |
|
|
zf <= res12z;
|
| 2504 |
|
|
nf <= res12n;
|
| 2505 |
|
|
accb <= res12[`LOBYTE];
|
| 2506 |
|
|
end
|
| 2507 |
|
|
`LDD_IMM,`LDD_DP,`LDD_NDX,`LDD_EXT:
|
| 2508 |
|
|
begin
|
| 2509 |
|
|
vf <= 1'b0;
|
| 2510 |
|
|
zf <= res24z;
|
| 2511 |
|
|
nf <= res24n;
|
| 2512 |
|
|
acca <= res[`HIBYTE];
|
| 2513 |
|
|
accb <= res[`LOBYTE];
|
| 2514 |
|
|
end
|
| 2515 |
|
|
`LDU_IMM,`LDU_DP,`LDU_NDX,`LDU_EXT:
|
| 2516 |
|
|
begin
|
| 2517 |
|
|
vf <= 1'b0;
|
| 2518 |
|
|
zf <= res24z;
|
| 2519 |
|
|
nf <= res24n;
|
| 2520 |
|
|
usp <= res[`DBLBYTE];
|
| 2521 |
|
|
end
|
| 2522 |
|
|
`LDS_IMM,`LDS_DP,`LDS_NDX,`LDS_EXT:
|
| 2523 |
|
|
begin
|
| 2524 |
|
|
vf <= 1'b0;
|
| 2525 |
|
|
zf <= res24z;
|
| 2526 |
|
|
nf <= res24n;
|
| 2527 |
|
|
ssp <= res[`DBLBYTE];
|
| 2528 |
|
|
nmi_armed <= 1'b1;
|
| 2529 |
|
|
end
|
| 2530 |
|
|
`LDX_IMM,`LDX_DP,`LDX_NDX,`LDX_EXT:
|
| 2531 |
|
|
begin
|
| 2532 |
|
|
vf <= 1'b0;
|
| 2533 |
|
|
zf <= res24z;
|
| 2534 |
|
|
nf <= res24n;
|
| 2535 |
|
|
xr <= res[`DBLBYTE];
|
| 2536 |
|
|
end
|
| 2537 |
|
|
`LDY_IMM,`LDY_DP,`LDY_NDX,`LDY_EXT:
|
| 2538 |
|
|
begin
|
| 2539 |
|
|
vf <= 1'b0;
|
| 2540 |
|
|
zf <= res24z;
|
| 2541 |
|
|
nf <= res24n;
|
| 2542 |
|
|
yr <= res[`DBLBYTE];
|
| 2543 |
|
|
end
|
| 2544 |
|
|
`LEAS_NDX:
|
| 2545 |
|
|
begin ssp <= res[`DBLBYTE]; nmi_armed <= 1'b1; end
|
| 2546 |
|
|
`LEAU_NDX:
|
| 2547 |
|
|
usp <= res[`DBLBYTE];
|
| 2548 |
|
|
`LEAX_NDX:
|
| 2549 |
|
|
begin
|
| 2550 |
|
|
zf <= res24z;
|
| 2551 |
|
|
xr <= res[`DBLBYTE];
|
| 2552 |
|
|
end
|
| 2553 |
|
|
`LEAY_NDX:
|
| 2554 |
|
|
begin
|
| 2555 |
|
|
zf <= res24z;
|
| 2556 |
|
|
yr <= res[`DBLBYTE];
|
| 2557 |
|
|
end
|
| 2558 |
|
|
`LSRA:
|
| 2559 |
|
|
begin
|
| 2560 |
|
|
cf <= res12c;
|
| 2561 |
|
|
nf <= res12[BPBM1];
|
| 2562 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2563 |
|
|
acca <= res12[`LOBYTE];
|
| 2564 |
|
|
end
|
| 2565 |
|
|
`LSRB:
|
| 2566 |
|
|
begin
|
| 2567 |
|
|
cf <= res12c;
|
| 2568 |
|
|
nf <= res12[BPBM1];
|
| 2569 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2570 |
|
|
accb <= res12[`LOBYTE];
|
| 2571 |
|
|
end
|
| 2572 |
|
|
`LSR_DP,`LSR_NDX,`LSR_EXT:
|
| 2573 |
|
|
begin
|
| 2574 |
|
|
cf <= res12c;
|
| 2575 |
|
|
nf <= res12[BPBM1];
|
| 2576 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2577 |
|
|
end
|
| 2578 |
|
|
`MUL:
|
| 2579 |
|
|
begin
|
| 2580 |
|
|
cf <= prod[BPBM1];
|
| 2581 |
|
|
zf <= res24z;
|
| 2582 |
|
|
acca <= prod[`HIBYTE];
|
| 2583 |
|
|
accb <= prod[`LOBYTE];
|
| 2584 |
|
|
end
|
| 2585 |
|
|
`NEGA:
|
| 2586 |
|
|
begin
|
| 2587 |
|
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
| 2588 |
|
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
| 2589 |
|
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
| 2590 |
|
|
nf <= res12[BPBM1];
|
| 2591 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2592 |
|
|
acca <= res12[`LOBYTE];
|
| 2593 |
|
|
end
|
| 2594 |
|
|
`NEGB:
|
| 2595 |
|
|
begin
|
| 2596 |
|
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
| 2597 |
|
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
| 2598 |
|
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
| 2599 |
|
|
nf <= res12[BPBM1];
|
| 2600 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2601 |
|
|
accb <= res12[`LOBYTE];
|
| 2602 |
|
|
end
|
| 2603 |
|
|
`NEG_DP,`NEG_NDX,`NEG_EXT:
|
| 2604 |
|
|
begin
|
| 2605 |
|
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
| 2606 |
|
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
| 2607 |
|
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
| 2608 |
|
|
nf <= res12[BPBM1];
|
| 2609 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2610 |
|
|
end
|
| 2611 |
|
|
`ROLA:
|
| 2612 |
|
|
begin
|
| 2613 |
|
|
cf <= res12c;
|
| 2614 |
|
|
vf <= res12[BPBM1] ^ res12[bitsPerByte];
|
| 2615 |
|
|
nf <= res12[BPBM1];
|
| 2616 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2617 |
|
|
acca <= res12[`LOBYTE];
|
| 2618 |
|
|
end
|
| 2619 |
|
|
`ROLB:
|
| 2620 |
|
|
begin
|
| 2621 |
|
|
cf <= res12c;
|
| 2622 |
|
|
vf <= res12[BPBM1] ^ res12[bitsPerByte];
|
| 2623 |
|
|
nf <= res12[BPBM1];
|
| 2624 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2625 |
|
|
accb <= res12[`LOBYTE];
|
| 2626 |
|
|
end
|
| 2627 |
|
|
`ROL_DP,`ROL_NDX,`ROL_EXT:
|
| 2628 |
|
|
begin
|
| 2629 |
|
|
cf <= res12c;
|
| 2630 |
|
|
vf <= res12[BPBM1] ^ res12[bitsPerByte];
|
| 2631 |
|
|
nf <= res12[BPBM1];
|
| 2632 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2633 |
|
|
end
|
| 2634 |
|
|
`RORA:
|
| 2635 |
|
|
begin
|
| 2636 |
|
|
cf <= res12c;
|
| 2637 |
|
|
vf <= res12[BPBM1] ^ res12[bitsPerByte];
|
| 2638 |
|
|
nf <= res12[BPBM1];
|
| 2639 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2640 |
|
|
acca <= res12[`LOBYTE];
|
| 2641 |
|
|
end
|
| 2642 |
|
|
`RORB:
|
| 2643 |
|
|
begin
|
| 2644 |
|
|
cf <= res12c;
|
| 2645 |
|
|
vf <= res12[BPBM1] ^ res12[bitsPerByte];
|
| 2646 |
|
|
nf <= res12[BPBM1];
|
| 2647 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2648 |
|
|
accb <= res12[`LOBYTE];
|
| 2649 |
|
|
end
|
| 2650 |
|
|
`ROR_DP,`ROR_NDX,`ROR_EXT:
|
| 2651 |
|
|
begin
|
| 2652 |
|
|
cf <= res12c;
|
| 2653 |
|
|
vf <= res12[BPBM1] ^ res12[bitsPerByte];
|
| 2654 |
|
|
nf <= res12[BPBM1];
|
| 2655 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2656 |
|
|
end
|
| 2657 |
|
|
`SBCA_IMM,`SBCA_DP,`SBCA_NDX,`SBCA_EXT:
|
| 2658 |
|
|
begin
|
| 2659 |
|
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
| 2660 |
|
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
| 2661 |
|
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
| 2662 |
|
|
nf <= res12[BPBM1];
|
| 2663 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2664 |
|
|
acca <= res12[`LOBYTE];
|
| 2665 |
|
|
end
|
| 2666 |
|
|
`SBCB_IMM,`SBCB_DP,`SBCB_NDX,`SBCB_EXT:
|
| 2667 |
|
|
begin
|
| 2668 |
|
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
| 2669 |
|
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
| 2670 |
|
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
| 2671 |
|
|
nf <= res12[BPBM1];
|
| 2672 |
|
|
zf <= res12[`LOBYTE]==12'h000;
|
| 2673 |
|
|
accb <= res12[`LOBYTE];
|
| 2674 |
|
|
end
|
| 2675 |
|
|
`SEX:
|
| 2676 |
|
|
begin
|
| 2677 |
|
|
vf <= 1'b0;
|
| 2678 |
|
|
nf <= res12n;
|
| 2679 |
|
|
zf <= res12z;
|
| 2680 |
|
|
acca <= res12[`LOBYTE];
|
| 2681 |
|
|
end
|
| 2682 |
|
|
`STA_DP,`STA_NDX,`STA_EXT,
|
| 2683 |
|
|
`STB_DP,`STB_NDX,`STB_EXT:
|
| 2684 |
|
|
begin
|
| 2685 |
|
|
vf <= 1'b0;
|
| 2686 |
|
|
zf <= res12z;
|
| 2687 |
|
|
nf <= res12n;
|
| 2688 |
|
|
end
|
| 2689 |
|
|
`STD_DP,`STD_NDX,`STD_EXT,
|
| 2690 |
|
|
`STU_DP,`STU_NDX,`STU_EXT,
|
| 2691 |
|
|
`STX_DP,`STX_NDX,`STX_EXT,
|
| 2692 |
|
|
`STY_DP,`STY_NDX,`STY_EXT:
|
| 2693 |
|
|
begin
|
| 2694 |
|
|
vf <= 1'b0;
|
| 2695 |
|
|
zf <= res24z;
|
| 2696 |
|
|
nf <= res24n;
|
| 2697 |
|
|
end
|
| 2698 |
|
|
`TFR:
|
| 2699 |
|
|
begin
|
| 2700 |
|
|
case(ir[bitsPerByte+3:bitsPerByte])
|
| 2701 |
|
|
4'b0000:
|
| 2702 |
|
|
begin
|
| 2703 |
|
|
acca <= src1[`HIBYTE];
|
| 2704 |
|
|
accb <= src1[`LOBYTE];
|
| 2705 |
|
|
end
|
| 2706 |
|
|
4'b0001: xr <= src1;
|
| 2707 |
|
|
4'b0010: yr <= src1;
|
| 2708 |
|
|
4'b0011: usp <= src1;
|
| 2709 |
|
|
4'b0100: begin ssp <= src1; nmi_armed <= `TRUE; end
|
| 2710 |
|
|
4'b0101: pc <= src1[`DBLBYTE];
|
| 2711 |
|
|
4'b1000: acca <= src1[`LOBYTE];
|
| 2712 |
|
|
4'b1001: accb <= src1[`LOBYTE];
|
| 2713 |
|
|
4'b1010:
|
| 2714 |
|
|
begin
|
| 2715 |
|
|
cf <= src1[0];
|
| 2716 |
|
|
vf <= src1[1];
|
| 2717 |
|
|
zf <= src1[2];
|
| 2718 |
|
|
nf <= src1[3];
|
| 2719 |
|
|
im <= src1[4];
|
| 2720 |
|
|
hf <= src1[5];
|
| 2721 |
|
|
firqim <= src1[6];
|
| 2722 |
|
|
ef <= src1[7];
|
| 2723 |
|
|
end
|
| 2724 |
|
|
4'b1011: dpr <= src1[`LOBYTE];
|
| 2725 |
|
|
4'b1110: usppg <= src1[`DBLBYTE];
|
| 2726 |
|
|
4'b1111: ;
|
| 2727 |
|
|
default: ;
|
| 2728 |
|
|
endcase
|
| 2729 |
|
|
end
|
| 2730 |
|
|
`TSTA,`TSTB:
|
| 2731 |
|
|
begin
|
| 2732 |
|
|
vf <= 1'b0;
|
| 2733 |
|
|
nf <= res12n;
|
| 2734 |
|
|
zf <= res12z;
|
| 2735 |
|
|
end
|
| 2736 |
|
|
`TSTD:
|
| 2737 |
|
|
begin
|
| 2738 |
|
|
vf <= 1'b0;
|
| 2739 |
|
|
nf <= res24n;
|
| 2740 |
|
|
zf <= res24z;
|
| 2741 |
|
|
end
|
| 2742 |
|
|
`TST_DP,`TST_NDX,`TST_EXT:
|
| 2743 |
|
|
begin
|
| 2744 |
|
|
vf <= 1'b0;
|
| 2745 |
|
|
nf <= res12n;
|
| 2746 |
|
|
zf <= res12z;
|
| 2747 |
|
|
end
|
| 2748 |
|
|
`SUBA_IMM,`SUBA_DP,`SUBA_NDX,`SUBA_EXT:
|
| 2749 |
|
|
begin
|
| 2750 |
|
|
acca <= res12[`LOBYTE];
|
| 2751 |
|
|
nf <= res12n;
|
| 2752 |
|
|
zf <= res12z;
|
| 2753 |
|
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
| 2754 |
|
|
cf <= res12c;
|
| 2755 |
|
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
| 2756 |
|
|
end
|
| 2757 |
|
|
`SUBB_IMM,`SUBB_DP,`SUBB_NDX,`SUBB_EXT:
|
| 2758 |
|
|
begin
|
| 2759 |
|
|
accb <= res12[`LOBYTE];
|
| 2760 |
|
|
nf <= res12n;
|
| 2761 |
|
|
zf <= res12z;
|
| 2762 |
|
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
| 2763 |
|
|
cf <= res12c;
|
| 2764 |
|
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
| 2765 |
|
|
end
|
| 2766 |
|
|
`SUBD_IMM,`SUBD_DP,`SUBD_NDX,`SUBD_EXT:
|
| 2767 |
|
|
begin
|
| 2768 |
|
|
cf <= res24c;
|
| 2769 |
|
|
vf <= (1'b1 ^ res[BPBX2M1] ^ b[BPBX2M1]) & (a[BPBX2M1] ^ b[BPBX2M1]);
|
| 2770 |
|
|
nf <= res[BPBX2M1];
|
| 2771 |
|
|
zf <= res[`DBLBYTE]==24'h000000;
|
| 2772 |
|
|
acca <= res[`HIBYTE];
|
| 2773 |
|
|
accb <= res[`LOBYTE];
|
| 2774 |
|
|
end
|
| 2775 |
|
|
endcase
|
| 2776 |
|
|
end
|
| 2777 |
|
|
end
|
| 2778 |
|
|
endtask
|
| 2779 |
|
|
|
| 2780 |
|
|
task dp_store;
|
| 2781 |
|
|
input [5:0] stw;
|
| 2782 |
|
|
begin
|
| 2783 |
|
|
store_what <= stw;
|
| 2784 |
|
|
wadr <= dp_address;
|
| 2785 |
|
|
pc <= pc + 2'd2;
|
| 2786 |
|
|
next_state(STORE1);
|
| 2787 |
|
|
end
|
| 2788 |
|
|
endtask
|
| 2789 |
|
|
|
| 2790 |
|
|
task indexed_store;
|
| 2791 |
|
|
input [5:0] stw;
|
| 2792 |
|
|
begin
|
| 2793 |
|
|
store_what <= stw;
|
| 2794 |
|
|
pc <= pc + insnsz;
|
| 2795 |
|
|
if (isIndirect) begin
|
| 2796 |
|
|
load_what <= isFar ? `LW_IA2316 : `LW_IAH;
|
| 2797 |
|
|
radr <= NdxAddr;
|
| 2798 |
|
|
next_state(LOAD1);
|
| 2799 |
|
|
end
|
| 2800 |
|
|
else begin
|
| 2801 |
|
|
wadr <= NdxAddr;
|
| 2802 |
|
|
next_state(STORE1);
|
| 2803 |
|
|
end
|
| 2804 |
|
|
end
|
| 2805 |
|
|
endtask
|
| 2806 |
|
|
|
| 2807 |
|
|
task ex_store;
|
| 2808 |
|
|
input [5:0] stw;
|
| 2809 |
|
|
begin
|
| 2810 |
|
|
pc <= pc + (isFar ? 3'd4 : 3'd3);
|
| 2811 |
|
|
store_what <= stw;
|
| 2812 |
|
|
wadr <= ex_address;
|
| 2813 |
|
|
next_state(STORE1);
|
| 2814 |
|
|
end
|
| 2815 |
|
|
endtask
|
| 2816 |
|
|
|
| 2817 |
|
|
task next_state;
|
| 2818 |
|
|
input [5:0] st;
|
| 2819 |
|
|
begin
|
| 2820 |
|
|
state <= st;
|
| 2821 |
|
|
end
|
| 2822 |
|
|
endtask
|
| 2823 |
|
|
|
| 2824 |
|
|
task wb_burst;
|
| 2825 |
|
|
input [5:0] len;
|
| 2826 |
|
|
input [bitsPerByte*2-1:0] adr;
|
| 2827 |
|
|
begin
|
| 2828 |
|
|
if (!tsc) begin
|
| 2829 |
|
|
bte_o <= 2'b00;
|
| 2830 |
|
|
cti_o <= 3'b001;
|
| 2831 |
|
|
bl_o <= len;
|
| 2832 |
|
|
cyc_o <= 1'b1;
|
| 2833 |
|
|
stb_o <= 1'b1;
|
| 2834 |
|
|
adr_o <= adr;
|
| 2835 |
|
|
end
|
| 2836 |
|
|
end
|
| 2837 |
|
|
endtask
|
| 2838 |
|
|
|
| 2839 |
|
|
task wb_read;
|
| 2840 |
|
|
input [`TRPBYTE] adr;
|
| 2841 |
|
|
begin
|
| 2842 |
|
|
if (!tsc) begin
|
| 2843 |
|
|
cyc_o <= 1'b1;
|
| 2844 |
|
|
stb_o <= 1'b1;
|
| 2845 |
|
|
adr_o <= adr;
|
| 2846 |
|
|
end
|
| 2847 |
|
|
end
|
| 2848 |
|
|
endtask
|
| 2849 |
|
|
|
| 2850 |
|
|
task wb_write;
|
| 2851 |
|
|
input [`TRPBYTE] adr;
|
| 2852 |
|
|
input [`LOBYTE] dat;
|
| 2853 |
|
|
begin
|
| 2854 |
|
|
if (!tsc) begin
|
| 2855 |
|
|
cyc_o <= 1'b1;
|
| 2856 |
|
|
stb_o <= 1'b1;
|
| 2857 |
|
|
we_o <= 1'b1;
|
| 2858 |
|
|
adr_o <= adr;
|
| 2859 |
|
|
dat_o <= dat;
|
| 2860 |
|
|
end
|
| 2861 |
|
|
end
|
| 2862 |
|
|
endtask
|
| 2863 |
|
|
|
| 2864 |
|
|
task wb_nack;
|
| 2865 |
|
|
begin
|
| 2866 |
|
|
cti_o <= 3'b000;
|
| 2867 |
|
|
bl_o <= 6'd0;
|
| 2868 |
|
|
cyc_o <= 1'b0;
|
| 2869 |
|
|
stb_o <= 1'b0;
|
| 2870 |
|
|
we_o <= 1'b0;
|
| 2871 |
|
|
adr_o <= 24'd0;
|
| 2872 |
|
|
dat_o <= 12'd0;
|
| 2873 |
|
|
end
|
| 2874 |
|
|
endtask
|
| 2875 |
|
|
|
| 2876 |
|
|
task load_tsk;
|
| 2877 |
|
|
input [`LOBYTE] dat;
|
| 2878 |
|
|
begin
|
| 2879 |
|
|
case(load_what)
|
| 2880 |
|
|
`LW_BH:
|
| 2881 |
|
|
begin
|
| 2882 |
|
|
radr <= radr + 2'd1;
|
| 2883 |
|
|
b[`HIBYTE] <= dat;
|
| 2884 |
|
|
load_what <= `LW_BL;
|
| 2885 |
|
|
next_state(LOAD1);
|
| 2886 |
|
|
end
|
| 2887 |
|
|
`LW_BL:
|
| 2888 |
|
|
begin
|
| 2889 |
|
|
// Don't increment address here for the benefit of the memory
|
| 2890 |
|
|
// operate instructions which set wadr=radr in CALC.
|
| 2891 |
|
|
b[`LOBYTE] <= dat;
|
| 2892 |
|
|
next_state(CALC);
|
| 2893 |
|
|
end
|
| 2894 |
|
|
`LW_CCR: begin
|
| 2895 |
|
|
next_state(PULL1);
|
| 2896 |
|
|
radr <= radr + 2'd1;
|
| 2897 |
|
|
cf <= dat[0];
|
| 2898 |
|
|
vf <= dat[1];
|
| 2899 |
|
|
zf <= dat[2];
|
| 2900 |
|
|
nf <= dat[3];
|
| 2901 |
|
|
im <= dat[4];
|
| 2902 |
|
|
hf <= dat[5];
|
| 2903 |
|
|
firqim <= dat[6];
|
| 2904 |
|
|
ef <= dat[7];
|
| 2905 |
|
|
if (isRTI) begin
|
| 2906 |
|
|
$display("loaded ccr=%b", dat);
|
| 2907 |
|
|
ir[`HIBYTE] <= dat[7] ? 12'hFE : 12'h80;
|
| 2908 |
|
|
ssp <= ssp + 2'd1;
|
| 2909 |
|
|
end
|
| 2910 |
|
|
else if (isPULS)
|
| 2911 |
|
|
ssp <= ssp + 2'd1;
|
| 2912 |
|
|
else if (isPULU)
|
| 2913 |
|
|
usp <= usp + 2'd1;
|
| 2914 |
|
|
end
|
| 2915 |
|
|
`LW_ACCA: begin
|
| 2916 |
|
|
acca <= dat;
|
| 2917 |
|
|
radr <= radr + 2'd1;
|
| 2918 |
|
|
if (isRTI) begin
|
| 2919 |
|
|
$display("loaded acca=%h from %h", dat, radr);
|
| 2920 |
|
|
ssp <= ssp + 2'd1;
|
| 2921 |
|
|
next_state(PULL1);
|
| 2922 |
|
|
end
|
| 2923 |
|
|
else if (isPULU) begin
|
| 2924 |
|
|
usp <= usp + 2'd1;
|
| 2925 |
|
|
next_state(PULL1);
|
| 2926 |
|
|
end
|
| 2927 |
|
|
else if (isPULS) begin
|
| 2928 |
|
|
ssp <= ssp + 2'd1;
|
| 2929 |
|
|
next_state(PULL1);
|
| 2930 |
|
|
end
|
| 2931 |
|
|
else
|
| 2932 |
|
|
next_state(IFETCH);
|
| 2933 |
|
|
end
|
| 2934 |
|
|
`LW_ACCB: begin
|
| 2935 |
|
|
accb <= dat;
|
| 2936 |
|
|
radr <= radr + 2'd1;
|
| 2937 |
|
|
if (isRTI) begin
|
| 2938 |
|
|
$display("loaded accb=%h from ", dat, radr);
|
| 2939 |
|
|
ssp <= ssp + 2'd1;
|
| 2940 |
|
|
next_state(PULL1);
|
| 2941 |
|
|
end
|
| 2942 |
|
|
else if (isPULU) begin
|
| 2943 |
|
|
usp <= usp + 2'd1;
|
| 2944 |
|
|
next_state(PULL1);
|
| 2945 |
|
|
end
|
| 2946 |
|
|
else if (isPULS) begin
|
| 2947 |
|
|
ssp <= ssp + 2'd1;
|
| 2948 |
|
|
next_state(PULL1);
|
| 2949 |
|
|
end
|
| 2950 |
|
|
else
|
| 2951 |
|
|
next_state(IFETCH);
|
| 2952 |
|
|
end
|
| 2953 |
|
|
`LW_DPR: begin
|
| 2954 |
|
|
dpr <= dat;
|
| 2955 |
|
|
radr <= radr + 2'd1;
|
| 2956 |
|
|
if (isRTI) begin
|
| 2957 |
|
|
$display("loaded dpr=%h from %h", dat, radr);
|
| 2958 |
|
|
ssp <= ssp + 2'd1;
|
| 2959 |
|
|
next_state(PULL1);
|
| 2960 |
|
|
end
|
| 2961 |
|
|
else if (isPULU) begin
|
| 2962 |
|
|
usp <= usp + 2'd1;
|
| 2963 |
|
|
next_state(PULL1);
|
| 2964 |
|
|
end
|
| 2965 |
|
|
else if (isPULS) begin
|
| 2966 |
|
|
ssp <= ssp + 2'd1;
|
| 2967 |
|
|
next_state(PULL1);
|
| 2968 |
|
|
end
|
| 2969 |
|
|
else
|
| 2970 |
|
|
next_state(IFETCH);
|
| 2971 |
|
|
end
|
| 2972 |
|
|
`LW_XH: begin
|
| 2973 |
|
|
load_what <= `LW_XL;
|
| 2974 |
|
|
next_state(LOAD1);
|
| 2975 |
|
|
xr[`HIBYTE] <= dat;
|
| 2976 |
|
|
radr <= radr + 2'd1;
|
| 2977 |
|
|
if (isRTI) begin
|
| 2978 |
|
|
$display("loaded XH=%h from %h", dat, radr);
|
| 2979 |
|
|
ssp <= ssp + 2'd1;
|
| 2980 |
|
|
end
|
| 2981 |
|
|
else if (isPULU) begin
|
| 2982 |
|
|
usp <= usp + 2'd1;
|
| 2983 |
|
|
end
|
| 2984 |
|
|
else if (isPULS) begin
|
| 2985 |
|
|
ssp <= ssp + 2'd1;
|
| 2986 |
|
|
end
|
| 2987 |
|
|
end
|
| 2988 |
|
|
`LW_XL: begin
|
| 2989 |
|
|
xr[`LOBYTE] <= dat;
|
| 2990 |
|
|
radr <= radr + 2'd1;
|
| 2991 |
|
|
if (isRTI) begin
|
| 2992 |
|
|
$display("loaded XL=%h from %h", dat, radr);
|
| 2993 |
|
|
ssp <= ssp + 2'd1;
|
| 2994 |
|
|
next_state(PULL1);
|
| 2995 |
|
|
end
|
| 2996 |
|
|
else if (isPULU) begin
|
| 2997 |
|
|
usp <= usp + 2'd1;
|
| 2998 |
|
|
next_state(PULL1);
|
| 2999 |
|
|
end
|
| 3000 |
|
|
else if (isPULS) begin
|
| 3001 |
|
|
ssp <= ssp + 2'd1;
|
| 3002 |
|
|
next_state(PULL1);
|
| 3003 |
|
|
end
|
| 3004 |
|
|
else
|
| 3005 |
|
|
next_state(IFETCH);
|
| 3006 |
|
|
end
|
| 3007 |
|
|
`LW_YH:
|
| 3008 |
|
|
begin
|
| 3009 |
|
|
load_what <= `LW_YL;
|
| 3010 |
|
|
next_state(LOAD1);
|
| 3011 |
|
|
yr[`HIBYTE] <= dat;
|
| 3012 |
|
|
radr <= radr + 2'd1;
|
| 3013 |
|
|
if (isRTI) begin
|
| 3014 |
|
|
$display("loadded YH=%h", dat);
|
| 3015 |
|
|
ssp <= ssp + 2'd1;
|
| 3016 |
|
|
end
|
| 3017 |
|
|
else if (isPULU) begin
|
| 3018 |
|
|
usp <= usp + 2'd1;
|
| 3019 |
|
|
end
|
| 3020 |
|
|
else if (isPULS) begin
|
| 3021 |
|
|
ssp <= ssp + 2'd1;
|
| 3022 |
|
|
end
|
| 3023 |
|
|
end
|
| 3024 |
|
|
`LW_YL: begin
|
| 3025 |
|
|
yr[`LOBYTE] <= dat;
|
| 3026 |
|
|
radr <= radr + 2'd1;
|
| 3027 |
|
|
if (isRTI) begin
|
| 3028 |
|
|
$display("loadded YL=%h", dat);
|
| 3029 |
|
|
ssp <= ssp + 2'd1;
|
| 3030 |
|
|
next_state(PULL1);
|
| 3031 |
|
|
end
|
| 3032 |
|
|
else if (isPULU) begin
|
| 3033 |
|
|
usp <= usp + 2'd1;
|
| 3034 |
|
|
next_state(PULL1);
|
| 3035 |
|
|
end
|
| 3036 |
|
|
else if (isPULS) begin
|
| 3037 |
|
|
ssp <= ssp + 2'd1;
|
| 3038 |
|
|
next_state(PULL1);
|
| 3039 |
|
|
end
|
| 3040 |
|
|
else
|
| 3041 |
|
|
next_state(IFETCH);
|
| 3042 |
|
|
end
|
| 3043 |
|
|
`LW_USPH: begin
|
| 3044 |
|
|
load_what <= `LW_USPL;
|
| 3045 |
|
|
next_state(LOAD1);
|
| 3046 |
|
|
usp[`HIBYTE] <= dat;
|
| 3047 |
|
|
radr <= radr + 2'd1;
|
| 3048 |
|
|
if (isRTI) begin
|
| 3049 |
|
|
$display("loadded USPH=%h", dat);
|
| 3050 |
|
|
ssp <= ssp + 2'd1;
|
| 3051 |
|
|
end
|
| 3052 |
|
|
else if (isPULS) begin
|
| 3053 |
|
|
ssp <= ssp + 2'd1;
|
| 3054 |
|
|
end
|
| 3055 |
|
|
end
|
| 3056 |
|
|
`LW_USPL: begin
|
| 3057 |
|
|
usp[`LOBYTE] <= dat;
|
| 3058 |
|
|
radr <= radr + 2'd1;
|
| 3059 |
|
|
if (isRTI) begin
|
| 3060 |
|
|
$display("loadded USPL=%h", dat);
|
| 3061 |
|
|
ssp <= ssp + 2'd1;
|
| 3062 |
|
|
next_state(PULL1);
|
| 3063 |
|
|
end
|
| 3064 |
|
|
else if (isPULS) begin
|
| 3065 |
|
|
ssp <= ssp + 2'd1;
|
| 3066 |
|
|
next_state(PULL1);
|
| 3067 |
|
|
end
|
| 3068 |
|
|
else
|
| 3069 |
|
|
next_state(IFETCH);
|
| 3070 |
|
|
end
|
| 3071 |
|
|
`LW_SSPH: begin
|
| 3072 |
|
|
load_what <= `LW_SSPL;
|
| 3073 |
|
|
next_state(LOAD1);
|
| 3074 |
|
|
ssp[`HIBYTE] <= dat;
|
| 3075 |
|
|
radr <= radr + 2'd1;
|
| 3076 |
|
|
if (isRTI) begin
|
| 3077 |
|
|
ssp <= ssp + 2'd1;
|
| 3078 |
|
|
end
|
| 3079 |
|
|
else if (isPULU) begin
|
| 3080 |
|
|
usp <= usp + 2'd1;
|
| 3081 |
|
|
end
|
| 3082 |
|
|
end
|
| 3083 |
|
|
`LW_SSPL: begin
|
| 3084 |
|
|
ssp[`LOBYTE] <= dat;
|
| 3085 |
|
|
radr <= radr + 2'd1;
|
| 3086 |
|
|
if (isRTI) begin
|
| 3087 |
|
|
ssp <= ssp + 2'd1;
|
| 3088 |
|
|
next_state(PULL1);
|
| 3089 |
|
|
end
|
| 3090 |
|
|
else if (isPULU) begin
|
| 3091 |
|
|
usp <= usp + 2'd1;
|
| 3092 |
|
|
next_state(PULL1);
|
| 3093 |
|
|
end
|
| 3094 |
|
|
else
|
| 3095 |
|
|
next_state(IFETCH);
|
| 3096 |
|
|
end
|
| 3097 |
|
|
`LW_PCL: begin
|
| 3098 |
|
|
pc[`LOBYTE] <= dat;
|
| 3099 |
|
|
radr <= radr + 2'd1;
|
| 3100 |
|
|
if (isRTI|isRTS|isPULS) begin
|
| 3101 |
|
|
$display("loadded PCL=%h", dat);
|
| 3102 |
|
|
ssp <= ssp + 2'd1;
|
| 3103 |
|
|
end
|
| 3104 |
|
|
else if (isPULU)
|
| 3105 |
|
|
usp <= usp + 2'd1;
|
| 3106 |
|
|
next_state(IFETCH);
|
| 3107 |
|
|
end
|
| 3108 |
|
|
`LW_PCH: begin
|
| 3109 |
|
|
pc[`HIBYTE] <= dat;
|
| 3110 |
|
|
load_what <= `LW_PCL;
|
| 3111 |
|
|
radr <= radr + 2'd1;
|
| 3112 |
|
|
if (isRTI|isRTS|isPULS) begin
|
| 3113 |
|
|
$display("loadded PCH=%h", dat);
|
| 3114 |
|
|
ssp <= ssp + 2'd1;
|
| 3115 |
|
|
end
|
| 3116 |
|
|
else if (isPULU)
|
| 3117 |
|
|
usp <= usp + 2'd1;
|
| 3118 |
|
|
next_state(LOAD1);
|
| 3119 |
|
|
end
|
| 3120 |
|
|
`LW_PC2316: begin
|
| 3121 |
|
|
pc[`BYTE3] <= dat;
|
| 3122 |
|
|
load_what <= `LW_PCH;
|
| 3123 |
|
|
radr <= radr + 16'd1;
|
| 3124 |
|
|
if (isRTI|isRTF|isPULS)
|
| 3125 |
|
|
ssp <= ssp + 16'd1;
|
| 3126 |
|
|
else if (isPULU)
|
| 3127 |
|
|
usp <= usp + 16'd1;
|
| 3128 |
|
|
next_state(LOAD1);
|
| 3129 |
|
|
end
|
| 3130 |
|
|
`LW_IAL:
|
| 3131 |
|
|
begin
|
| 3132 |
|
|
ia[`LOBYTE] <= dat;
|
| 3133 |
|
|
res[`LOBYTE] <= dat;
|
| 3134 |
|
|
radr <= {ia[`BYTE3],ia[`HIBYTE],dat};
|
| 3135 |
|
|
wadr <= {ia[`BYTE3],ia[`HIBYTE],dat};
|
| 3136 |
|
|
`ifdef SUPPORT_DBL_IND
|
| 3137 |
|
|
if (isDblIndirect) begin
|
| 3138 |
|
|
load_what <= `LW_IAH;
|
| 3139 |
|
|
next_state(LOAD1);
|
| 3140 |
|
|
isDblIndirect <= `FALSE;
|
| 3141 |
|
|
end
|
| 3142 |
|
|
else
|
| 3143 |
|
|
`endif
|
| 3144 |
|
|
begin
|
| 3145 |
|
|
load_what <= load_what2;
|
| 3146 |
|
|
if (isOuterIndexed)
|
| 3147 |
|
|
next_state(OUTER_INDEXING);
|
| 3148 |
|
|
else begin
|
| 3149 |
|
|
if (isLEA)
|
| 3150 |
|
|
next_state(IFETCH);
|
| 3151 |
|
|
else if (isStore)
|
| 3152 |
|
|
next_state(STORE1);
|
| 3153 |
|
|
else
|
| 3154 |
|
|
next_state(LOAD1);
|
| 3155 |
|
|
end
|
| 3156 |
|
|
end
|
| 3157 |
|
|
end
|
| 3158 |
|
|
`LW_IAH:
|
| 3159 |
|
|
begin
|
| 3160 |
|
|
ia[`HIBYTE] <= dat;
|
| 3161 |
|
|
res[`HIBYTE] <= dat;
|
| 3162 |
|
|
load_what <= `LW_IAL;
|
| 3163 |
|
|
radr <= radr + 2'd1;
|
| 3164 |
|
|
next_state(LOAD1);
|
| 3165 |
|
|
end
|
| 3166 |
|
|
`LW_IA2316:
|
| 3167 |
|
|
begin
|
| 3168 |
|
|
ia[`BYTE3] <= dat;
|
| 3169 |
|
|
load_what <= `LW_IAH;
|
| 3170 |
|
|
radr <= radr + 32'd1;
|
| 3171 |
|
|
next_state(LOAD1);
|
| 3172 |
|
|
end
|
| 3173 |
|
|
endcase
|
| 3174 |
|
|
end
|
| 3175 |
|
|
endtask
|
| 3176 |
|
|
|
| 3177 |
|
|
endmodule
|
| 3178 |
|
|
|
| 3179 |
|
|
// ============================================================================
|
| 3180 |
|
|
// Cache Memories
|
| 3181 |
|
|
// ============================================================================
|
| 3182 |
|
|
module rf6809_icachemem(wclk, wce, wr, wa, i, rclk, rce, pc, insn);
|
| 3183 |
|
|
input wclk;
|
| 3184 |
|
|
input wce;
|
| 3185 |
|
|
input wr;
|
| 3186 |
|
|
input [11:0] wa;
|
| 3187 |
|
|
input [BPB*16-1:0] i;
|
| 3188 |
|
|
input rclk;
|
| 3189 |
|
|
input rce;
|
| 3190 |
|
|
input [11:0] pc;
|
| 3191 |
|
|
output [`HEXBYTE] insn;
|
| 3192 |
|
|
reg [`HEXBYTE] insn;
|
| 3193 |
|
|
|
| 3194 |
|
|
integer n;
|
| 3195 |
|
|
reg [BPB*16-1:0] mem [0:255];
|
| 3196 |
|
|
reg [11:0] rpc,rpcp16;
|
| 3197 |
|
|
initial begin
|
| 3198 |
|
|
for (n = 0; n < 256; n = n + 1)
|
| 3199 |
|
|
mem[n] = {16{`NOP}};
|
| 3200 |
|
|
end
|
| 3201 |
|
|
|
| 3202 |
|
|
always_ff @(posedge wclk)
|
| 3203 |
|
|
if (wce & wr) mem[wa[11:4]] <= i;
|
| 3204 |
|
|
|
| 3205 |
|
|
always_ff @(posedge rclk)
|
| 3206 |
|
|
if (rce) rpc <= pc;
|
| 3207 |
|
|
always_ff @(posedge rclk)
|
| 3208 |
|
|
if (rce) rpcp16 <= pc + 5'd16;
|
| 3209 |
|
|
wire [BPB*16-1:0] insn0 = mem[rpc[11:4]];
|
| 3210 |
|
|
wire [BPB*16-1:0] insn1 = mem[rpcp16[11:4]];
|
| 3211 |
|
|
always_comb
|
| 3212 |
|
|
insn = {insn1,insn0} >> ({4'h0,rpc[3:0]} * BPB);
|
| 3213 |
|
|
|
| 3214 |
|
|
endmodule
|
| 3215 |
|
|
|
| 3216 |
|
|
module rf6809_itagmem(wclk, wce, wr, wa, invalidate, rclk, rce, pc, hit0, hit1);
|
| 3217 |
|
|
input wclk;
|
| 3218 |
|
|
input wce;
|
| 3219 |
|
|
input wr;
|
| 3220 |
|
|
input [`TRPBYTE] wa;
|
| 3221 |
|
|
input invalidate;
|
| 3222 |
|
|
input rclk;
|
| 3223 |
|
|
input rce;
|
| 3224 |
|
|
input [`TRPBYTE] pc;
|
| 3225 |
|
|
output hit0;
|
| 3226 |
|
|
output hit1;
|
| 3227 |
|
|
|
| 3228 |
|
|
integer n;
|
| 3229 |
|
|
reg [BPB*3-1:12] mem [0:255];
|
| 3230 |
|
|
reg [0:255] tvalid = 256'd0;
|
| 3231 |
|
|
reg [`TRPBYTE] rpc,rpcp16;
|
| 3232 |
|
|
wire [BPB*3-1:11] tag0,tag1;
|
| 3233 |
|
|
initial begin
|
| 3234 |
|
|
for (n = 0; n < 256; n = n + 1)
|
| 3235 |
|
|
mem[n] = {BPB*2{1'b0}};
|
| 3236 |
|
|
end
|
| 3237 |
|
|
|
| 3238 |
|
|
always_ff @(posedge wclk)
|
| 3239 |
|
|
if (wce & wr) mem[wa[11:4]] <= wa[BPB*3-1:12];
|
| 3240 |
|
|
always_ff @(posedge wclk)
|
| 3241 |
|
|
if (invalidate) tvalid <= 256'd0;
|
| 3242 |
|
|
else if (wce & wr) tvalid[wa[11:4]] <= 1'b1;
|
| 3243 |
|
|
always_ff @(posedge rclk)
|
| 3244 |
|
|
if (rce) rpc <= pc;
|
| 3245 |
|
|
always_ff @(posedge rclk)
|
| 3246 |
|
|
if (rce) rpcp16 <= pc + 5'd16;
|
| 3247 |
|
|
assign tag0 = {mem[rpc[11:4]],tvalid[rpc[11:4]]};
|
| 3248 |
|
|
assign tag1 = {mem[rpcp16[11:4]],tvalid[rpcp16[11:4]]};
|
| 3249 |
|
|
|
| 3250 |
|
|
assign hit0 = tag0 == {rpc[BPB*3-1:12],1'b1};
|
| 3251 |
|
|
assign hit1 = tag1 == {rpcp16[BPB*3-1:12],1'b1};
|
| 3252 |
|
|
|
| 3253 |
|
|
endmodule
|
| 3254 |
|
|
|
