OpenCores
URL https://opencores.org/ocsvn/rf6809/rf6809/trunk

Subversion Repositories rf6809

[/] [rf6809/] [trunk/] [rtl/] [noc/] [lib/] [BtnDebounce.v] - Blame information for rev 19

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2016-2021  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch<remove>@finitron.ca
6
//       ||
7
//
8
// This source file is free software: you can redistribute it and/or modify 
9
// it under the terms of the GNU Lesser General Public License as published 
10
// by the Free Software Foundation, either version 3 of the License, or     
11
// (at your option) any later version.                                      
12
//                                                                          
13
// This source file is distributed in the hope that it will be useful,      
14
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
15
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
16
// GNU General Public License for more details.                             
17
//                                                                          
18
// You should have received a copy of the GNU General Public License        
19
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
20
//
21
//
22
// Button / switch debounce circuit.
23
// Assumes 25MHz clock
24
// Approximately 10ms of debounce is provided.
25
// ============================================================================
26
//
27
module BtnDebounce(clk, btn_i, o);
28
input clk;
29
input btn_i;
30
output reg o;
31
 
32
reg [18:0] counter;
33
reg val1, val2;
34
 
35
always @(posedge clk)
36
begin
37
  val1 <= btn_i;
38
  val2 <= val1;
39
end
40
 
41
always @(posedge clk)
42
if (val1 != val2)
43
  counter <= 19'h0;
44
else if (counter[18])
45
  counter <= 19'h0;
46
else
47
  counter <= counter + 19'd1;
48
 
49
always @(posedge clk)
50
if (counter[18])
51
  o <= val2;
52
 
53
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.