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magro732 |
-------------------------------------------------------------------------------
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--
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-- RapidIO IP Library Core
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--
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-- This file is part of the RapidIO IP library project
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-- http://www.opencores.org/cores/rio/
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--
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-- Description
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-- Contains commonly used types, functions, procedures and entities used in
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-- the RapidIO IP library project.
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--
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-- To Do:
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-- -
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--
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-- Author(s):
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-- - Magnus Rosenius, magro732@opencores.org
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2013 Authors and OPENCORES.ORG
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- RioCommon library.
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-------------------------------------------------------------------------------
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-- RioCommon package description.
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-------------------------------------------------------------------------------
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package rio_common is
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magro732 |
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magro732 |
-----------------------------------------------------------------------------
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magro732 |
-- Primitive memory component declarations.
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-----------------------------------------------------------------------------
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component MemorySimpleDualPort
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generic(
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ADDRESS_WIDTH : natural := 1;
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DATA_WIDTH : natural := 1);
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port(
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clkA_i : in std_logic;
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enableA_i : in std_logic;
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addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
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dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
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clkB_i : in std_logic;
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enableB_i : in std_logic;
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addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
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dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
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end component;
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component MemoryDualPort is
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generic(
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ADDRESS_WIDTH : natural := 1;
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DATA_WIDTH : natural := 1);
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port(
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clkA_i : in std_logic;
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enableA_i : in std_logic;
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writeEnableA_i : in std_logic;
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addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
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dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
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dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
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clkB_i : in std_logic;
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enableB_i : in std_logic;
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addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
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dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
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end component;
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magro732 |
component Crc16CITT is
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port(
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d_i : in std_logic_vector(15 downto 0);
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crc_i : in std_logic_vector(15 downto 0);
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crc_o : out std_logic_vector(15 downto 0));
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end component;
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magro732 |
-----------------------------------------------------------------------------
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-- Logical layer component declarations.
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-----------------------------------------------------------------------------
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component RioLogicalCommon is
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generic(
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PORTS : natural);
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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readFrameEmpty_i : in std_logic;
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readFrame_o : out std_logic;
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readContent_o : out std_logic;
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readContentEnd_i : in std_logic;
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readContentData_i : in std_logic_vector(31 downto 0);
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writeFrameFull_i : in std_logic;
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writeFrame_o : out std_logic;
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writeFrameAbort_o : out std_logic;
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writeContent_o : out std_logic;
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writeContentData_o : out std_logic_vector(31 downto 0);
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inboundStb_o : out std_logic;
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magro732 |
inboundAdr_o : out std_logic_vector(3 downto 0);
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magro732 |
inboundDat_o : out std_logic_vector(31 downto 0);
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magro732 |
inboundStall_i : in std_logic;
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magro732 |
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outboundStb_i : in std_logic_vector(PORTS-1 downto 0);
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magro732 |
outboundAdr_i : in std_logic_vector(PORTS-1 downto 0);
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magro732 |
outboundDat_i : in std_logic_vector(32*PORTS-1 downto 0);
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magro732 |
outboundStall_o : out std_logic_vector(PORTS-1 downto 0));
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magro732 |
end component;
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component RioLogicalMaintenance is
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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readRequestReady_i : in std_logic;
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writeRequestReady_i : in std_logic;
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magro732 |
size_i : in std_logic_vector(3 downto 0);
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magro732 |
offset_i : in std_logic_vector(20 downto 0);
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wdptr_i : in std_logic;
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47 |
magro732 |
payloadLength_i : in std_logic_vector(2 downto 0);
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payloadIndex_o : out std_logic_vector(2 downto 0);
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payload_i : in std_logic_vector(63 downto 0);
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magro732 |
done_o : out std_logic;
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readResponseReady_o : out std_logic;
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writeResponseReady_o : out std_logic;
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magro732 |
status_o : out std_logic_vector(3 downto 0);
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payloadLength_o : out std_logic_vector(2 downto 0);
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payloadIndex_i : in std_logic_vector(2 downto 0);
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payload_o : out std_logic_vector(63 downto 0);
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magro732 |
done_i : in std_logic;
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configStb_o : out std_logic;
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configWe_o : out std_logic;
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configAdr_o : out std_logic_vector(21 downto 0);
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configDat_o : out std_logic_vector(31 downto 0);
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configDat_i : in std_logic_vector(31 downto 0);
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configAck_i : in std_logic);
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end component;
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component MaintenanceInbound is
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magro732 |
generic(
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ENABLE_READ_REQUEST : boolean := true;
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ENABLE_WRITE_REQUEST : boolean := true;
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ENABLE_READ_RESPONSE : boolean := true;
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ENABLE_WRITE_RESPONSE : boolean := true;
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ENABLE_PORT_WRITE : boolean := true);
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46 |
magro732 |
port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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readRequestReady_o : out std_logic;
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writeRequestReady_o : out std_logic;
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readResponseReady_o : out std_logic;
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writeResponseReady_o : out std_logic;
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portWriteReady_o : out std_logic;
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48 |
magro732 |
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46 |
magro732 |
vc_o : out std_logic;
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crf_o : out std_logic;
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prio_o : out std_logic_vector(1 downto 0);
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tt_o : out std_logic_vector(1 downto 0);
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dstid_o : out std_logic_vector(31 downto 0);
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srcid_o : out std_logic_vector(31 downto 0);
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47 |
magro732 |
size_o : out std_logic_vector(3 downto 0);
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status_o : out std_logic_vector(3 downto 0);
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46 |
magro732 |
tid_o : out std_logic_vector(7 downto 0);
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hop_o : out std_logic_vector(7 downto 0);
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offset_o : out std_logic_vector(20 downto 0);
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wdptr_o : out std_logic;
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47 |
magro732 |
payloadLength_o : out std_logic_vector(2 downto 0);
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payloadIndex_i : in std_logic_vector(2 downto 0);
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payload_o : out std_logic_vector(63 downto 0);
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46 |
magro732 |
done_i : in std_logic;
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inboundStb_i : in std_logic;
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48 |
magro732 |
inboundAdr_i : in std_logic_vector(3 downto 0);
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46 |
magro732 |
inboundDat_i : in std_logic_vector(31 downto 0);
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48 |
magro732 |
inboundStall_o : out std_logic);
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magro732 |
end component;
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48 |
magro732 |
component RequestClassInbound is
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generic(
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EXTENDED_ADDRESS : natural range 0 to 2 := 0);
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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nreadReady_o : out std_logic;
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vc_o : out std_logic;
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crf_o : out std_logic;
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prio_o : out std_logic_vector(1 downto 0);
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tt_o : out std_logic_vector(1 downto 0);
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225 |
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dstId_o : out std_logic_vector(31 downto 0);
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srcId_o : out std_logic_vector(31 downto 0);
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tid_o : out std_logic_vector(7 downto 0);
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address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
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length_o : out std_logic_vector(4 downto 0);
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230 |
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select_o : out std_logic_vector(7 downto 0);
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done_i : in std_logic;
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233 |
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inboundStb_i : in std_logic;
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inboundAdr_i : in std_logic_vector(3 downto 0);
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inboundDat_i : in std_logic_vector(31 downto 0);
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inboundStall_o : out std_logic);
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end component;
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component WriteClassInbound is
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240 |
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generic(
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ENABLE_NWRITE : boolean := true;
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242 |
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ENABLE_NWRITER : boolean := true;
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243 |
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EXTENDED_ADDRESS : natural range 0 to 2 := 0);
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244 |
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port(
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245 |
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clk : in std_logic;
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areset_n : in std_logic;
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247 |
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enable : in std_logic;
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248 |
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|
249 |
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nwriteReady_o : out std_logic;
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250 |
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nwriterReady_o : out std_logic;
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251 |
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|
252 |
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vc_o : out std_logic;
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253 |
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crf_o : out std_logic;
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254 |
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prio_o : out std_logic_vector(1 downto 0);
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255 |
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tt_o : out std_logic_vector(1 downto 0);
|
256 |
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dstId_o : out std_logic_vector(31 downto 0);
|
257 |
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srcId_o : out std_logic_vector(31 downto 0);
|
258 |
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tid_o : out std_logic_vector(7 downto 0);
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259 |
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address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
260 |
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length_o : out std_logic_vector(4 downto 0);
|
261 |
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select_o : out std_logic_vector(7 downto 0);
|
262 |
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payloadIndex_i : in std_logic_vector(4 downto 0);
|
263 |
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payload_o : out std_logic_vector(63 downto 0);
|
264 |
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done_i : in std_logic;
|
265 |
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|
266 |
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inboundStb_i : in std_logic;
|
267 |
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inboundAdr_i : in std_logic_vector(3 downto 0);
|
268 |
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inboundDat_i : in std_logic_vector(31 downto 0);
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269 |
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inboundStall_o : out std_logic);
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270 |
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end component;
|
271 |
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|
272 |
46 |
magro732 |
component MaintenanceOutbound is
|
273 |
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port(
|
274 |
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clk : in std_logic;
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275 |
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areset_n : in std_logic;
|
276 |
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enable : in std_logic;
|
277 |
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|
278 |
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readRequestReady_i : in std_logic;
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279 |
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writeRequestReady_i : in std_logic;
|
280 |
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readResponseReady_i : in std_logic;
|
281 |
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writeResponseReady_i : in std_logic;
|
282 |
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portWriteReady_i : in std_logic;
|
283 |
48 |
magro732 |
|
284 |
46 |
magro732 |
vc_i : in std_logic;
|
285 |
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crf_i : in std_logic;
|
286 |
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prio_i : in std_logic_vector(1 downto 0);
|
287 |
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tt_i : in std_logic_vector(1 downto 0);
|
288 |
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dstid_i : in std_logic_vector(31 downto 0);
|
289 |
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srcid_i : in std_logic_vector(31 downto 0);
|
290 |
47 |
magro732 |
size_i : in std_logic_vector(3 downto 0);
|
291 |
46 |
magro732 |
status_i : in std_logic_vector(3 downto 0);
|
292 |
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tid_i : in std_logic_vector(7 downto 0);
|
293 |
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hop_i : in std_logic_vector(7 downto 0);
|
294 |
|
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offset_i : in std_logic_vector(20 downto 0);
|
295 |
|
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wdptr_i : in std_logic;
|
296 |
47 |
magro732 |
payloadLength_i : in std_logic_vector(2 downto 0);
|
297 |
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payloadIndex_o : out std_logic_vector(2 downto 0);
|
298 |
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payload_i : in std_logic_vector(63 downto 0);
|
299 |
46 |
magro732 |
done_o : out std_logic;
|
300 |
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|
301 |
|
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outboundStb_o : out std_logic;
|
302 |
48 |
magro732 |
outboundAdr_o : out std_logic;
|
303 |
46 |
magro732 |
outboundDat_o : out std_logic_vector(31 downto 0);
|
304 |
48 |
magro732 |
outboundStall_i : in std_logic);
|
305 |
46 |
magro732 |
end component;
|
306 |
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|
307 |
48 |
magro732 |
component ResponseClassOutbound is
|
308 |
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port(
|
309 |
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clk : in std_logic;
|
310 |
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areset_n : in std_logic;
|
311 |
|
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enable : in std_logic;
|
312 |
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|
313 |
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doneNoPayloadReady_i : in std_logic;
|
314 |
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doneWithPayloadReady_i : in std_logic;
|
315 |
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errorReady_i : in std_logic;
|
316 |
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|
317 |
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vc_i : in std_logic;
|
318 |
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crf_i : in std_logic;
|
319 |
|
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prio_i : in std_logic_vector(1 downto 0);
|
320 |
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tt_i : in std_logic_vector(1 downto 0);
|
321 |
|
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dstid_i : in std_logic_vector(31 downto 0);
|
322 |
|
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srcid_i : in std_logic_vector(31 downto 0);
|
323 |
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tid_i : in std_logic_vector(7 downto 0);
|
324 |
|
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payloadLength_i : in std_logic_vector(4 downto 0);
|
325 |
|
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payloadIndex_o : out std_logic_vector(4 downto 0);
|
326 |
|
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payload_i : in std_logic_vector(63 downto 0);
|
327 |
|
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done_o : out std_logic;
|
328 |
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|
329 |
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outboundStb_o : out std_logic;
|
330 |
|
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outboundAdr_o : out std_logic;
|
331 |
|
|
outboundDat_o : out std_logic_vector(31 downto 0);
|
332 |
|
|
outboundStall_i : in std_logic);
|
333 |
|
|
end component;
|
334 |
|
|
|
335 |
46 |
magro732 |
component RioPacketBuffer is
|
336 |
|
|
generic(
|
337 |
|
|
SIZE_ADDRESS_WIDTH : natural := 6;
|
338 |
|
|
CONTENT_ADDRESS_WIDTH : natural := 8);
|
339 |
|
|
port(
|
340 |
|
|
clk : in std_logic;
|
341 |
|
|
areset_n : in std_logic;
|
342 |
|
|
|
343 |
|
|
inboundWriteFrameFull_o : out std_logic;
|
344 |
|
|
inboundWriteFrame_i : in std_logic;
|
345 |
|
|
inboundWriteFrameAbort_i : in std_logic;
|
346 |
|
|
inboundWriteContent_i : in std_logic;
|
347 |
|
|
inboundWriteContentData_i : in std_logic_vector(31 downto 0);
|
348 |
|
|
inboundReadFrameEmpty_o : out std_logic;
|
349 |
|
|
inboundReadFrame_i : in std_logic;
|
350 |
|
|
inboundReadFrameRestart_i : in std_logic;
|
351 |
|
|
inboundReadFrameAborted_o : out std_logic;
|
352 |
|
|
inboundReadContentEmpty_o : out std_logic;
|
353 |
|
|
inboundReadContent_i : in std_logic;
|
354 |
|
|
inboundReadContentEnd_o : out std_logic;
|
355 |
|
|
inboundReadContentData_o : out std_logic_vector(31 downto 0);
|
356 |
|
|
|
357 |
|
|
outboundWriteFrameFull_o : out std_logic;
|
358 |
|
|
outboundWriteFrame_i : in std_logic;
|
359 |
|
|
outboundWriteFrameAbort_i : in std_logic;
|
360 |
|
|
outboundWriteContent_i : in std_logic;
|
361 |
|
|
outboundWriteContentData_i : in std_logic_vector(31 downto 0);
|
362 |
|
|
outboundReadFrameEmpty_o : out std_logic;
|
363 |
|
|
outboundReadFrame_i : in std_logic;
|
364 |
|
|
outboundReadFrameRestart_i : in std_logic;
|
365 |
|
|
outboundReadFrameAborted_o : out std_logic;
|
366 |
|
|
outboundReadContentEmpty_o : out std_logic;
|
367 |
|
|
outboundReadContent_i : in std_logic;
|
368 |
|
|
outboundReadContentEnd_o : out std_logic;
|
369 |
|
|
outboundReadContentData_o : out std_logic_vector(31 downto 0));
|
370 |
|
|
end component;
|
371 |
|
|
|
372 |
|
|
-----------------------------------------------------------------------------
|
373 |
2 |
magro732 |
-- Commonly used types.
|
374 |
|
|
-----------------------------------------------------------------------------
|
375 |
|
|
type Array1 is array (natural range <>) of
|
376 |
|
|
std_logic;
|
377 |
|
|
type Array2 is array (natural range <>) of
|
378 |
|
|
std_logic_vector(1 downto 0);
|
379 |
|
|
type Array3 is array (natural range <>) of
|
380 |
|
|
std_logic_vector(2 downto 0);
|
381 |
|
|
type Array4 is array (natural range <>) of
|
382 |
|
|
std_logic_vector(3 downto 0);
|
383 |
|
|
type Array5 is array (natural range <>) of
|
384 |
|
|
std_logic_vector(4 downto 0);
|
385 |
|
|
type Array8 is array (natural range <>) of
|
386 |
|
|
std_logic_vector(7 downto 0);
|
387 |
|
|
type Array9 is array (natural range <>) of
|
388 |
|
|
std_logic_vector(8 downto 0);
|
389 |
|
|
type Array10 is array (natural range <>) of
|
390 |
|
|
std_logic_vector(9 downto 0);
|
391 |
|
|
type Array16 is array (natural range <>) of
|
392 |
|
|
std_logic_vector(15 downto 0);
|
393 |
|
|
type Array32 is array (natural range <>) of
|
394 |
|
|
std_logic_vector(31 downto 0);
|
395 |
|
|
type Array34 is array (natural range <>) of
|
396 |
|
|
std_logic_vector(33 downto 0);
|
397 |
|
|
|
398 |
|
|
-----------------------------------------------------------------------------
|
399 |
|
|
-- Commonly used constants.
|
400 |
|
|
-----------------------------------------------------------------------------
|
401 |
|
|
|
402 |
51 |
magro732 |
-- Symbol types between the serial and the PCS layer.
|
403 |
|
|
constant SYMBOL_IDLE : std_logic_vector(1 downto 0) := "00";
|
404 |
|
|
constant SYMBOL_CONTROL : std_logic_vector(1 downto 0) := "01";
|
405 |
|
|
constant SYMBOL_ERROR : std_logic_vector(1 downto 0) := "10";
|
406 |
|
|
constant SYMBOL_DATA : std_logic_vector(1 downto 0) := "11";
|
407 |
|
|
|
408 |
2 |
magro732 |
-- STYPE0 constants.
|
409 |
|
|
constant STYPE0_PACKET_ACCEPTED : std_logic_vector(2 downto 0) := "000";
|
410 |
|
|
constant STYPE0_PACKET_RETRY : std_logic_vector(2 downto 0) := "001";
|
411 |
|
|
constant STYPE0_PACKET_NOT_ACCEPTED : std_logic_vector(2 downto 0) := "010";
|
412 |
|
|
constant STYPE0_RESERVED : std_logic_vector(2 downto 0) := "011";
|
413 |
|
|
constant STYPE0_STATUS : std_logic_vector(2 downto 0) := "100";
|
414 |
|
|
constant STYPE0_VC_STATUS : std_logic_vector(2 downto 0) := "101";
|
415 |
|
|
constant STYPE0_LINK_RESPONSE : std_logic_vector(2 downto 0) := "110";
|
416 |
|
|
constant STYPE0_IMPLEMENTATION_DEFINED : std_logic_vector(2 downto 0) := "111";
|
417 |
|
|
|
418 |
|
|
-- STYPE1 constants.
|
419 |
|
|
constant STYPE1_START_OF_PACKET : std_logic_vector(2 downto 0) := "000";
|
420 |
|
|
constant STYPE1_STOMP : std_logic_vector(2 downto 0) := "001";
|
421 |
|
|
constant STYPE1_END_OF_PACKET : std_logic_vector(2 downto 0) := "010";
|
422 |
|
|
constant STYPE1_RESTART_FROM_RETRY : std_logic_vector(2 downto 0) := "011";
|
423 |
|
|
constant STYPE1_LINK_REQUEST : std_logic_vector(2 downto 0) := "100";
|
424 |
|
|
constant STYPE1_MULTICAST_EVENT : std_logic_vector(2 downto 0) := "101";
|
425 |
|
|
constant STYPE1_RESERVED : std_logic_vector(2 downto 0) := "110";
|
426 |
|
|
constant STYPE1_NOP : std_logic_vector(2 downto 0) := "111";
|
427 |
|
|
|
428 |
|
|
-- FTYPE constants.
|
429 |
|
|
constant FTYPE_REQUEST_CLASS : std_logic_vector(3 downto 0) := "0010";
|
430 |
|
|
constant FTYPE_WRITE_CLASS : std_logic_vector(3 downto 0) := "0101";
|
431 |
|
|
constant FTYPE_STREAMING_WRITE_CLASS : std_logic_vector(3 downto 0) := "0110";
|
432 |
|
|
constant FTYPE_MAINTENANCE_CLASS : std_logic_vector(3 downto 0) := "1000";
|
433 |
|
|
constant FTYPE_RESPONSE_CLASS : std_logic_vector(3 downto 0) := "1101";
|
434 |
|
|
constant FTYPE_DOORBELL_CLASS : std_logic_vector(3 downto 0) := "1010";
|
435 |
|
|
constant FTYPE_MESSAGE_CLASS : std_logic_vector(3 downto 0) := "0010";
|
436 |
|
|
|
437 |
|
|
-- TTYPE Constants
|
438 |
|
|
constant TTYPE_MAINTENANCE_READ_REQUEST : std_logic_vector(3 downto 0) := "0000";
|
439 |
|
|
constant TTYPE_MAINTENANCE_WRITE_REQUEST : std_logic_vector(3 downto 0) := "0001";
|
440 |
|
|
constant TTYPE_MAINTENANCE_READ_RESPONSE : std_logic_vector(3 downto 0) := "0010";
|
441 |
|
|
constant TTYPE_MAINTENANCE_WRITE_RESPONSE : std_logic_vector(3 downto 0) := "0011";
|
442 |
48 |
magro732 |
constant TTYPE_MAINTENANCE_PORT_WRITE : std_logic_vector(3 downto 0) := "0100";
|
443 |
2 |
magro732 |
constant TTYPE_NREAD_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
|
444 |
|
|
constant TTYPE_NWRITE_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
|
445 |
48 |
magro732 |
constant TTYPE_NWRITER_TRANSACTION : std_logic_vector(3 downto 0) := "0101";
|
446 |
|
|
constant TTYPE_RESPONSE_NO_PAYLOAD : std_logic_vector(3 downto 0) := "0000";
|
447 |
|
|
constant TTYPE_RESPONSE_WITH_PAYLOAD : std_logic_vector(3 downto 0) := "1000";
|
448 |
2 |
magro732 |
|
449 |
|
|
constant LINK_REQUEST_CMD_RESET_DEVICE : std_logic_vector(2 downto 0) := "011";
|
450 |
|
|
constant LINK_REQUEST_CMD_INPUT_STATUS : std_logic_vector(2 downto 0) := "100";
|
451 |
|
|
|
452 |
|
|
constant PACKET_NOT_ACCEPTED_CAUSE_UNEXPECTED_ACKID : std_logic_vector(4 downto 0) := "00001";
|
453 |
|
|
constant PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC : std_logic_vector(4 downto 0) := "00010";
|
454 |
|
|
constant PACKET_NOT_ACCEPTED_CAUSE_NON_MAINTENANCE_STOPPED : std_logic_vector(4 downto 0) := "00011";
|
455 |
|
|
constant PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC : std_logic_vector(4 downto 0) := "00100";
|
456 |
|
|
constant PACKET_NOT_ACCEPTED_CAUSE_INVALID_CHARACTER : std_logic_vector(4 downto 0) := "00101";
|
457 |
|
|
constant PACKET_NOT_ACCEPTED_CAUSE_NO_RESOURCES : std_logic_vector(4 downto 0) := "00110";
|
458 |
|
|
constant PACKET_NOT_ACCEPTED_CAUSE_LOSS_DESCRAMBLER : std_logic_vector(4 downto 0) := "00111";
|
459 |
|
|
constant PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR : std_logic_vector(4 downto 0) := "11111";
|
460 |
|
|
|
461 |
|
|
end package;
|
462 |
|
|
|
463 |
|
|
-------------------------------------------------------------------------------
|
464 |
|
|
-- RioCommon package body description.
|
465 |
|
|
-------------------------------------------------------------------------------
|
466 |
|
|
package body rio_common is
|
467 |
|
|
|
468 |
|
|
end rio_common;
|
469 |
|
|
|
470 |
|
|
|
471 |
|
|
|
472 |
|
|
-------------------------------------------------------------------------------
|
473 |
|
|
-- Crc16CITT
|
474 |
|
|
-- A CRC-16 calculator following the implementation proposed in the 2.2
|
475 |
|
|
-- standard.
|
476 |
|
|
-------------------------------------------------------------------------------
|
477 |
|
|
library ieee;
|
478 |
|
|
use ieee.std_logic_1164.all;
|
479 |
|
|
|
480 |
|
|
|
481 |
|
|
-------------------------------------------------------------------------------
|
482 |
|
|
-- Entity for Crc16CITT.
|
483 |
|
|
-------------------------------------------------------------------------------
|
484 |
|
|
entity Crc16CITT is
|
485 |
|
|
port(
|
486 |
|
|
d_i : in std_logic_vector(15 downto 0);
|
487 |
|
|
crc_i : in std_logic_vector(15 downto 0);
|
488 |
|
|
crc_o : out std_logic_vector(15 downto 0));
|
489 |
|
|
end entity;
|
490 |
|
|
|
491 |
|
|
|
492 |
|
|
-------------------------------------------------------------------------------
|
493 |
|
|
-- Architecture for Crc16CITT.
|
494 |
|
|
-------------------------------------------------------------------------------
|
495 |
|
|
architecture Crc16Impl of Crc16CITT is
|
496 |
|
|
signal d : std_logic_vector(0 to 15);
|
497 |
|
|
signal c : std_logic_vector(0 to 15);
|
498 |
|
|
signal e : std_logic_vector(0 to 15);
|
499 |
|
|
signal cc : std_logic_vector(0 to 15);
|
500 |
|
|
begin
|
501 |
|
|
|
502 |
|
|
-- Reverse the bit vector indexes to make them the same as in the standard.
|
503 |
|
|
d(15) <= d_i(0); d(14) <= d_i(1); d(13) <= d_i(2); d(12) <= d_i(3);
|
504 |
|
|
d(11) <= d_i(4); d(10) <= d_i(5); d(9) <= d_i(6); d(8) <= d_i(7);
|
505 |
|
|
d(7) <= d_i(8); d(6) <= d_i(9); d(5) <= d_i(10); d(4) <= d_i(11);
|
506 |
|
|
d(3) <= d_i(12); d(2) <= d_i(13); d(1) <= d_i(14); d(0) <= d_i(15);
|
507 |
|
|
|
508 |
|
|
-- Reverse the bit vector indexes to make them the same as in the standard.
|
509 |
|
|
c(15) <= crc_i(0); c(14) <= crc_i(1); c(13) <= crc_i(2); c(12) <= crc_i(3);
|
510 |
|
|
c(11) <= crc_i(4); c(10) <= crc_i(5); c(9) <= crc_i(6); c(8) <= crc_i(7);
|
511 |
|
|
c(7) <= crc_i(8); c(6) <= crc_i(9); c(5) <= crc_i(10); c(4) <= crc_i(11);
|
512 |
|
|
c(3) <= crc_i(12); c(2) <= crc_i(13); c(1) <= crc_i(14); c(0) <= crc_i(15);
|
513 |
|
|
|
514 |
|
|
-- Calculate the resulting crc.
|
515 |
|
|
e <= c xor d;
|
516 |
|
|
cc(0) <= e(4) xor e(5) xor e(8) xor e(12);
|
517 |
|
|
cc(1) <= e(5) xor e(6) xor e(9) xor e(13);
|
518 |
|
|
cc(2) <= e(6) xor e(7) xor e(10) xor e(14);
|
519 |
|
|
cc(3) <= e(0) xor e(7) xor e(8) xor e(11) xor e(15);
|
520 |
|
|
cc(4) <= e(0) xor e(1) xor e(4) xor e(5) xor e(9);
|
521 |
|
|
cc(5) <= e(1) xor e(2) xor e(5) xor e(6) xor e(10);
|
522 |
|
|
cc(6) <= e(0) xor e(2) xor e(3) xor e(6) xor e(7) xor e(11);
|
523 |
|
|
cc(7) <= e(0) xor e(1) xor e(3) xor e(4) xor e(7) xor e(8) xor e(12);
|
524 |
|
|
cc(8) <= e(0) xor e(1) xor e(2) xor e(4) xor e(5) xor e(8) xor e(9) xor e(13);
|
525 |
|
|
cc(9) <= e(1) xor e(2) xor e(3) xor e(5) xor e(6) xor e(9) xor e(10) xor e(14);
|
526 |
|
|
cc(10) <= e(2) xor e(3) xor e(4) xor e(6) xor e(7) xor e(10) xor e(11) xor e(15);
|
527 |
|
|
cc(11) <= e(0) xor e(3) xor e(7) xor e(11);
|
528 |
|
|
cc(12) <= e(0) xor e(1) xor e(4) xor e(8) xor e(12);
|
529 |
|
|
cc(13) <= e(1) xor e(2) xor e(5) xor e(9) xor e(13);
|
530 |
|
|
cc(14) <= e(2) xor e(3) xor e(6) xor e(10) xor e(14);
|
531 |
|
|
cc(15) <= e(3) xor e(4) xor e(7) xor e(11) xor e(15);
|
532 |
|
|
|
533 |
|
|
-- Reverse the bit vector indexes to make them the same as in the standard.
|
534 |
|
|
crc_o(15) <= cc(0); crc_o(14) <= cc(1); crc_o(13) <= cc(2); crc_o(12) <= cc(3);
|
535 |
|
|
crc_o(11) <= cc(4); crc_o(10) <= cc(5); crc_o(9) <= cc(6); crc_o(8) <= cc(7);
|
536 |
|
|
crc_o(7) <= cc(8); crc_o(6) <= cc(9); crc_o(5) <= cc(10); crc_o(4) <= cc(11);
|
537 |
|
|
crc_o(3) <= cc(12); crc_o(2) <= cc(13); crc_o(1) <= cc(14); crc_o(0) <= cc(15);
|
538 |
|
|
|
539 |
|
|
end architecture;
|
540 |
|
|
|
541 |
|
|
|
542 |
|
|
|
543 |
|
|
-------------------------------------------------------------------------------
|
544 |
|
|
-- MemoryDualPort
|
545 |
|
|
-- Generic synchronous memory with one read/write port and one read port.
|
546 |
|
|
-------------------------------------------------------------------------------
|
547 |
|
|
|
548 |
|
|
library ieee;
|
549 |
|
|
use ieee.std_logic_1164.all;
|
550 |
|
|
use ieee.numeric_std.all;
|
551 |
|
|
|
552 |
|
|
|
553 |
|
|
-------------------------------------------------------------------------------
|
554 |
|
|
-- Entity for MemoryDualPort.
|
555 |
|
|
-------------------------------------------------------------------------------
|
556 |
|
|
entity MemoryDualPort is
|
557 |
|
|
generic(
|
558 |
|
|
ADDRESS_WIDTH : natural := 1;
|
559 |
|
|
DATA_WIDTH : natural := 1);
|
560 |
|
|
port(
|
561 |
|
|
clkA_i : in std_logic;
|
562 |
|
|
enableA_i : in std_logic;
|
563 |
|
|
writeEnableA_i : in std_logic;
|
564 |
|
|
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
565 |
|
|
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
566 |
|
|
dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
567 |
|
|
|
568 |
|
|
clkB_i : in std_logic;
|
569 |
|
|
enableB_i : in std_logic;
|
570 |
|
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
571 |
|
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
572 |
|
|
end entity;
|
573 |
|
|
|
574 |
|
|
|
575 |
|
|
-------------------------------------------------------------------------------
|
576 |
|
|
-- Architecture for MemoryDualPort.
|
577 |
|
|
-------------------------------------------------------------------------------
|
578 |
|
|
architecture MemoryDualPortImpl of MemoryDualPort is
|
579 |
|
|
type MemoryType is array (natural range <>) of
|
580 |
|
|
std_logic_vector(DATA_WIDTH-1 downto 0);
|
581 |
|
|
|
582 |
|
|
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
|
583 |
|
|
|
584 |
|
|
begin
|
585 |
|
|
process(clkA_i)
|
586 |
|
|
begin
|
587 |
|
|
if (clkA_i'event and clkA_i = '1') then
|
588 |
|
|
if (enableA_i = '1') then
|
589 |
|
|
if (writeEnableA_i = '1') then
|
590 |
|
|
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
|
591 |
|
|
end if;
|
592 |
|
|
|
593 |
|
|
dataA_o <= memory(to_integer(unsigned(addressA_i)));
|
594 |
|
|
end if;
|
595 |
|
|
end if;
|
596 |
|
|
end process;
|
597 |
|
|
|
598 |
|
|
process(clkB_i)
|
599 |
|
|
begin
|
600 |
|
|
if (clkB_i'event and clkB_i = '1') then
|
601 |
|
|
if (enableB_i = '1') then
|
602 |
|
|
dataB_o <= memory(to_integer(unsigned(addressB_i)));
|
603 |
|
|
end if;
|
604 |
|
|
end if;
|
605 |
|
|
end process;
|
606 |
|
|
|
607 |
|
|
end architecture;
|
608 |
|
|
|
609 |
|
|
|
610 |
|
|
|
611 |
|
|
-------------------------------------------------------------------------------
|
612 |
|
|
-- MemorySimpleDualPort
|
613 |
|
|
-- Generic synchronous memory with one write port and one read port.
|
614 |
|
|
-------------------------------------------------------------------------------
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615 |
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|
616 |
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library ieee;
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617 |
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use ieee.std_logic_1164.all;
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618 |
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use ieee.numeric_std.all;
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619 |
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620 |
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621 |
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-------------------------------------------------------------------------------
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622 |
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-- Entity for MemorySimpleDualPort.
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623 |
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-------------------------------------------------------------------------------
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624 |
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entity MemorySimpleDualPort is
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625 |
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generic(
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626 |
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ADDRESS_WIDTH : natural := 1;
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627 |
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DATA_WIDTH : natural := 1);
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628 |
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port(
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629 |
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clkA_i : in std_logic;
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630 |
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enableA_i : in std_logic;
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631 |
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addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
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632 |
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dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
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633 |
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634 |
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clkB_i : in std_logic;
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635 |
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enableB_i : in std_logic;
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636 |
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addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
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637 |
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dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
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638 |
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end entity;
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639 |
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|
640 |
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|
641 |
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-------------------------------------------------------------------------------
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642 |
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-- Architecture for MemorySimpleDualPort.
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643 |
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-------------------------------------------------------------------------------
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644 |
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architecture MemorySimpleDualPortImpl of MemorySimpleDualPort is
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type MemoryType is array (natural range <>) of
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646 |
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std_logic_vector(DATA_WIDTH-1 downto 0);
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647 |
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648 |
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signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
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649 |
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650 |
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begin
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651 |
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process(clkA_i)
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652 |
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begin
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653 |
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if (clkA_i'event and clkA_i = '1') then
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654 |
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if (enableA_i = '1') then
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655 |
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memory(to_integer(unsigned(addressA_i))) <= dataA_i;
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656 |
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end if;
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657 |
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end if;
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658 |
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end process;
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659 |
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|
660 |
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process(clkB_i)
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661 |
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begin
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662 |
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if (clkB_i'event and clkB_i = '1') then
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663 |
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if (enableB_i = '1') then
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664 |
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dataB_o <= memory(to_integer(unsigned(addressB_i)));
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665 |
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end if;
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666 |
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end if;
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667 |
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end process;
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668 |
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669 |
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end architecture;
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670 |
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|
671 |
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|
672 |
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|
673 |
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-------------------------------------------------------------------------------
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674 |
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-- MemorySinglePort
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675 |
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-- Generic synchronous memory with one read/write port.
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676 |
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-------------------------------------------------------------------------------
|
677 |
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|
678 |
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library ieee;
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679 |
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use ieee.std_logic_1164.all;
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680 |
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use ieee.numeric_std.all;
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681 |
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|
682 |
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|
683 |
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-------------------------------------------------------------------------------
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684 |
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-- Entity for MemorySinglePort.
|
685 |
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-------------------------------------------------------------------------------
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686 |
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entity MemorySinglePort is
|
687 |
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generic(
|
688 |
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ADDRESS_WIDTH : natural := 1;
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689 |
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DATA_WIDTH : natural := 1);
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690 |
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port(
|
691 |
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clk_i : in std_logic;
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692 |
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enable_i : in std_logic;
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693 |
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writeEnable_i : in std_logic;
|
694 |
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address_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
695 |
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data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
696 |
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data_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
697 |
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end entity;
|
698 |
|
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|
699 |
|
|
|
700 |
|
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-------------------------------------------------------------------------------
|
701 |
|
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-- Architecture for MemorySinglePort.
|
702 |
|
|
-------------------------------------------------------------------------------
|
703 |
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|
architecture MemorySinglePortImpl of MemorySinglePort is
|
704 |
|
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type MemoryType is array (natural range <>) of
|
705 |
|
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std_logic_vector(DATA_WIDTH-1 downto 0);
|
706 |
|
|
|
707 |
|
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signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
|
708 |
|
|
|
709 |
|
|
begin
|
710 |
|
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process(clk_i)
|
711 |
|
|
begin
|
712 |
|
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if (clk_i'event and clk_i = '1') then
|
713 |
|
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if (enable_i = '1') then
|
714 |
|
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if (writeEnable_i = '1') then
|
715 |
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memory(to_integer(unsigned(address_i))) <= data_i;
|
716 |
|
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end if;
|
717 |
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|
718 |
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data_o <= memory(to_integer(unsigned(address_i)));
|
719 |
|
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end if;
|
720 |
|
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end if;
|
721 |
|
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end process;
|
722 |
|
|
|
723 |
|
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end architecture;
|
724 |
|
|
|
725 |
|
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|
726 |
|
|
|
727 |
|
|
|
728 |
|
|
-------------------------------------------------------------------------------
|
729 |
|
|
-- MemorySimpleDualPortAsync
|
730 |
|
|
-- Generic memory with one synchronous write port and one asynchronous read port.
|
731 |
|
|
-------------------------------------------------------------------------------
|
732 |
|
|
|
733 |
|
|
library ieee;
|
734 |
|
|
use ieee.std_logic_1164.all;
|
735 |
|
|
use ieee.numeric_std.all;
|
736 |
|
|
|
737 |
|
|
|
738 |
|
|
-------------------------------------------------------------------------------
|
739 |
|
|
-- Entity for MemorySimpleDualPortAsync.
|
740 |
|
|
-------------------------------------------------------------------------------
|
741 |
|
|
entity MemorySimpleDualPortAsync is
|
742 |
|
|
generic(
|
743 |
|
|
ADDRESS_WIDTH : natural := 1;
|
744 |
|
|
DATA_WIDTH : natural := 1;
|
745 |
|
|
INIT_VALUE : std_logic := 'U');
|
746 |
|
|
port(
|
747 |
|
|
clkA_i : in std_logic;
|
748 |
|
|
enableA_i : in std_logic;
|
749 |
|
|
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
750 |
|
|
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
751 |
|
|
|
752 |
|
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
753 |
|
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
754 |
|
|
end entity;
|
755 |
|
|
|
756 |
|
|
|
757 |
|
|
-------------------------------------------------------------------------------
|
758 |
|
|
-- Architecture for MemorySimpleDualPortAsync.
|
759 |
|
|
-------------------------------------------------------------------------------
|
760 |
|
|
architecture MemorySimpleDualPortAsyncImpl of MemorySimpleDualPortAsync is
|
761 |
|
|
type MemoryType is array (natural range <>) of
|
762 |
|
|
std_logic_vector(DATA_WIDTH-1 downto 0);
|
763 |
|
|
|
764 |
|
|
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1) := (others=>(others=>INIT_VALUE));
|
765 |
|
|
|
766 |
|
|
begin
|
767 |
|
|
process(clkA_i)
|
768 |
|
|
begin
|
769 |
|
|
if (clkA_i'event and clkA_i = '1') then
|
770 |
|
|
if (enableA_i = '1') then
|
771 |
|
|
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
|
772 |
|
|
end if;
|
773 |
|
|
end if;
|
774 |
|
|
end process;
|
775 |
|
|
|
776 |
|
|
dataB_o <= memory(to_integer(unsigned(addressB_i)));
|
777 |
|
|
|
778 |
|
|
end architecture;
|
779 |
|
|
|
780 |
|
|
|
781 |
|
|
|
782 |
|
|
|
783 |
|
|
|