OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [common/] [coreservices/] [icpuriscv.h] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 sergeykhbr
/**
2
 * @file
3
 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
4
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
5
 * @brief      RISC-V simulating CPU interface.
6
 */
7
 
8
#ifndef __DEBUGGER_SOCSIM_PLUGIN_CPU_RISCV_H__
9
#define __DEBUGGER_SOCSIM_PLUGIN_CPU_RISCV_H__
10
 
11
#include "iface.h"
12
#include <inttypes.h>
13
 
14
namespace debugger {
15
 
16
static const char *const IFACE_CPU_RISCV = "ICpuRiscV";
17
 
18
/** Signal types */
19
//static const int CPU_SIGNAL_RESET   = 0;
20
//static const int CPU_SIGNAL_EXT_IRQ = 1;
21
 
22
class ICpuRiscV : public IFace {
23
public:
24
    ICpuRiscV() : IFace(IFACE_CPU_RISCV) {}
25
};
26
 
27
}  // namespace debugger
28
 
29
#endif  // __DEBUGGER_SOCSIM_PLUGIN_CPU_RISCV_H__

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.