| 1 |
4 |
sergeykhbr |
/*
|
| 2 |
|
|
* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
|
| 3 |
|
|
*
|
| 4 |
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
| 5 |
|
|
* you may not use this file except in compliance with the License.
|
| 6 |
|
|
* You may obtain a copy of the License at
|
| 7 |
|
|
*
|
| 8 |
|
|
* http://www.apache.org/licenses/LICENSE-2.0
|
| 9 |
|
|
*
|
| 10 |
|
|
* Unless required by applicable law or agreed to in writing, software
|
| 11 |
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
| 12 |
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
| 13 |
|
|
* See the License for the specific language governing permissions and
|
| 14 |
|
|
* limitations under the License.
|
| 15 |
3 |
sergeykhbr |
*/
|
| 16 |
|
|
|
| 17 |
|
|
#include "icache.h"
|
| 18 |
|
|
|
| 19 |
|
|
namespace debugger {
|
| 20 |
|
|
|
| 21 |
|
|
ICache::ICache(sc_module_name name_) : sc_module(name_) {
|
| 22 |
|
|
SC_METHOD(comb);
|
| 23 |
|
|
sensitive << i_nrst;
|
| 24 |
|
|
sensitive << i_req_ctrl_valid;
|
| 25 |
|
|
sensitive << i_req_ctrl_addr;
|
| 26 |
|
|
sensitive << i_resp_mem_data_valid;
|
| 27 |
|
|
sensitive << i_resp_mem_data;
|
| 28 |
|
|
sensitive << i_resp_ctrl_ready;
|
| 29 |
|
|
sensitive << i_req_mem_ready;
|
| 30 |
4 |
sergeykhbr |
sensitive << r.iline[0].addr;
|
| 31 |
|
|
sensitive << r.iline[0].data;
|
| 32 |
|
|
sensitive << r.iline[1].addr;
|
| 33 |
|
|
sensitive << r.iline[1].data;
|
| 34 |
3 |
sergeykhbr |
sensitive << r.iline_addr_req;
|
| 35 |
4 |
sergeykhbr |
sensitive << r.addr_processing;
|
| 36 |
|
|
sensitive << r.double_req;
|
| 37 |
|
|
sensitive << r.delay_valid;
|
| 38 |
|
|
sensitive << r.delay_data;
|
| 39 |
3 |
sergeykhbr |
sensitive << r.state;
|
| 40 |
|
|
|
| 41 |
|
|
SC_METHOD(registers);
|
| 42 |
|
|
sensitive << i_clk.pos();
|
| 43 |
|
|
};
|
| 44 |
|
|
|
| 45 |
|
|
void ICache::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
|
| 46 |
|
|
if (o_vcd) {
|
| 47 |
|
|
sc_trace(o_vcd, i_nrst, "/top/cache0/i0/i_nrst");
|
| 48 |
|
|
sc_trace(o_vcd, i_req_ctrl_valid, "/top/cache0/i0/i_req_ctrl_valid");
|
| 49 |
|
|
sc_trace(o_vcd, i_req_ctrl_addr, "/top/cache0/i0/i_req_ctrl_addr");
|
| 50 |
|
|
sc_trace(o_vcd, o_req_ctrl_ready, "/top/cache0/i0/o_req_ctrl_ready");
|
| 51 |
|
|
sc_trace(o_vcd, o_req_mem_valid, "/top/cache0/i0/o_req_mem_valid");
|
| 52 |
|
|
sc_trace(o_vcd, o_req_mem_addr, "/top/cache0/i0/o_req_mem_addr");
|
| 53 |
|
|
sc_trace(o_vcd, i_req_mem_ready, "/top/cache0/i0/i_req_mem_ready");
|
| 54 |
|
|
sc_trace(o_vcd, i_resp_mem_data_valid, "/top/cache0/i0/i_resp_mem_data_valid");
|
| 55 |
|
|
sc_trace(o_vcd, i_resp_mem_data, "/top/cache0/i0/i_resp_mem_data");
|
| 56 |
|
|
sc_trace(o_vcd, o_resp_ctrl_valid, "/top/cache0/i0/o_resp_ctrl_valid");
|
| 57 |
|
|
sc_trace(o_vcd, i_resp_ctrl_ready, "/top/cache0/i0/i_resp_ctrl_ready");
|
| 58 |
|
|
sc_trace(o_vcd, o_resp_ctrl_addr, "/top/cache0/i0/o_resp_ctrl_addr");
|
| 59 |
|
|
sc_trace(o_vcd, o_resp_ctrl_data, "/top/cache0/i0/o_resp_ctrl_data");
|
| 60 |
4 |
sergeykhbr |
sc_trace(o_vcd, r.iline[0].addr, "/top/cache0/i0/r_iline(0)_addr");
|
| 61 |
|
|
sc_trace(o_vcd, r.iline[0].data, "/top/cache0/i0/r_iline(0)_data");
|
| 62 |
|
|
sc_trace(o_vcd, r.iline[1].addr, "/top/cache0/i0/r_iline(1)_addr");
|
| 63 |
|
|
sc_trace(o_vcd, r.iline[1].data, "/top/cache0/i0/r_iline(1)_data");
|
| 64 |
3 |
sergeykhbr |
sc_trace(o_vcd, r.iline_addr_req, "/top/cache0/i0/r_iline_addr_req");
|
| 65 |
4 |
sergeykhbr |
sc_trace(o_vcd, r.addr_processing, "/top/cache0/i0/r_addr_processing");
|
| 66 |
|
|
sc_trace(o_vcd, r.double_req, "/top/cache0/i0/double_req");
|
| 67 |
|
|
sc_trace(o_vcd, r.delay_valid, "/top/cache0/i0/r_delay_valid");
|
| 68 |
|
|
sc_trace(o_vcd, r.delay_data, "/top/cache0/i0/r_delay_valid");
|
| 69 |
3 |
sergeykhbr |
sc_trace(o_vcd, r.state, "/top/cache0/i0/r_state");
|
| 70 |
4 |
sergeykhbr |
sc_trace(o_vcd, w_need_mem_req, "/top/cache0/i0/w_need_mem_req");
|
| 71 |
|
|
sc_trace(o_vcd, wb_l[0].hit, "/top/cache0/i0/wb_l(0)_hit");
|
| 72 |
|
|
sc_trace(o_vcd, wb_l[1].hit, "/top/cache0/i0/wb_l(1)_hit");
|
| 73 |
|
|
sc_trace(o_vcd, wb_l[0].hit_data, "/top/cache0/i0/wb_l(0)_hit_data");
|
| 74 |
|
|
sc_trace(o_vcd, wb_l[1].hit_data, "/top/cache0/i0/wb_l(1)_hit_data");
|
| 75 |
|
|
sc_trace(o_vcd, wb_hit_word, "/top/cache0/i0/wb_hit_word");
|
| 76 |
|
|
sc_trace(o_vcd, wb_l[0].hit_hold, "/top/cache0/i0/wb_l(0).hit_hold");
|
| 77 |
|
|
sc_trace(o_vcd, wb_l[1].hit_hold, "/top/cache0/i0/wb_l(1).hit_hold");
|
| 78 |
|
|
sc_trace(o_vcd, w_reuse_lastline, "/top/cache0/i0/w_reuse_lastline");
|
| 79 |
|
|
sc_trace(o_vcd, w_wait_response, "/top/cache0/i0/w_wait_response");
|
| 80 |
3 |
sergeykhbr |
}
|
| 81 |
|
|
}
|
| 82 |
|
|
|
| 83 |
|
|
void ICache::comb() {
|
| 84 |
|
|
// Instruction cache:
|
| 85 |
|
|
bool w_o_req_ctrl_ready;
|
| 86 |
|
|
bool w_o_req_mem_valid;
|
| 87 |
|
|
sc_uint<BUS_ADDR_WIDTH> wb_o_req_mem_addr;
|
| 88 |
4 |
sergeykhbr |
bool w_req_ctrl_valid;
|
| 89 |
3 |
sergeykhbr |
bool w_req_fire;
|
| 90 |
|
|
bool w_o_resp_valid;
|
| 91 |
|
|
sc_uint<BUS_ADDR_WIDTH> wb_o_resp_addr;
|
| 92 |
|
|
sc_uint<32> wb_o_resp_data;
|
| 93 |
4 |
sergeykhbr |
sc_uint<BUS_ADDR_WIDTH> wb_req_addr[2];
|
| 94 |
|
|
sc_uint<BUS_ADDR_WIDTH> wb_hold_addr[2];
|
| 95 |
3 |
sergeykhbr |
|
| 96 |
|
|
v = r;
|
| 97 |
|
|
|
| 98 |
4 |
sergeykhbr |
w_wait_response = 0;
|
| 99 |
|
|
if (r.state.read() == State_WaitResp && i_resp_mem_data_valid.read() == 0) {
|
| 100 |
|
|
w_wait_response = 1;
|
| 101 |
3 |
sergeykhbr |
}
|
| 102 |
4 |
sergeykhbr |
w_req_ctrl_valid = !w_wait_response
|
| 103 |
|
|
&& (i_req_ctrl_valid.read() || r.double_req.read());
|
| 104 |
|
|
wb_req_addr[0] = i_req_ctrl_addr.read();
|
| 105 |
|
|
wb_req_addr[1] = i_req_ctrl_addr.read() + 2;
|
| 106 |
|
|
|
| 107 |
|
|
wb_hold_addr[0] = r.addr_processing.read();
|
| 108 |
|
|
wb_hold_addr[1] = r.addr_processing.read() + 2;
|
| 109 |
|
|
|
| 110 |
|
|
for (int i = 0; i < ILINE_TOTAL; i++) {
|
| 111 |
|
|
wb_l[i].hit = 0;
|
| 112 |
|
|
wb_l[i].hit_data = 0;
|
| 113 |
|
|
if (wb_req_addr[i](BUS_ADDR_WIDTH-1, 3) == r.iline[0].addr.read()) {
|
| 114 |
|
|
wb_l[i].hit[Hit_Line1] = w_req_ctrl_valid;
|
| 115 |
|
|
wb_l[i].hit_data = r.iline[0].data.read();
|
| 116 |
|
|
} else if (wb_req_addr[i](BUS_ADDR_WIDTH-1, 3) ==
|
| 117 |
|
|
r.iline[1].addr.read()) {
|
| 118 |
|
|
wb_l[i].hit[Hit_Line2] = w_req_ctrl_valid;
|
| 119 |
|
|
wb_l[i].hit_data = r.iline[1].data.read();
|
| 120 |
|
|
} else if (wb_req_addr[i](BUS_ADDR_WIDTH-1, 3) ==
|
| 121 |
|
|
r.iline_addr_req.read()(BUS_ADDR_WIDTH-1, 3)) {
|
| 122 |
|
|
wb_l[i].hit[Hit_Response] = i_resp_mem_data_valid.read();
|
| 123 |
|
|
wb_l[i].hit_data = i_resp_mem_data.read();
|
| 124 |
|
|
}
|
| 125 |
|
|
|
| 126 |
|
|
wb_l[i].hit_hold = 0;
|
| 127 |
|
|
wb_l[i].hold_data = 0;
|
| 128 |
|
|
if (wb_hold_addr[i](BUS_ADDR_WIDTH-1, 3) == r.iline[0].addr.read()) {
|
| 129 |
|
|
wb_l[i].hit_hold[Hit_Line1] = 1;
|
| 130 |
|
|
wb_l[i].hold_data = r.iline[0].data.read();
|
| 131 |
|
|
} else if (wb_hold_addr[i](BUS_ADDR_WIDTH-1, 3) ==
|
| 132 |
|
|
r.iline[1].addr.read()) {
|
| 133 |
|
|
wb_l[i].hit_hold[Hit_Line2] = 1;
|
| 134 |
|
|
wb_l[i].hold_data = r.iline[1].data.read();
|
| 135 |
|
|
} else if (wb_hold_addr[i](BUS_ADDR_WIDTH-1, 3) ==
|
| 136 |
|
|
r.iline_addr_req.read()(BUS_ADDR_WIDTH-1, 3)) {
|
| 137 |
|
|
wb_l[i].hold_data = i_resp_mem_data.read();
|
| 138 |
|
|
}
|
| 139 |
3 |
sergeykhbr |
}
|
| 140 |
|
|
|
| 141 |
4 |
sergeykhbr |
wb_hit_word = 0;
|
| 142 |
|
|
w_need_mem_req = 1;
|
| 143 |
|
|
if (wb_l[0].hit != 0 && wb_l[1].hit != 0) {
|
| 144 |
|
|
w_need_mem_req = 0;
|
| 145 |
|
|
}
|
| 146 |
|
|
switch (r.addr_processing.read()(2, 1)) {
|
| 147 |
|
|
case 0:
|
| 148 |
|
|
wb_hit_word = wb_l[0].hold_data(31, 0);
|
| 149 |
|
|
break;
|
| 150 |
|
|
case 1:
|
| 151 |
|
|
wb_hit_word = wb_l[0].hold_data(47, 16);
|
| 152 |
|
|
break;
|
| 153 |
|
|
case 2:
|
| 154 |
|
|
wb_hit_word = wb_l[0].hold_data(63, 32);
|
| 155 |
|
|
break;
|
| 156 |
|
|
default:
|
| 157 |
|
|
wb_hit_word = (wb_l[1].hold_data(15, 0) << 16)
|
| 158 |
|
|
| wb_l[0].hold_data(63, 48);
|
| 159 |
|
|
}
|
| 160 |
|
|
|
| 161 |
|
|
if (w_req_ctrl_valid && !w_need_mem_req) {
|
| 162 |
|
|
v.delay_valid = 1;
|
| 163 |
|
|
switch (i_req_ctrl_addr.read()(2, 1)) {
|
| 164 |
|
|
case 0:
|
| 165 |
|
|
v.delay_data = wb_l[0].hit_data(31, 0);
|
| 166 |
|
|
break;
|
| 167 |
|
|
case 1:
|
| 168 |
|
|
v.delay_data = wb_l[0].hit_data(47, 16);
|
| 169 |
|
|
break;
|
| 170 |
|
|
case 2:
|
| 171 |
|
|
v.delay_data = wb_l[0].hit_data(63, 32);
|
| 172 |
|
|
break;
|
| 173 |
|
|
default:
|
| 174 |
|
|
v.delay_data = (wb_l[1].hit_data(15, 0) << 16)
|
| 175 |
|
|
| wb_l[0].hit_data(63, 48);
|
| 176 |
|
|
}
|
| 177 |
|
|
} else if (i_resp_ctrl_ready.read()) {
|
| 178 |
|
|
v.delay_valid = 0;
|
| 179 |
|
|
v.delay_data = 0;
|
| 180 |
|
|
}
|
| 181 |
|
|
|
| 182 |
|
|
w_o_req_mem_valid = w_need_mem_req & w_req_ctrl_valid;
|
| 183 |
|
|
if (r.double_req.read()) {
|
| 184 |
|
|
if ((r.addr_processing.read()(BUS_ADDR_WIDTH-1, 3) ==
|
| 185 |
|
|
r.iline_addr_req.read()(BUS_ADDR_WIDTH-1, 3))
|
| 186 |
|
|
|| (r.addr_processing.read()(BUS_ADDR_WIDTH-1, 3) ==
|
| 187 |
|
|
wb_hold_addr[0](BUS_ADDR_WIDTH-1, 3))
|
| 188 |
|
|
) {
|
| 189 |
|
|
wb_o_req_mem_addr = wb_hold_addr[1](BUS_ADDR_WIDTH-1, 3) << 3;
|
| 190 |
|
|
} else {
|
| 191 |
|
|
wb_o_req_mem_addr = wb_hold_addr[0](BUS_ADDR_WIDTH-1, 3) << 3;
|
| 192 |
|
|
}
|
| 193 |
|
|
} else if (wb_l[0].hit == 0) {
|
| 194 |
|
|
wb_o_req_mem_addr = wb_req_addr[0](BUS_ADDR_WIDTH-1, 3) << 3;
|
| 195 |
|
|
} else {
|
| 196 |
|
|
wb_o_req_mem_addr = wb_req_addr[1](BUS_ADDR_WIDTH-1, 3) << 3;
|
| 197 |
|
|
}
|
| 198 |
|
|
|
| 199 |
|
|
w_o_req_ctrl_ready = !w_need_mem_req
|
| 200 |
|
|
| (i_req_mem_ready.read() & !w_wait_response);
|
| 201 |
|
|
w_req_fire = w_req_ctrl_valid && w_o_req_ctrl_ready;
|
| 202 |
|
|
|
| 203 |
|
|
if ((w_o_req_mem_valid && i_req_mem_ready.read() && !w_wait_response)
|
| 204 |
|
|
|| r.double_req.read()) {
|
| 205 |
|
|
v.iline_addr_req = wb_o_req_mem_addr;
|
| 206 |
|
|
}
|
| 207 |
|
|
|
| 208 |
3 |
sergeykhbr |
switch (r.state.read()) {
|
| 209 |
|
|
case State_Idle:
|
| 210 |
4 |
sergeykhbr |
if (w_req_ctrl_valid) {
|
| 211 |
|
|
if (!w_need_mem_req) {
|
| 212 |
3 |
sergeykhbr |
v.state = State_WaitAccept;
|
| 213 |
|
|
} else if (i_req_mem_ready.read()) {
|
| 214 |
|
|
v.state = State_WaitResp;
|
| 215 |
|
|
} else {
|
| 216 |
|
|
v.state = State_WaitGrant;
|
| 217 |
|
|
}
|
| 218 |
|
|
}
|
| 219 |
|
|
break;
|
| 220 |
|
|
case State_WaitGrant:
|
| 221 |
|
|
if (i_req_mem_ready.read()) {
|
| 222 |
|
|
v.state = State_WaitResp;
|
| 223 |
4 |
sergeykhbr |
} else if (!w_need_mem_req) {
|
| 224 |
3 |
sergeykhbr |
/** Fetcher can change request address while request wasn't
|
| 225 |
|
|
* accepteed. */
|
| 226 |
|
|
v.state = State_WaitAccept;
|
| 227 |
|
|
}
|
| 228 |
|
|
break;
|
| 229 |
|
|
case State_WaitResp:
|
| 230 |
|
|
if (i_resp_mem_data_valid.read()) {
|
| 231 |
|
|
if (!i_resp_ctrl_ready.read()) {
|
| 232 |
|
|
v.state = State_WaitAccept;
|
| 233 |
4 |
sergeykhbr |
} else if (!w_req_ctrl_valid) {
|
| 234 |
3 |
sergeykhbr |
v.state = State_Idle;
|
| 235 |
|
|
} else {
|
| 236 |
|
|
// New request
|
| 237 |
4 |
sergeykhbr |
if (!w_need_mem_req) {
|
| 238 |
3 |
sergeykhbr |
v.state = State_WaitAccept;
|
| 239 |
|
|
} else if (i_req_mem_ready.read()) {
|
| 240 |
|
|
v.state = State_WaitResp;
|
| 241 |
|
|
} else {
|
| 242 |
|
|
v.state = State_WaitGrant;
|
| 243 |
|
|
}
|
| 244 |
|
|
}
|
| 245 |
|
|
}
|
| 246 |
|
|
break;
|
| 247 |
|
|
case State_WaitAccept:
|
| 248 |
|
|
if (i_resp_ctrl_ready.read()) {
|
| 249 |
4 |
sergeykhbr |
if (!w_req_ctrl_valid) {
|
| 250 |
3 |
sergeykhbr |
v.state = State_Idle;
|
| 251 |
|
|
} else {
|
| 252 |
4 |
sergeykhbr |
if (!w_need_mem_req) {
|
| 253 |
3 |
sergeykhbr |
v.state = State_WaitAccept;
|
| 254 |
|
|
} else if (i_req_mem_ready.read()) {
|
| 255 |
|
|
v.state = State_WaitResp;
|
| 256 |
|
|
} else {
|
| 257 |
|
|
v.state = State_WaitGrant;
|
| 258 |
|
|
}
|
| 259 |
|
|
}
|
| 260 |
|
|
}
|
| 261 |
|
|
break;
|
| 262 |
|
|
default:;
|
| 263 |
|
|
}
|
| 264 |
|
|
|
| 265 |
|
|
if (w_req_fire) {
|
| 266 |
4 |
sergeykhbr |
v.double_req = 0;
|
| 267 |
|
|
if (i_req_ctrl_addr.read()(2, 1) == 0x3
|
| 268 |
|
|
&& wb_l[0].hit == 0 && wb_l[1].hit == 0
|
| 269 |
|
|
&& r.double_req.read() == 0) {
|
| 270 |
|
|
v.double_req = 1;
|
| 271 |
3 |
sergeykhbr |
}
|
| 272 |
4 |
sergeykhbr |
if (!r.double_req.read()) {
|
| 273 |
|
|
v.addr_processing = i_req_ctrl_addr;
|
| 274 |
|
|
}
|
| 275 |
3 |
sergeykhbr |
}
|
| 276 |
4 |
sergeykhbr |
|
| 277 |
|
|
w_reuse_lastline = 0;
|
| 278 |
|
|
|
| 279 |
3 |
sergeykhbr |
if (i_resp_mem_data_valid.read()) {
|
| 280 |
4 |
sergeykhbr |
/** Condition to avoid removing the last line:
|
| 281 |
|
|
*/
|
| 282 |
|
|
if (i_resp_ctrl_ready.read()) {
|
| 283 |
|
|
if ((wb_l[0].hit[Hit_Line2] || wb_l[1].hit[Hit_Line2]) == 1
|
| 284 |
|
|
&& r.iline[1].addr.read()
|
| 285 |
|
|
!= i_req_ctrl_addr.read()(BUS_ADDR_WIDTH-1, 3)) {
|
| 286 |
|
|
w_reuse_lastline = w_need_mem_req;
|
| 287 |
|
|
}
|
| 288 |
3 |
sergeykhbr |
} else {
|
| 289 |
4 |
sergeykhbr |
if ((wb_l[0].hit_hold[Hit_Line2] || wb_l[1].hit_hold[Hit_Line2]) == 1
|
| 290 |
|
|
&& (wb_l[0].hit_hold[Hit_Line1] || wb_l[1].hit_hold[Hit_Line1]) == 0
|
| 291 |
|
|
&& r.iline[1].addr.read()
|
| 292 |
|
|
!= r.iline_addr_req.read()(BUS_ADDR_WIDTH-1, 3)) {
|
| 293 |
|
|
w_reuse_lastline = 1;
|
| 294 |
3 |
sergeykhbr |
}
|
| 295 |
|
|
}
|
| 296 |
4 |
sergeykhbr |
if (!w_reuse_lastline) {
|
| 297 |
|
|
v.iline[1].addr = r.iline[0].addr;
|
| 298 |
|
|
v.iline[1].data = r.iline[0].data;
|
| 299 |
3 |
sergeykhbr |
}
|
| 300 |
4 |
sergeykhbr |
|
| 301 |
|
|
v.iline[0].addr = r.iline_addr_req.read()(BUS_ADDR_WIDTH-1, 3);
|
| 302 |
|
|
v.iline[0].data = i_resp_mem_data;
|
| 303 |
3 |
sergeykhbr |
}
|
| 304 |
|
|
|
| 305 |
4 |
sergeykhbr |
if (r.state.read() == State_WaitAccept) {
|
| 306 |
|
|
w_o_resp_valid = !r.double_req.read();
|
| 307 |
|
|
} else {
|
| 308 |
|
|
w_o_resp_valid = i_resp_mem_data_valid && !r.double_req.read();
|
| 309 |
|
|
}
|
| 310 |
|
|
if (r.delay_valid.read()) {
|
| 311 |
|
|
wb_o_resp_data = r.delay_data.read();
|
| 312 |
|
|
} else {
|
| 313 |
|
|
wb_o_resp_data = wb_hit_word;
|
| 314 |
|
|
}
|
| 315 |
|
|
wb_o_resp_addr = r.addr_processing;
|
| 316 |
3 |
sergeykhbr |
|
| 317 |
4 |
sergeykhbr |
|
| 318 |
3 |
sergeykhbr |
if (!i_nrst.read()) {
|
| 319 |
4 |
sergeykhbr |
v.iline[0].addr = ~0;
|
| 320 |
|
|
v.iline[0].data = 0;
|
| 321 |
|
|
v.iline[1].addr = ~0;
|
| 322 |
|
|
v.iline[1].data = 0;
|
| 323 |
3 |
sergeykhbr |
v.iline_addr_req = 0;
|
| 324 |
4 |
sergeykhbr |
v.addr_processing = 0;
|
| 325 |
3 |
sergeykhbr |
v.state = State_Idle;
|
| 326 |
4 |
sergeykhbr |
v.double_req = 0;
|
| 327 |
|
|
v.delay_valid = 0;
|
| 328 |
|
|
v.delay_data = 0;
|
| 329 |
3 |
sergeykhbr |
}
|
| 330 |
|
|
|
| 331 |
|
|
o_req_ctrl_ready = w_o_req_ctrl_ready;
|
| 332 |
|
|
|
| 333 |
|
|
o_req_mem_valid = w_o_req_mem_valid;
|
| 334 |
|
|
o_req_mem_addr = wb_o_req_mem_addr;
|
| 335 |
|
|
o_req_mem_write = false;
|
| 336 |
|
|
o_req_mem_strob = 0;
|
| 337 |
|
|
o_req_mem_data = 0;
|
| 338 |
|
|
|
| 339 |
|
|
o_resp_ctrl_valid = w_o_resp_valid;
|
| 340 |
|
|
o_resp_ctrl_data = wb_o_resp_data;
|
| 341 |
|
|
o_resp_ctrl_addr = wb_o_resp_addr;
|
| 342 |
|
|
o_istate = r.state;
|
| 343 |
|
|
}
|
| 344 |
|
|
|
| 345 |
|
|
void ICache::registers() {
|
| 346 |
|
|
r = v;
|
| 347 |
|
|
}
|
| 348 |
|
|
|
| 349 |
|
|
#ifdef DBG_ICACHE_TB
|
| 350 |
|
|
void ICache_tb::comb0() {
|
| 351 |
|
|
v = r;
|
| 352 |
|
|
v.clk_cnt = r.clk_cnt.read() + 1;
|
| 353 |
|
|
|
| 354 |
|
|
if (r.clk_cnt.read() < 10) {
|
| 355 |
|
|
w_nrst = 0;
|
| 356 |
|
|
v.mem_state = 0;
|
| 357 |
|
|
v.mem_cnt = 0;
|
| 358 |
|
|
v.fetch_state = 0;
|
| 359 |
|
|
v.fetch_cnt = 0;
|
| 360 |
|
|
return;
|
| 361 |
|
|
}
|
| 362 |
|
|
w_nrst = 1;
|
| 363 |
|
|
|
| 364 |
|
|
w_req_ctrl_valid = 0;
|
| 365 |
|
|
wb_req_ctrl_addr = 0;
|
| 366 |
|
|
w_resp_ctrl_ready = 0;
|
| 367 |
|
|
|
| 368 |
|
|
struct FetchDelayType {
|
| 369 |
|
|
uint32_t raddr;
|
| 370 |
|
|
int req_wait;
|
| 371 |
|
|
int accept_wait;
|
| 372 |
|
|
};
|
| 373 |
|
|
static const FetchDelayType RADDR[4] = {{0x100008f4, 0, 0}, {0x100007b0, 0, 0}, {0x100008f0, 2, 0}, {0x100007b4, 0, 0}};
|
| 374 |
|
|
struct MemDelayType {
|
| 375 |
|
|
unsigned rdy_wait;
|
| 376 |
|
|
unsigned valid_wait;
|
| 377 |
|
|
};
|
| 378 |
|
|
//static const MemDelayType MEM_DELAY[4] = {{2,3}, {2,3}, {0,0}, {0,0}};
|
| 379 |
|
|
static const MemDelayType MEM_DELAY[4] = {{0,0}, {0,0}, {5,0}, {5,0}};
|
| 380 |
|
|
|
| 381 |
|
|
|
| 382 |
|
|
// fetch model:
|
| 383 |
|
|
w_resp_ctrl_ready = 0;
|
| 384 |
|
|
if (r.clk_cnt.read() >= 15) {
|
| 385 |
|
|
switch (r.fetch_state.read()) {
|
| 386 |
|
|
case 0:
|
| 387 |
|
|
if (r.fetch_cnt.read() < 4) {
|
| 388 |
|
|
if (RADDR[r.fetch_cnt.read()].req_wait == 0) {
|
| 389 |
|
|
w_req_ctrl_valid = 1;
|
| 390 |
|
|
wb_req_ctrl_addr = RADDR[r.fetch_cnt.read()].raddr;
|
| 391 |
|
|
if (w_req_ctrl_ready) {
|
| 392 |
|
|
v.fetch_state = 3;
|
| 393 |
|
|
v.fetch_cnt = r.fetch_cnt.read() + 1;
|
| 394 |
|
|
v.fetch_wait_cnt = RADDR[r.fetch_cnt.read()].accept_wait;
|
| 395 |
|
|
} else {
|
| 396 |
|
|
v.fetch_state = 2;
|
| 397 |
|
|
}
|
| 398 |
|
|
} else {
|
| 399 |
|
|
if (RADDR[r.fetch_cnt.read()].req_wait == 1) {
|
| 400 |
|
|
v.fetch_state = 2;
|
| 401 |
|
|
} else {
|
| 402 |
|
|
v.fetch_state = 1;
|
| 403 |
|
|
}
|
| 404 |
|
|
v.fetch_wait_cnt = RADDR[r.fetch_cnt.read()].req_wait;
|
| 405 |
|
|
}
|
| 406 |
|
|
}
|
| 407 |
|
|
break;
|
| 408 |
|
|
case 1:
|
| 409 |
|
|
// wait to request:
|
| 410 |
|
|
v.fetch_wait_cnt = r.fetch_wait_cnt.read() - 1;
|
| 411 |
|
|
if (r.fetch_wait_cnt.read() == 1) {
|
| 412 |
|
|
v.fetch_state = 2;
|
| 413 |
|
|
}
|
| 414 |
|
|
break;
|
| 415 |
|
|
case 2:// wait ready signal
|
| 416 |
|
|
w_req_ctrl_valid = 1;
|
| 417 |
|
|
wb_req_ctrl_addr = RADDR[r.fetch_cnt.read()].raddr;
|
| 418 |
|
|
if (w_req_ctrl_ready) {
|
| 419 |
|
|
v.fetch_state = 3;
|
| 420 |
|
|
v.fetch_cnt = r.fetch_cnt.read() + 1;
|
| 421 |
|
|
v.fetch_wait_cnt = RADDR[r.fetch_cnt.read()].accept_wait;
|
| 422 |
|
|
}
|
| 423 |
|
|
break;
|
| 424 |
|
|
case 3: // wait valid signal:
|
| 425 |
|
|
if (w_resp_ctrl_valid) {
|
| 426 |
|
|
w_resp_ctrl_ready = 1;
|
| 427 |
|
|
if (r.fetch_wait_cnt.read()) {
|
| 428 |
|
|
v.fetch_wait_cnt = r.fetch_wait_cnt.read() - 1;
|
| 429 |
|
|
w_resp_ctrl_ready = 0;
|
| 430 |
|
|
} else if (r.fetch_cnt.read() < 4) {
|
| 431 |
|
|
if (RADDR[r.fetch_cnt.read()].req_wait == 0) {
|
| 432 |
|
|
w_req_ctrl_valid = 1;
|
| 433 |
|
|
wb_req_ctrl_addr = RADDR[r.fetch_cnt.read()].raddr;
|
| 434 |
|
|
if (w_req_ctrl_ready) {
|
| 435 |
|
|
v.fetch_state = 3;
|
| 436 |
|
|
v.fetch_cnt = r.fetch_cnt.read() + 1;
|
| 437 |
|
|
v.fetch_wait_cnt = RADDR[r.fetch_cnt.read()].accept_wait;
|
| 438 |
|
|
} else {
|
| 439 |
|
|
v.fetch_state = 2;
|
| 440 |
|
|
}
|
| 441 |
|
|
} else {
|
| 442 |
|
|
if (RADDR[r.fetch_cnt.read()].req_wait == 1) {
|
| 443 |
|
|
v.fetch_state = 2;
|
| 444 |
|
|
} else {
|
| 445 |
|
|
v.fetch_state = 1;
|
| 446 |
|
|
}
|
| 447 |
|
|
v.fetch_wait_cnt = RADDR[r.fetch_cnt.read()].req_wait;
|
| 448 |
|
|
}
|
| 449 |
|
|
} else {
|
| 450 |
|
|
v.fetch_state = 0;
|
| 451 |
|
|
}
|
| 452 |
|
|
}
|
| 453 |
|
|
break;
|
| 454 |
|
|
default:;
|
| 455 |
|
|
}
|
| 456 |
|
|
}
|
| 457 |
|
|
|
| 458 |
|
|
if (r.clk_cnt.read() == 21) {
|
| 459 |
|
|
wb_req_ctrl_addr = 0x100008f8;
|
| 460 |
|
|
} else if (r.clk_cnt.read() == 22) {
|
| 461 |
|
|
wb_req_ctrl_addr = 0x100007b4;
|
| 462 |
|
|
}
|
| 463 |
|
|
|
| 464 |
|
|
|
| 465 |
|
|
// Memory model:
|
| 466 |
|
|
w_req_mem_ready = 0;
|
| 467 |
|
|
w_resp_mem_data_valid = 0;
|
| 468 |
|
|
|
| 469 |
|
|
switch (r.mem_state.read()) {
|
| 470 |
|
|
case 0: // MemIdle
|
| 471 |
|
|
if (w_req_mem_valid && r.mem_cnt.read() < 4) {
|
| 472 |
|
|
if (MEM_DELAY[r.mem_cnt.read()].rdy_wait == 0) {
|
| 473 |
|
|
if (MEM_DELAY[r.mem_cnt.read()].valid_wait == 0) {
|
| 474 |
|
|
v.mem_state = 3;
|
| 475 |
|
|
v.mem_raddr = wb_req_mem_addr;
|
| 476 |
|
|
w_req_mem_ready = 1;
|
| 477 |
|
|
v.mem_cnt = r.mem_cnt.read() + 1;
|
| 478 |
|
|
} else {
|
| 479 |
|
|
v.mem_state = 2;
|
| 480 |
|
|
v.mem_wait_cnt = MEM_DELAY[r.mem_cnt.read()].valid_wait;
|
| 481 |
|
|
}
|
| 482 |
|
|
} else {
|
| 483 |
|
|
v.mem_state = 1;
|
| 484 |
|
|
v.mem_wait_cnt = MEM_DELAY[r.mem_cnt.read()].rdy_wait;
|
| 485 |
|
|
}
|
| 486 |
|
|
}
|
| 487 |
|
|
break;
|
| 488 |
|
|
case 1:
|
| 489 |
|
|
v.mem_wait_cnt = r.mem_wait_cnt.read() - 1;
|
| 490 |
|
|
if (r.mem_wait_cnt.read() == 1) {
|
| 491 |
|
|
if (w_req_mem_valid) {
|
| 492 |
|
|
v.mem_raddr = wb_req_mem_addr;
|
| 493 |
|
|
w_req_mem_ready = 1;
|
| 494 |
|
|
v.mem_cnt = r.mem_cnt.read() + 1;
|
| 495 |
|
|
if (MEM_DELAY[r.mem_cnt.read()].valid_wait == 0) {
|
| 496 |
|
|
v.mem_state = 3;
|
| 497 |
|
|
} else {
|
| 498 |
|
|
v.mem_state = 2;
|
| 499 |
|
|
v.mem_wait_cnt = MEM_DELAY[r.mem_cnt.read()].valid_wait;
|
| 500 |
|
|
}
|
| 501 |
|
|
} else {
|
| 502 |
|
|
v.mem_state = 0;
|
| 503 |
|
|
}
|
| 504 |
|
|
}
|
| 505 |
|
|
break;
|
| 506 |
|
|
case 2:
|
| 507 |
|
|
v.mem_wait_cnt = r.mem_wait_cnt.read() - 1;
|
| 508 |
|
|
if (r.mem_wait_cnt.read() == 1) {
|
| 509 |
|
|
v.mem_state = 3;
|
| 510 |
|
|
}
|
| 511 |
|
|
break;
|
| 512 |
|
|
case 3:
|
| 513 |
|
|
w_resp_mem_data_valid = 1;
|
| 514 |
|
|
if (r.mem_raddr.read() == 0x100008f0) {
|
| 515 |
|
|
wb_resp_mem_data = 0xffdff06fea9ff0efull;
|
| 516 |
|
|
} else if (r.mem_raddr.read() == 0x100007b0) {
|
| 517 |
|
|
wb_resp_mem_data = 0xfa0a0a1300004a17;
|
| 518 |
|
|
}
|
| 519 |
|
|
|
| 520 |
|
|
if (w_req_mem_valid && r.mem_cnt.read() < 4) {
|
| 521 |
|
|
if (MEM_DELAY[r.mem_cnt.read()].rdy_wait == 0) {
|
| 522 |
|
|
if (MEM_DELAY[r.mem_cnt.read()].valid_wait == 0) {
|
| 523 |
|
|
v.mem_state = 3;
|
| 524 |
|
|
v.mem_raddr = wb_req_mem_addr;
|
| 525 |
|
|
w_req_mem_ready = 1;
|
| 526 |
|
|
v.mem_cnt = r.mem_cnt.read() + 1;
|
| 527 |
|
|
} else {
|
| 528 |
|
|
v.mem_state = 2;
|
| 529 |
|
|
v.mem_wait_cnt = MEM_DELAY[r.mem_cnt.read()].valid_wait;
|
| 530 |
|
|
}
|
| 531 |
|
|
} else {
|
| 532 |
|
|
v.mem_state = 1;
|
| 533 |
|
|
v.mem_wait_cnt = MEM_DELAY[r.mem_cnt.read()].rdy_wait;
|
| 534 |
|
|
}
|
| 535 |
|
|
} else {
|
| 536 |
|
|
v.mem_state = 0;
|
| 537 |
|
|
}
|
| 538 |
|
|
break;
|
| 539 |
|
|
default:;
|
| 540 |
|
|
}
|
| 541 |
|
|
|
| 542 |
|
|
|
| 543 |
|
|
}
|
| 544 |
|
|
#endif
|
| 545 |
|
|
|
| 546 |
|
|
} // namespace debugger
|
| 547 |
|
|
|
