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sergeykhbr |
/** @page verification_page RTL Verification
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@section sim_tb_link Top-level simulation
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@par Test-bench example
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Use file work/tb/riscv_soc_tb.vhd to run simulation scenario. You can
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get the following time diagram after simulation of 2 ms interval.
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@latexonly {\includegraphics[scale=0.75]{../doxygen/pics/soc_sim.png}} @endlatexonly
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@note Simulation behaviour depends of current firmware image. It may
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significantly differs in a new releases either as Zephyr OS kernel
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image is absolutely different relative GNSS FW image.
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Some FW versions can detect RTL simulation target by reading 'Target'
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Register in PnP device that allows to speed-up simulation
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by removing some delays and changing Devices IO parameters (UART speed
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for example).
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@par Running on FPGA
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Supported FPGA:
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ML605 with Virtex6 FPGA using ISE 14.7 (default).
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KC705 with Kintex7 FPGA using Vivado 2015.4.
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@warning In a case of using GNSS FW without connected RF front-end
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don't forget to switch ON DIP[0] (i_int_clkrf) to enable
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Test Mode. Otherwise there
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wouldn't be generated interrupts and, as result, no UART
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output.
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@section auto_compare_page VCD-files automatic comparision
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@subsection gen_sysc_vcd Generating VCD-pattern form SystemC model
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Edit the following attributes in SystemC target script
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debugger/targets/sysc_river_gui.json to enable vcd-file generation.
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['InVcdFile','i_river','Non empty string enables generation of stimulus VCD file'].
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['OutVcdFile','o_river','Non empty string enables VCD file with reference signals']
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Files i_river.vcd and o_river.vcd will be generated.
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The first one will be used as a RTL simulation stimulus to generate input
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signals. The second one as a reference.
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@subsection run_vcd_compare Compare RIVER SystemC model relative RTL
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Run simulation in ModelSim with the following commands using correct pathes
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for your host:
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vcd2wlf E:/Projects/GitProjects/riscv_vhdl/debugger/win32build/Debug/i_river.vcd -o e:/i_river.wlf
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vcd2wlf E:/Projects/GitProjects/riscv_vhdl/debugger/win32build/Debug/o_river.vcd -o e:/o_river.wlf
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wlf2vcd e:/i_river.wlf -o e:/i_river.vcd
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vsim -t 1ps -vcdstim E:/i_river.vcd riverlib.RiverTop
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vsim -view e:/o_river.wlf
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add wave o_river:/SystemC/o_*
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add wave sim:/rivertop/*
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run 500us
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compare start o_river sim
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compare add -wave sim:/RiverTop/o_req_mem_valid o_river:/SystemC/o_req_mem_valid
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compare add -wave sim:/RiverTop/o_req_mem_write o_river:/SystemC/o_req_mem_write
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compare add -wave sim:/RiverTop/o_req_mem_addr o_river:/SystemC/o_req_mem_addr
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compare add -wave sim:/RiverTop/o_req_mem_strob o_river:/SystemC/o_req_mem_strob
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compare add -wave sim:/RiverTop/o_req_mem_data o_river:/SystemC/o_req_mem_data
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compare add -wave sim:/RiverTop/o_dport_ready o_river:/SystemC/o_dport_ready
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compare add -wave sim:/RiverTop/o_dport_rdata o_river:/SystemC/o_dport_rdata
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compare run
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@note In this script I've used \c vcd2wlf and \c wlf2vcd utilities to form
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compatible with ModelSim VCD-file. Otherwise there're will be errors because
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ModelSim cannot parse std_logic_vector siganls (only std_logic).
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*/
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