URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [docs/] [doxygen/] [06_periph.doxy] - Blame information for rev 5

Details | Compare with Previous | View Log


/**  @page peripheries_page Peripheries
 
  List of implemented modules with AXI4 interface:
 
   @subpage dsu_page
 
   @subpage gpio_page
 
   @subpage gptimers_page
 
   @subpage irqctrl_page
 
   @subpage uart_page
 
   @subpage spiflash_page
 
   @subpage pnp_page
 
*/

Line No.	Rev	Author	Line
1	5	sergeykhbr	`/** @page peripheries_page Peripheries`
2
3			`List of implemented modules with AXI4 interface:`
4
5			`@subpage dsu_page`
6
7			`@subpage gpio_page`
8
9			`@subpage gptimers_page`
10
11			`@subpage irqctrl_page`
12
13			`@subpage uart_page`
14
15			`@subpage spiflash_page`
16
17			`@subpage pnp_page`
18
19			`*/`

Browse

Tools

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [docs/] [doxygen/] [06_periph.doxy] - Blame information for rev 5