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sergeykhbr |
/** @page dsu_page Debug Support Unit (DSU)
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Debug Support Unit (DSU) was developed to interact with "RIVER" CPU
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via its debug port interace. This bus provides access to all internal CPU
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registers and states and may be additionally extended by request.
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Run control functionality like 'run', 'halt', 'step' or 'breakpoints'
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imlemented using proprietary algorithms and intend to simplify integration
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with debugger application.
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Set of general registers and control registers (CSR) are described in
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RISC-V privileged ISA specification and also available for read and write
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access via debug port.
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@note Take into account that CPU can have any number of
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platform specific CSRs that usually not entirely documented.
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@section dsu_regs DSU registers mapping
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DSU acts like a slave AMBA AXI4 device that is directly mapped into
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physical memory. Default address location for our implementation
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is 0x80020000. DSU directly transforms device offset address
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into one of regions of the debug port:
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0x00000..0x08000 (Region 1): CSR registers.
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0x08000..0x10000 (Region 2): General set of registers.
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0x10000..0x18000 (Region 3): Run control and debug support registers.
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0x18000..0x20000 (Region 4): Local DSU region that doesn't access CPU debug port.
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@par Example:
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Bus transaction at address 0x80023C10
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will be redirected to Debug port with CSR index 0x782.
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@subsection dsu_csr CSR Region (32 KB)
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@par User Exception Program Counter (0x00208). ISA offset 0x041.
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|Bits|Type| Reset | Name | Definition
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|:--:|:--:|:-----:|:-------------:|---------------------------------------------|
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| 64 | RO | 64h'0 | uepc | User mode exception program counter. Instruction URET is used to return from traps in User Mode into specified instruction pointer. URET is only provided if user-mode traps are supported.
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@par Machine Status Register (0x01800). ISA offset 0x300.
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|Bits|Type| Reset |Field Name| Bits | Description
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|:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
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| 1 | RW | 1b'0 | SD | 63 | Bit summarizes whether either the FS field or XS field signals the presence of some dirty state that will require saving extended user context to memory
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| 22 | RW | 22h'0 | WPRI | 62:20 | Reserved
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| 5 | RW | 5h'0 | VM (WARL)| 28:24 | Virtual addressing enable
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| 4 | RW | 4h'0 | WPRI | 23:20 | Reserved
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| 1 | RW | 1b'0 | MXR | 19 | Make eXecutable Readable
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| 1 | RW | 1b'0 | PUM | 18 | Protect User Memory bit modifies the privilege with which loads access virtual memory
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| 1 | RW | 1b'0 | MPRV | 17 | Privilege level at which loads and stores execute
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| 2 | RW | 2h'0 | XS | 16:15 | Context switch reducing flags: 0=All Off; 1=None dirty or clean, some on; 2=None dirty, some clean; 3=Some dirty
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| 2 | RW | 2h'0 | FS | 14:13 | Context switch reducing flags: 0=Off; 1=Initial; 2=Clean; 3=Dirty
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| 2 | RW | 2h'0 | MPP | 12:11 | Priviledge mode on MRET
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| 2 | RW | 2h'0 | HPP | 10:9 | Priviledge mode on HRET
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| 1 | RW | 1b'0 | SPP | 8 | Priviledge mode on SRET
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| 1 | RW | 1b'0 | MPIE | 7 | MIE prior to the trap
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| 1 | RW | 1b'0 | HPIE | 6 | HIE prior to the trap
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| 1 | RW | 1b'0 | SPIE | 5 | SIE prior to the trap
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| 1 | RW | 1b'0 | UPIE | 4 | UIE prior to the trap
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| 1 | RW | 1b'0 | MIE | 3 | Machine interrupt enable bit
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| 1 | RW | 1b'0 | HIE | 2 | Hypervisor interrupt enable bit
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| 1 | RW | 1b'0 | SIE | 1 | Super-user interrupt enable bit
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| 1 | RW | 1b'0 | UIE | 0 | User interrupt enable bit
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@par Machine Trap-Vector Base-Address Register (0x01828). ISA offset 0x305.
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|Bits|Type| Reset | Field Name | Definition
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|:--:|:--:|:-----:|:-----------------:|:---------------------------------------------|
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| 64 | RW | 64h'0 | mtvec | Trap-vector Base Address. The mtvec register is an XLEN-bit read/write register that holds the base address of the M-mode trap vector.
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@par Machine Exception Program Counter (0x01A08). ISA offset 0x341.
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|Bits|Type| Reset | Field Name | Definition
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|:--:|:--:|:-----:|:-----------------:|:---------------------------------------------|
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| 64 | RW | 64h'0 | mepc | Machine mode exception program counter. Instruction MRET is used to return from traps in User Mode into specified instruction pointer. On implementations that do not support instruction-set extensions with 16-bit instruction alignment, the two low bits (mepc[1:0]) are always zero.
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@par Machine Cause Register (0x01A10). ISA offset 0x342.
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|Bits|Type| Reset | Field Name |Bits| Definition
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|:--:|:--:|:-----:|:-------------|:--:|:---------------------------------------------|
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| 1 | RW | 1b'0 | Interrupt | 63 | The Interrupt bit is set if the trap was caused by an interrupt.
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| 63 | RW | 63h'0 | Exception Code | 62:0 | Exception code. The Exception Code field contains a code identifying the last exception. Table 3.6 lists the possible machine-level exception codes.
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@par Machine Cause Register (0x01A18). ISA offset 0x343.
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|Bits|Type| Reset | Field Name |Bits| Definition
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|:--:|:--:|:-----:|:-------------|:--:|:---------------------------------------------|
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| 64 | RW | 64h'0 | mbadaddr | 63:0 | Exception address. When a hardware breakpoint is triggered, or an instruction-fetch, load, or store address-misaligned or access exception occurs, mbadaddr is written with the faulting address. mbadaddr is not modified for other exceptions.
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@par Machine ISA Register (0x07880). ISA offset 0xf10.
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|Bits|Type| Reset |Field Name| Bits | Description
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|:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
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| 2 | RO | 2h'2 | Base (WARL)| 63:62 | Integer ISA width: 1=32 bits; 2=64 bits; 3=128 bits.
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| 34 | RO | 64h'0 | WIRI | 61:28 | Reserved.
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| 28 | RO | 28h'141181 | Extension (WARL) | 27:0 | Supported ISA extensions. See priviledge-isa datasheet.
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@par Machine Vendor ID (0x07888). ISA offset 0xf11.
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|Bits|Type| Reset |Field Name| Bits | Description
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|:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
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| 64 | RO | 64h'0 | Vendor | 63:0 | Vendor ID. read-only register encoding the manufacturer of the part. This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented or that this is a non-commercial implementation.
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@par Machine Architecture ID Register (0x07890). ISA offset 0xf12.
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|Bits|Type| Reset |Field Name| Bits | Description
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|:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
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| 64 | RO | 64h'0 | marchid | 63:0 |Architecture ID. Read-only register encoding the base microarchitecture of the hart. This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented. The combination of mvendorid and marchid should uniquely identify the type of hart microarchitecture that is implemented.
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@par Machine implementation ID Register (0x07898). ISA offset 0xf13.
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|Bits|Type| Reset |Field Name| Bits | Description
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|:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
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| 64 | RO | 64h'0 | mimplid | 63:0 | Implementation ID. CSR provides a unique encoding of the version of the processor implementation. This register must be readable in any implementation, but a value of 0 can be returned to indicate that the field is not implemented.
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@par Hart ID Register (0x078A0). ISA offset 0xf14.
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|Bits|Type| Reset |Field Name| Bits | Description
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|:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
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| 64 | RO | 64h'0 | mhartid | 63:0 | Integer ID of hardware thread. Hart IDs mightnot necessarily be numbered contiguously in a multiprocessor system, but at least one hart musthave a hart ID of zero.
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@subsection dsu_iregs General CPU Registers Region (32 KB)
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@par CPU integer registers (0x08000).
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|Offset |Bits|Type| Reset | Name | Definition
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|:------|:--:|:--:|:-----:|:----:|---------------------------------------------|
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|0x08000| 64 | RW | 64h'0 | zero | x0. CPU General Integer Register hardware connected to zero.
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|0x08008| 64 | RW | 64h'0 | ra | x1. Return address.
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|0x08010| 64 | RW | 64h'0 | sp | x2. Stack pointer.
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|0x08018| 64 | RW | 64h'0 | gp | x3. Global pointer.
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|0x08020| 64 | RW | 64h'0 | tp | x4. Thread pointer.
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|0x08028| 64 | RW | 64h'0 | t0 | x5. Temporaries 0.
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|0x08030| 64 | RW | 64h'0 | t1 | x6. Temporaries 1.
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|0x08038| 64 | RW | 64h'0 | t2 | x7. Temporaries 2.
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|0x08040| 64 | RW | 64h'0 | s0/fp| x8. CPU General Integer Register 'Saved register 0/ Frame pointer'.
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|0x08048| 64 | RW | 64h'0 | s1 | x9. Saved register 1.
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|0x08050| 64 | RW | 64h'0 | a0 | x10. Function argument 0. It is also used to save return value.
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|0x08058| 64 | RW | 64h'0 | a1 | x11. Function argument 1.
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|0x08060| 64 | RW | 64h'0 | a2 | x12. Function argument 2.
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|0x08068| 64 | RW | 64h'0 | a3 | x13. Function argument 3.
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|0x08070| 64 | RW | 64h'0 | a4 | x14. Function argument 4.
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|0x08078| 64 | RW | 64h'0 | a5 | x15. Function argument 5.
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|0x08080| 64 | RW | 64h'0 | a6 | x16. Function argument 6.
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|0x08088| 64 | RW | 64h'0 | a7 | x17. Function argument 7.
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|0x08090| 64 | RW | 64h'0 | s2 | x18. Saved register 2.
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|0x08098| 64 | RW | 64h'0 | s3 | x19. Saved register 3.
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|0x080a0| 64 | RW | 64h'0 | s4 | x20. Saved register 4.
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|0x080a8| 64 | RW | 64h'0 | s5 | x21. Saved register 5.
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|0x080b0| 64 | RW | 64h'0 | s6 | x22. Saved register 6.
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|0x080b8| 64 | RW | 64h'0 | s7 | x23. Saved register 7.
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|0x080c0| 64 | RW | 64h'0 | s8 | x24. Saved register 8.
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|0x080c8| 64 | RW | 64h'0 | s9 | x25. Saved register 9.
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|0x080d0| 64 | RW | 64h'0 | s10 | x26. Saved register 10.
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|0x080d8| 64 | RW | 64h'0 | s11 | x27. Saved register 11.
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|0x080e0| 64 | RW | 64h'0 | t3 | x28. Temporaries 3.
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|0x080e8| 64 | RW | 64h'0 | t4 | x29. Temporaries 4.
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|0x080f0| 64 | RW | 64h'0 | t5 | x30. Temporaries 5.
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|0x080f8| 64 | RW | 64h'0 | t6 | x31. Temporaries 6.
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|0x08100| 64 | RO | 64h'0 | pc | Instruction pointer. Cannot be modified because shows the latest executed instruction address
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|0x08108| 64 | RW | 64h'0 | npc | Next Instruction Pointer
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@subsection dsu_control Run Control and Debug support Region (32 KB)
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@par Run control/status registers (0x10000).
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 44 | RW | 61h'0 | Reserved | 63:6 | Reserved.
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| 16 | RO | 16h'0 | core_id | 15:4 | Core ID.
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| 1 | RW | 1b'0 | Reserved | 3 | Reserved.
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| 1 | RO | 1b'0 | breakpoint | 2 | Breakpoint. Status bit is set when CPU was halted due the EBREAK instruction.
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| 1 | WO | 1b'0 | stepping_mode | 1 | Stepping mode. This bit enables stepping mode if the Register 'steps' is non zero.
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| 1 | RW | 1b'0 | halt | 0 | Halt mode. When this bit is set CPU pipeline is in the halted state. CPU can be halted at any time without impact on processing data.
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@par Stepping mode Steps registers (0x10008).
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 64 | RW | 64h'0 | steps | 63:0 | Step counter. Total number of instructions that should execute CPU before halt. CPU is set into stepping using 'stepping mode' bit in Run Control register.
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@par Clock counter registers (0x10010).
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 64 | RW | 64h'0 | clock_cnt | 63:0 | Clock counter. Clock counter is used for hardware computation of CPI rate. Clock counter isn't incrementing in Halt state.
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@par Step counter registers (0x10018).
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 64 | RW | 64h'0 | executed_cnt | 63:0 | Step counter. Total number of executed instructions. Step counter is used for hardware computation of CPI rate.
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@par Breakpoint Control registers (0x10020).
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 63 | RW | 63h'0 | Reserved | 63:1 | Reserved
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| 1 | RW | 1b'0 | trap_on_break | 0 | Trap On Break. Generate exception 'Breakpoint' on EBRAK instruction if this bit is set or just Halt the pipeline otherwise.
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@par Add hardware breakpoint registers (0x10028).
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 64 | RW | 64h'0 | add_break | 63:0 | Add HW breakpoint address. Add specified address into Hardware breakpoint stack. In case of matching Instruction Pointer (pc) and any HW breakpoint there's injected EBREAK instruction on hardware level.
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@par Remove hardware breakpoint registers (0x10030).
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 64 | RW | 64h'0 | rem_break | 63:0 | Remove HW breakpoint address. Remove specified address from Hardware breakpoints stack.
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@par Breakpoint Address Fetch registers (0x10038).
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 64 | RW | 64h'0 | br_address_fetch | 63:0 | Breakpoint fetch address. Specify address that will be ignored by Fetch stage and used Breakpoint Fetch Instruction value instead. This logic is used to avoid re-writing EBREAK into memory.
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@par Breakpoint Instruction Fetch registers (0x10040).
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 64 | RW | 64h'0 | br_instr_fetch | 63:0 | Breakpoint fetch instruction. Specify instruction that should executed instead of fetched from memory in a case of matching Breapoint Address Fetch register and Instruction pointer (pc).
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@subsection dsu_local Local DSU Region (32 KB)
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@par Soft Reset registers (0x18000).
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|Bits|Type| Reset | Field Name | Bits | Description
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234 |
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 63 | RW | 63h'0 | Reserved | 63:1 | Reserved.
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| 1 | RW | 1b'0 | soft_reset | 0 | Soft Reset. Status bit is set when CPU was halted due the EBREAK instruction.
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@par Miss Access counter registers (0x18008).
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239 |
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 64 | RO | 64h'0 | miss_access_cnt | 63:0 | Miss Access counter. This value as an additional debugging informantion provided by AXI Controller. It is possible to enable interrupt generation in Interrupt Controller on miss-access.
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@par Miss Access Address registers (0x18010).
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|Bits|Type| Reset | Field Name | Bits | Description
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|:--:|:--:|:-----:|:----------:|:-----:|:------------------------------------------------------------|
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| 64 | RO | 64h'0 | miss_access_addr | 63:0 | Miss Access address. Address of the latest miss-accessed transaction. This information comes from AXI Controller.
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@par Bus Utilization registers (0x18040 + n*2*sizeof(uint64_t)).
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|Offset |Bits|Type| Reset | Name | Definition
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253 |
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|:------|:--:|:--:|:-----:|:-----:|---------------------------------------------|
|
254 |
|
|
|0x18040| 64 | RO | 64h'0 | w_cnt | Write transactions counter for master 0. Master 0 is the RIVER CPU by default.
|
255 |
|
|
|0x18048| 64 | RO | 64h'0 | r_cnt | Read transactions counter for master 0.
|
256 |
|
|
|0x18050| 64 | RO | 64h'0 | w_cnt | Write transactions counter for master 1. Master 1 is unused in a case of configuration with RIVER CPU.
|
257 |
|
|
|0x18058| 64 | RO | 64h'0 | r_cnt | Read transactions counter for master 1.
|
258 |
|
|
|0x18060| 64 | RO | 64h'0 | w_cnt | Write transactions counter for master 2. Master 2 is the GRETH by default (Ethernet Controller with master interface).
|
259 |
|
|
|0x18068| 64 | RO | 64h'0 | r_cnt | Read transactions counter for master 2.
|
260 |
|
|
|
261 |
|
|
|
262 |
|
|
*/
|