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sergeykhbr |
/** @page spiflash_page SPI Controller
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@section spiflash_overview Overview
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This SPI controller is the specially developed module to support the
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following Flash memory ICs:
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\li Microchip 25AA1024 and 25LC1024.
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\li 1636PP52Y
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Read/write access to the controller's registers directly generate SPI
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signals sequence (nCS, SDO, SCK) to form read/write transaction request.
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AXI4 bus transaction is holded and CPU (or DMA) waits the response from the
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SPI interface all the time while SPI is active.
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The following generic parameters are used to configure the SPI controllers:
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| Name | Default | Description
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|:------|:---------:|:------------
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| xaddr | 0 | Base address. Bus address bits [31:12] allocated for the controller.
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| xmask | 16#fffff# | Address mask. Bus address mask bits used to specify allocated size (default 4 KB, minimum).
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@section spiflash_regs Mapped Registers
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SPI controller module acts like a slave AMBA AXI4 device that is directly mapped
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into physical memory. Default address location for this implementation
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is defined as 0x00200000 with allocated memory size 256 KB.
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The lower 128 KB region is used for the direct access to the external Flash
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memory via SPI interface. The control registers are mapped at offset 0x20000
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(upper 128 KB).
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@par Flash Region 128 KB (0x00000..0x20000).
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Read access to this region directly converted into SPI read request.
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4 and 8-bytes read requests is supported by this SPI controller.
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Write requests to this region doesn't generate any SPI activity. All write data
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is writing ONLY into the local Page Buffer (256 Bytes length). 4 or 8-bytes write
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access is supported. Address bits [31:8] are ignored and must be specified on
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write access into Flash Page Write register.
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@par Scaler register (0x20000).
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|Bits|Type| Reset |Field Name| Bits | Description
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|:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
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| 32 | RW | 0 | scaler | 31:0 | Clock Scaling Rate. RW register is specifies the SPI frequency relative Bus Frequency. Fspi = Fbus / (2*scaler).
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@par Flash STATUS (0x20010).
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|Bits|Type| Field Name | Bits | Description
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|:--:|:--:|:-----------|:-----:|:------------------------------------------------------------|
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| 32 | RW | STATUS | 7:0 | STATUS. Flash STATUS register read via SPI. Read Command ID = 0x05; Write Command ID = 0x01.
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@par Flash ID (0x20018).
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|Bits|Type| Field Name| Bits | Description
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|:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
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| 8 | RO | ID | 7:0 | Manufacturer ID. Read Only value read from Flash: 0x29 is the default value of Microchip. Command ID = 0xAB.
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@par Flash Write Enable (0x20020).
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|Bits|Type| Field Name| Bits | Description
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|:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
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| 32 | WO | WE | 31:0 | Flash Write Enable. Writing to this register generates SPI transasction with command ID = 0x06. Write value is ignored.
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@par Flash Page Write (0x20028).
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|Bits|Type| Field Name| Bits | Description
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|:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
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| 8 | WO | ignored | 7:0 | Ignored.
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| 9 | WO | PAGE_ADDR | 16:8 | Page address. Page Address which is used to store current Page Buffer (256 Bytes) into external Flash. Command ID = 0x02.
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| 15 | WO | ignored | 31:17 | Ignored.
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@par Flash Write Disable (0x20030).
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|Bits|Type| Field Name| Bits | Description
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|:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
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| 32 | WO | WD | 31:0 | Flash Write Disable. Writing to this register generates SPI transasction with command ID = 0x04. Write value is ignored.
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@par Flash Page Erase (0x20038).
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|Bits|Type| Field Name| Bits | Description
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|:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
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| 24 | WO | PAGE_ADDR | 23:0 | Flash Page Erase. Erase external Flash page with specified address. Command ID = 0x42.
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| 8 | WO | ignored | 31:24 | Ignored.
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@par Flash Sectore Erase (0x20040).
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|Bits|Type| Field Name| Bits | Description
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|:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
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| 24 | WO | SECTOR_ADDR | 23:0 | Flash Sector Erase. Erase external Flash sector with specified address. Command ID = 0xDB.
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| 8 | WO | ignored | 31:24 | Ignored.
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@par Flash Chip Erase (0x20048).
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|Bits|Type| Field Name| Bits | Description
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|:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
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| 32 | WO | ignored | 31:0 | Chip Erase. Writing any value to this register generates SPI transasction with command ID = 0xC7. Write value is ignored.
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@par Deep Power-Down mode (0x20050).
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|Bits|Type| Field Name| Bits | Description
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|:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
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| 32 | WO | ignored | 31:0 | Deep Power-Down mode. Writing any value to this register generates SPI transasction with command ID = 0xB9 that sends ICs into Power-Down mode. Write value is ignored.
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*/
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