OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [examples/] [boot/] [src/] [trap.c] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 sergeykhbr
/******************************************************************************
2
 * @file
3
 * @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
4
 * @author    Sergey Khabarov - sergeykhbr@gmail.com
5
 * @brief     General interrupt handler called from assembler.
6
******************************************************************************/
7
 
8
#include <string.h>
9
#include "axi_maps.h"
10
#include "encoding.h"
11
 
12
typedef void (*IRQ_HANDLER)(int idx, void *args);
13
 
14
typedef union csr_mcause_type {
15
    struct bits_type {
16
        uint64_t code   : 63;   // 11 - Machine external interrupt
17
        uint64_t irq    : 1;
18
    } bits;
19
    uint64_t value;
20
} csr_mcause_type;
21
 
22
extern void print_uart(const char *buf, int sz);
23
extern void print_uart_hex(long val);
24
 
25
long handle_trap(long cause, long epc, long long regs[32]) {
26
    /**
27
     * Pending interrupt bit is cleared in the crt.S file by calling:
28
     *      csrc mip, MIP_MSIP
29
     * If we woudn't do it the interrupt handler will be called infinitly
30
     *
31
     * Rise interrupt from the software maybe done sending a self-IPI:
32
     *      csrwi mipi, 0
33
     */
34
    irqctrl_map *p_irqctrl = (irqctrl_map *)ADDR_NASTI_SLAVE_IRQCTRL;
35
    IRQ_HANDLER irq_handler = (IRQ_HANDLER *)p_irqctrl->isr_table;
36
    uint32_t pending;
37
    csr_mcause_type mcause;
38
 
39
    mcause.value = cause;
40
    p_irqctrl->dbg_cause = cause;
41
    p_irqctrl->dbg_epc = epc;
42
 
43
    p_irqctrl->irq_lock = 1;
44
    pending = p_irqctrl->irq_pending;
45
    p_irqctrl->irq_clear = pending;
46
    p_irqctrl->irq_lock = 0;
47
 
48
    if (mcause.bits.irq == 0x1 && mcause.bits.code == 11) {
49
        for (int i = 0; i < CFG_IRQ_TOTAL; i++) {
50
            if (pending & 0x1) {
51
                p_irqctrl->irq_cause_idx = i;
52
                irq_handler(i, NULL);
53
            }
54
            pending >>= 1;
55
        }
56
    } else {
57
       print_uart("mcause:", 7);
58
       print_uart_hex(cause);
59
       print_uart(",mepc:", 6);
60
       print_uart_hex(epc);
61
       print_uart("\r\n", 2);
62
       /// Exception trap
63
       ((gpio_map *)ADDR_NASTI_SLAVE_GPIO)->led = 0xF0;
64
       while (1) {}
65
    }
66
 
67
    return epc;
68
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.