URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [examples/] [bootarm/] [makefiles/] [test.ld] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	sergeykhbr	`OUTPUT_ARCH( "arm" )`
2
3			`/----------------------------------------------------------------------/`
4			`/* Sections */`
5			`/----------------------------------------------------------------------/`
6
7			`SECTIONS`
8			`{`
9
10			`/* text: test code section */`
11			`. = 0x0000;`
12			`.text :`
13			`{`
14			`../linuxbuild/obj/crt.o(.text)`
15			`}`
16
17			`/* data segment */`
18			`.data : { *(.data) }`
19
20
21			`/* bss segment */`
22			`__bss_start__ = .;`
23			`.bss : { *(.bss) }`
24			`__bss_end__ = .;`
25
26			`__exidx_start = .;`
27			`.ARM.exidx : { (.ARM.exidx .gnu.linkonce.armexidx.*) }`
28			`__exidx_end = .;`
29
30			`/* End of uninitalized data segement */`
31			`_end = .;`
32			`}`
33