OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [examples/] [dhrystone21/] [makefiles/] [makefile] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 sergeykhbr
include makeutil.mak
2
 
3
TOP_DIR=../../
4
OBJ_DIR = $(TOP_DIR)dhrystone21/makefiles/obj
5
ELF_DIR = $(TOP_DIR)dhrystone21/makefiles/bin
6
 
7
 
8
#-----------------------------------------------------------------------------
9
.SILENT:
10
  TEA = 2>&1 | tee _$@-comp.err
11
 
12
all: riscv
13
        $(ECHO) "    All done.\n"
14
 
15
riscv:
16
        $(ECHO) "    Dhrystonev 2.1 RISC-V application building started:"
17
        $(MKDIR) ./$(OBJ_DIR)
18
        $(MKDIR) ./$(ELF_DIR)
19
        make -f make_riscv TOP_DIR=$(TOP_DIR) OBJ_DIR=$(OBJ_DIR) ELF_DIR=$(ELF_DIR) $@ $(TEA)
20
 
21
arm:
22
        $(ECHO) "    Dhrystonev 2.1 Cortex-R5 application building started:"
23
        $(MKDIR) ./$(OBJ_DIR)
24
        $(MKDIR) ./$(ELF_DIR)
25
        make -f make_arm TOP_DIR=$(TOP_DIR) OBJ_DIR=$(OBJ_DIR) ELF_DIR=$(ELF_DIR) $@ $(TEA)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.