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[/] [riscv_vhdl/] [trunk/] [examples/] [dhrystone21/] [makefiles/] [test_arm.ld] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	sergeykhbr
2			`OUTPUT_ARCH( "arm" )`
3
4			`/----------------------------------------------------------------------/`
5			`/* Sections */`
6			`/----------------------------------------------------------------------/`
7			`SECTIONS`
8			`{`
9
10			`/* text: test code section */`
11			`. = 0x10000000;`
12			`.text :`
13			`{`
14			`(.text.entrypoint)`
15			`(.text)`
16			`}`
17
18			`/* data segment */`
19			`.data : { *(.data) }`
20
21
22			`/* bss segment */`
23			`__bss_start__ = .;`
24			`.bss : { *(.bss) }`
25			`__bss_end__ = .;`
26
27			`__exidx_start = .;`
28			`.ARM.exidx : { (.ARM.exidx .gnu.linkonce.armexidx.*) }`
29			`__exidx_end = .;`
30
31			`/* End of uninitalized data segement */`
32			`_end = .;`
33			`}`
34