OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [examples/] [dhrystone21/] [src/] [uart.h] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 sergeykhbr
#ifndef __UART_H__
2
#define __UART_H__
3
 
4
#include <stdarg.h>
5
 
6
#ifdef __cplusplus
7
extern "C" {
8
#endif
9
 
10
void uart_init();
11
int printf_uart(const char *_format, ... );
12
 
13
#ifdef __cplusplus
14
}
15
#endif
16
 
17
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.