OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [examples/] [isrdemo/] [makefiles/] [app.ld] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 sergeykhbr
OUTPUT_ARCH( "riscv" )
2
 
3
/*----------------------------------------------------------------------*/
4
/* Sections                                                             */
5
/*----------------------------------------------------------------------*/
6
SECTIONS
7
{
8
 
9
  /* text: test code section */
10
  . = 0x10000000;
11
  .text :
12
  {
13
    ../../isrdemo/makefiles/obj/main.o (.text.startup)
14
    *(.text)
15
  }
16
 
17
  /* data segment */
18
  .data : { *(.data) }
19
 
20
  .sdata : {
21
    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
22
    *(.sdata .sdata.* .gnu.linkonce.s.*)
23
  }
24
 
25
  /* bss segment */
26
  .sbss : {
27
    *(.sbss .sbss.* .gnu.linkonce.sb.*)
28
    *(.scommon)
29
  }
30
  .bss : { *(.bss) }
31
 
32
  /* thread-local data segment */
33
  .tdata :
34
  {
35
    *(.tdata)
36
  }
37
  .tbss :
38
  {
39
    *(.tbss)
40
  }
41
 
42
  /* End of uninitalized data segement */
43
  _end = .;
44
 
45
}
46
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.