URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [.gitignore] - Blame information for rev 5

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*.bak
*.dump
*.err
*.lst
gnsslib/*
!gnsslib/types_gnss
!gnsslib/sync
!gnsslib/rf3b
!gnsslib/gnssengine_stub
patches/
work/tb/*
!work/tb/riscv_soc_tb.vhd
!work/tb/uart_sim.vhd
!work/tb/ethphy_sim.vhd
!work/tb/jtag_sim.vhd
 

Line No.	Rev	Author	Line
1	5	sergeykhbr	`*.bak`
2			`*.dump`
3			`*.err`
4			`*.lst`
5			`gnsslib/*`
6			`!gnsslib/types_gnss`
7			`!gnsslib/sync`
8			`!gnsslib/rf3b`
9			`!gnsslib/gnssengine_stub`
10			`patches/`
11			`work/tb/*`
12			`!work/tb/riscv_soc_tb.vhd`
13			`!work/tb/uart_sim.vhd`
14			`!work/tb/ethphy_sim.vhd`
15			`!work/tb/jtag_sim.vhd`
16

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Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [.gitignore] - Blame information for rev 5