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[/] [riscv_vhdl/] [trunk/] [rtl/] [commonlib/] [types_common.vhd] - Blame information for rev 5

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1 5 sergeykhbr 
-----------------------------------------------------------------------------
2 
--! @file
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--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
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--! @author    Sergey Khabarov - sergeykhbr@gmail.com
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--! @brief     Declaration and implementation of the types_common package.
6 
------------------------------------------------------------------------------
7 
 
8 
--! Standard library
9 
library ieee;
10 
use ieee.std_logic_1164.all;
11 
use ieee.numeric_std.all;
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use std.textio.all;
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--! @brief   Definition of the generic VHDL methods and constants.
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--! @details This package defines common mathematical methods and
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--!          utility methods for the VHDL types conversions.
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package types_common is
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--! @brief Array declaration of the pre-computed log2 values.
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type log2arr is array(0 to 512) of integer;
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22 
--! @brief Array definition of the pre-computed log2 values.
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--! @details These values are used as an argument in bus width
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--!          declaration.
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--!
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--! Example usage:
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--! @code
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--!   component foo_component is
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--!   generic (
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--!     max_clients  : integer := 8
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--!   );
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--!   port (
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--!     foo : inout  std_logic_vector(log2(max_clients)-1 downto 0)
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--!   );
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--!   end component;
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--! @endcode
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constant log2   : log2arr := (
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0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
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  6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
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  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
41 
  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
42 
  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
43 
  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
44 
  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
45 
  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
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  others => 9);
47 
 
48 
constant log2x  : log2arr := (
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0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
50 
  6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
51 
  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
52 
  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
53 
  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
54 
  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
55 
  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
56 
  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
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  others => 9);
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59 
constant zero32 : std_logic_vector(31 downto 0) := X"00000000";
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constant zero64 : std_logic_vector(63 downto 0) := zero32 & zero32;
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62 
 
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function "-" (i : integer; d : std_logic_vector) return std_logic_vector;
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function "-" (d : std_logic_vector; i : integer) return std_logic_vector;
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function "-" (a, b : std_logic_vector) return std_logic_vector;
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function "+" (d : std_logic_vector; i : integer) return std_logic_vector;
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function "+" (a, b : std_logic_vector) return std_logic_vector;
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function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector;
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function "*" (a, b : std_logic_vector) return std_logic_vector;
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71 
function conv_integer(v : std_logic_vector) return integer;
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function conv_integer(v : std_logic) return integer;
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function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector;
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function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector;
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function conv_std_logic(b : boolean) return std_ulogic;
76 
 
77 
end;
78 
 
79 
 
80 
package body types_common is
81 
 
82 
 
83 
function conv_integer(v : std_logic_vector) return integer is
84 
begin
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  if not is_x(v) then return(to_integer(unsigned(v)));
86 
  else return(0); end if;
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end;
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89 
function conv_integer(v : std_logic) return integer is
90 
begin
91 
  if not is_x(v) then
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    if v = '1' then return(1);
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    else return(0); end if;
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  else return(0); end if;
95 
end;
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97 
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is
98 
variable tmp : std_logic_vector(w-1 downto 0);
99 
begin
100 
  tmp := std_logic_vector(to_unsigned(i, w));
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  return(tmp);
102 
end;
103 
 
104 
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector is
105 
variable tmp : std_logic_vector(w-1 downto 0);
106 
begin
107 
  tmp := std_logic_vector(to_signed(i, w));
108 
  return(tmp);
109 
end;
110 
 
111 
function conv_std_logic(b : boolean) return std_ulogic is
112 
begin
113 
  if b then return('1'); else return('0'); end if;
114 
end;
115 
 
116 
function "+" (d : std_logic_vector; i : integer) return std_logic_vector is
117 
variable x : std_logic_vector(d'length-1 downto 0);
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begin
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-- pragma translate_off
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  if not is_x(d) then
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-- pragma translate_on
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    return(std_logic_vector(unsigned(d) + i));
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-- pragma translate_off
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  else x := (others =>'X'); return(x);
125 
  end if;
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-- pragma translate_on
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end;
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129 
function "+" (a, b : std_logic_vector) return std_logic_vector is
130 
variable x : std_logic_vector(a'length-1 downto 0);
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variable y : std_logic_vector(b'length-1 downto 0);
132 
begin
133 
-- pragma translate_off
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  if not is_x(a&b) then
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-- pragma translate_on
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    return(std_logic_vector(unsigned(a) + unsigned(b)));
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-- pragma translate_off
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  else
139 
     x := (others =>'X'); y := (others =>'X');
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     if (x'length > y'length) then return(x); else return(y); end if;
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  end if;
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-- pragma translate_on
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end;
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function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector is
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variable x : std_logic_vector(d'length-1 downto 0);
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variable y : std_logic_vector(0 downto 0);
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begin
149 
  y(0) := i;
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-- pragma translate_off
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  if not is_x(d) then
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-- pragma translate_on
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    return(std_logic_vector(unsigned(d) + unsigned(y)));
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-- pragma translate_off
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  else x := (others =>'X'); return(x);
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  end if;
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-- pragma translate_on
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end;
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160 
 
161 
function "-" (i : integer; d : std_logic_vector) return std_logic_vector is
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variable x : std_logic_vector(d'length-1 downto 0);
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begin
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-- pragma translate_off
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  if not is_x(d) then
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-- pragma translate_on
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    return(std_logic_vector(i - unsigned(d)));
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-- pragma translate_off
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  else x := (others =>'X'); return(x);
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  end if;
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-- pragma translate_on
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end;
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function "-" (d : std_logic_vector; i : integer) return std_logic_vector is
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variable x : std_logic_vector(d'length-1 downto 0);
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begin
177 
-- pragma translate_off
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  if not is_x(d) then
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-- pragma translate_on
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    return(std_logic_vector(unsigned(d) - i));
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-- pragma translate_off
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  else x := (others =>'X'); return(x);
183 
  end if;
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-- pragma translate_on
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end;
186 
 
187 
function "-" (a, b : std_logic_vector) return std_logic_vector is
188 
variable x : std_logic_vector(a'length-1 downto 0);
189 
variable y : std_logic_vector(b'length-1 downto 0);
190 
begin
191 
-- pragma translate_off
192 
  if not is_x(a&b) then
193 
-- pragma translate_on
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    return(std_logic_vector(unsigned(a) - unsigned(b)));
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-- pragma translate_off
196 
  else
197 
     x := (others =>'X'); y := (others =>'X');
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     if (x'length > y'length) then return(x); else return(y); end if;
199 
  end if;
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-- pragma translate_on
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end;
202 
 
203 
function "*" (a, b : std_logic_vector) return std_logic_vector is
204 
variable z : std_logic_vector(a'length+b'length-1 downto 0);
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begin
206 
-- pragma translate_off
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  if not is_x(a&b) then
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-- pragma translate_on
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    return(std_logic_vector(unsigned(a) * unsigned(b)));
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-- pragma translate_off
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  else
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     z := (others =>'X'); return(z);
213 
  end if;
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-- pragma translate_on
215 
end;
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217 
 
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end;
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