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5 |
sergeykhbr |
git submodule foreach git pull origin master
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make CONFIG=GnssConfig verilog
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ModelSim: Global define for behav.srams.v +define+RANDOMIZE=1
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ModelSim: Global define for rocketchip.GnssConfig.v +define+RANDOMIZE_REG_INIT=1
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// VCD stimulus in ModelSim from SystemC.
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// ModelSim uses only 1-bit signals, so convert VCD -> WLF -> VCD.
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vcd2wlf E:/Projects/GitProjects/riscv_vhdl/debugger/win32build/Debug/intdiv.vcd -o e:/indiv.wlf
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wlf2vcd e:/indiv.wlf -o e:/intdiv.vcd
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vsim -t 1ps -vcdstim E:/intdiv.vcd riverlib.intdiv -do "add wave sim:/intdiv/*; run 10000000"
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vsim -view e:/indiv.wlf -- Add wlf-data to wave-viewer.
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add wave o_fetch:/SystemC/*
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// Comparision
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compare start o_mem sim
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compare add -wave sim:/memaccess/o_mem_addr
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compare run
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compare end
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//////////////////////////////
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// SCALA modifications
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rocketchip/Configs.scals
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+class GnssConfig extends Config(new BaseConfig)
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/* @brief: Enable rwx permssions and make cachable < 0x80000000
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*
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* This must enable rwx permissions for all memory regions
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*/
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//Check that build output memory mapping contains Debug regions
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0x0 - 0x1000 Debug rwx
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//Let's fake all memories will be mapped to this region manager
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rocket/TLB.scala
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val prot_r = fastCheck(_.supportsGet) !!! fastCheck need to change
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val prot_w = fastCheck(_.supportsPutFull)
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val prot_x = fastCheck(_.executable)
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-+ val cacheable = ~mpu_physaddr(31)//fastCheck(_.supportsAcquire)
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uncore/tilelink2/parameters.scala
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- def find(address: BigInt) = managers.find(_.address.exists(_.contains(address)))
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+ def find(address: BigInt) = managers.find(_.address.exists(_.contains(BigInt(0x0))))
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// The safe version will check the entire address
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- def findSafe(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
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+ def findSafe(address: UInt) = Vec(managers.map(_.address.map(_.contains(UInt(0x0))).reduce(_ || _)))
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// The fast version assumes the address is valid
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- def findFast(address: UInt) = Vec(managers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
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+ def findFast(address: UInt) = Vec(managers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(UInt(0x0))).reduce(_ || _)))
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////////////////////////////
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// Generated Verilog fixes
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// Use search [0:127] !!;
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module BTB add reset:
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if(reset) begin
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`ifndef SYNTHESIS
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for (initvar=0; initvar<128; initvar=initvar+1) begin
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_T_2578[initvar] <= 2'b00;
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end
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`endif
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end else if(T_2209_T_2234_en & T_2209_T_2234_mask) begin
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_T_2578[T_2209_T_2234_addr] <= T_2209_T_2234_data;
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end
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CSRFile:: reset "reg_mideleg" and "reg_medeleg" b
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if(reset) begin
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reg_mideleg <= 64'd0;
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end else begin
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if(wen) begin
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if(T_6079) begin
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reg_mideleg <= T_7516;
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end
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end
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end
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if(reset) begin
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reg_medeleg <= 64'd0;
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end else begin
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if(wen) begin
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if(T_6081) begin
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reg_medeleg <= T_7517;
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end
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end
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end
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/* @brief how to find registers info
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*
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* Find the following code in module Rocket(..)
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*/
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`ifdef PRINTF_COND
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if (`PRINTF_COND) begin
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`endif
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if (T_8604) begin
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$fwrite(32'h80000002,"C%d: %d [%d] pc=[%h] W[r%d=%h][%d] R[r%d=%h] R[r%d=%h] inst=[%h] DASM(%h)\n",\
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io_hartid, - core
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T_8594, - csr_io_time
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wb_valid,
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wb_reg_pc, - pc
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T_8596, - register write idx r0..r31
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rf_wdata, - new value
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rf_wen, -
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T_8597, - register read1 idx
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T_8599, - read1 value
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T_8600, - register read2 idx
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T_8602, - read2 value
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wb_reg_inst, - inst
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wb_reg_inst);
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end
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`ifdef PRINTF_COND
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---------------------------------------------
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112 |
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HOW TO build toolchain for soft-float?
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---------------------------------------------
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114 |
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cd riscv-tools/riscv-gnu-toolchain
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./configure --prefix=/home/teeshina/riscv/gcc-softloat --disable-float
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116 |
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mkdir /home/teeshina/riscv/gcc-softloat
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export PATH=/home/teeshina/riscv/gcc-softloat/bin:$PATH
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118 |
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make
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