URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [patches/] [run.srcipt] - Blame information for rev 5

Details | Compare with Previous | View Log


git clone https://github.com/ucb-bar/rocket-chip.git
cd rocket-chip
git submodule update --init
cd riscv-tools/
git submodule update --init --recursive riscv-tests
cd rocket-chip/rocket-chip/fsim/
make CONFIG=GnssConfig verilog

Line No.	Rev	Author	Line
1	5	sergeykhbr	`git clone https://github.com/ucb-bar/rocket-chip.git`
2			`cd rocket-chip`
3			`git submodule update --init`
4			`cd riscv-tools/`
5			`git submodule update --init --recursive riscv-tests`
6			`cd rocket-chip/rocket-chip/fsim/`
7			`make CONFIG=GnssConfig verilog`

Browse

Tools

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [patches/] [run.srcipt] - Blame information for rev 5