Subversion Repositories riscv_vhdl

diff --git a/rocket b/rocket

--- a/rocket

+++ b/rocket

@@ -1 +1 @@

-Subproject commit b08f86b4fb9ef44d27ddda1b038e0d1cc15f0b24

+Subproject commit b08f86b4fb9ef44d27ddda1b038e0d1cc15f0b24-dirty

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala

index f47b21a..8ababc6 100644

--- a/src/main/scala/Configs.scala

+++ b/src/main/scala/Configs.scala

@@ -221,6 +221,15 @@ class DefaultConfig extends Config (

 class DefaultVLSIConfig extends DefaultConfig

 class DefaultCPPConfig extends DefaultConfig

+class WithoutFPU extends Config(

+  (pname,site,here) => pname match {

+      case UseFPU => false

+      case UseBackupMemoryPort => false

+      case MIFDataBits => 128

+  }

+)

+class GnssConfigNoFPU extends Config(new WithoutFPU ++ new DefaultConfig)

+

 class With2Cores extends Config(knobValues = { case "NTILES" => 2 })

 class With4Cores extends Config(knobValues = { case "NTILES" => 4 })

 class With8Cores extends Config(knobValues = { case "NTILES" => 8 })

diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala

index 1f053ec..5050281 100644

--- a/src/main/scala/RocketChip.scala

+++ b/src/main/scala/RocketChip.scala

@@ -69,6 +69,7 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)

 class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {

   val mem = Vec(new NastiIO, nMemChannels)

+  val mmio = new NastiIO

 }

 object TopUtils {

@@ -118,8 +119,9 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {

   }

   // tie off the mmio port

-  val errslave = Module(new NastiErrorSlave)

-  errslave.io <> uncore.io.mmio

+  //val errslave = Module(new NastiErrorSlave)

+  //errslave.io <> uncore.io.mmio

+  io.mmio <> uncore.io.mmio

 }

 /** Wrapper around everything that isn't a Tile.