OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [prj/] [kc705/] [riscv_soc_kc705.xdc] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 sergeykhbr 
 
2 
####################################################################################
3 
# Generated by PlanAhead 14.7 built on 'Fri Sep 27 19:29:51 MDT 2013' by 'xbuild'
4 
####################################################################################
5 
 
6 
 
7 
create_clock -name i_sclk_p -period 5.000 [get_ports i_sclk_p]
8 
set_property PACKAGE_PIN AD12 [get_ports i_sclk_p]
9 
set_property IOSTANDARD LVDS [get_ports i_sclk_p]
10 
set_property PACKAGE_PIN AD11 [get_ports i_sclk_n]
11 
set_property IOSTANDARD LVDS [get_ports i_sclk_n]
12 
 
13 
# button "Center"
14 
set_property PACKAGE_PIN G12 [get_ports i_rst]
15 
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_rst]
16 
set_property IOSTANDARD LVCMOS25 [get_ports i_rst]
17 
 
18 
# DIP switch: SW1.1
19 
set_property PACKAGE_PIN Y29 [get_ports {i_dip[0]}]
20 
set_property IOSTANDARD LVCMOS25 [get_ports {i_dip[0]}]
21 
set_property PACKAGE_PIN W29 [get_ports {i_dip[1]}]
22 
set_property IOSTANDARD LVCMOS25 [get_ports {i_dip[1]}]
23 
set_property PACKAGE_PIN AA28 [get_ports {i_dip[2]}]
24 
set_property IOSTANDARD LVCMOS25 [get_ports {i_dip[2]}]
25 
set_property PACKAGE_PIN Y28 [get_ports {i_dip[3]}]
26 
set_property IOSTANDARD LVCMOS25 [get_ports {i_dip[3]}]
27 
 
28 
#UART interface
29 
set_property PACKAGE_PIN K23 [get_ports i_uart1_ctsn]
30 
set_property IOSTANDARD LVCMOS25 [get_ports i_uart1_ctsn]
31 
set_property PACKAGE_PIN M19 [get_ports i_uart1_rd]
32 
set_property IOSTANDARD LVCMOS25 [get_ports i_uart1_rd]
33 
set_property PACKAGE_PIN L27 [get_ports o_uart1_rtsn]
34 
set_property IOSTANDARD LVCMOS25 [get_ports o_uart1_rtsn]
35 
set_property PACKAGE_PIN K24 [get_ports o_uart1_td]
36 
set_property IOSTANDARD LVCMOS25 [get_ports o_uart1_td]
37 
 
38 
# UART2 interface (debug port)
39 
# HPC H20
40 
set_property PACKAGE_PIN B24 [get_ports i_uart2_ctsn]
41 
set_property IOSTANDARD LVCMOS25 [get_ports i_uart2_ctsn]
42 
set_property PULLDOWN TRUE [get_ports i_uart2_ctsn]
43 
# HPC H19
44 
set_property PACKAGE_PIN C24 [get_ports i_uart2_rd]
45 
set_property IOSTANDARD LVCMOS25 [get_ports i_uart2_rd]
46 
# HPC G19
47 
set_property PACKAGE_PIN A27 [get_ports o_uart2_rtsn]
48 
set_property IOSTANDARD LVCMOS25 [get_ports o_uart2_rtsn]
49 
# HPC G18
50 
set_property PACKAGE_PIN B27 [get_ports o_uart2_td]
51 
set_property IOSTANDARD LVCMOS25 [get_ports o_uart2_td]
52 
 
53 
#/ User's LEDs:
54 
set_property PACKAGE_PIN AB8 [get_ports {o_led[0]}]
55 
set_property IOSTANDARD LVCMOS15 [get_ports {o_led[0]}]
56 
set_property PACKAGE_PIN AA8 [get_ports {o_led[1]}]
57 
set_property IOSTANDARD LVCMOS15 [get_ports {o_led[1]}]
58 
set_property PACKAGE_PIN AC9 [get_ports {o_led[2]}]
59 
set_property IOSTANDARD LVCMOS15 [get_ports {o_led[2]}]
60 
set_property PACKAGE_PIN AB9 [get_ports {o_led[3]}]
61 
set_property IOSTANDARD LVCMOS15 [get_ports {o_led[3]}]
62 
set_property PACKAGE_PIN AE26 [get_ports {o_led[4]}]
63 
set_property IOSTANDARD LVCMOS25 [get_ports {o_led[4]}]
64 
set_property PACKAGE_PIN G19 [get_ports {o_led[5]}]
65 
set_property IOSTANDARD LVCMOS25 [get_ports {o_led[5]}]
66 
set_property PACKAGE_PIN E18 [get_ports {o_led[6]}]
67 
set_property IOSTANDARD LVCMOS25 [get_ports {o_led[6]}]
68 
set_property PACKAGE_PIN F16 [get_ports {o_led[7]}]
69 
set_property IOSTANDARD LVCMOS25 [get_ports {o_led[7]}]
70 
 
71 
# Ethernet signals
72 
set_property PACKAGE_PIN G8 [get_ports i_gmiiclk_p]
73 
set_property PACKAGE_PIN G7 [get_ports i_gmiiclk_n]
74 
 
75 
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_pins igbebuf0/xk7.x1/x1/O]]
76 
 
77 
set_property PACKAGE_PIN J21 [get_ports io_emdio]
78 
set_property IOSTANDARD LVCMOS25 [get_ports io_emdio]
79 
set_property PACKAGE_PIN R23 [get_ports o_emdc]
80 
set_property IOSTANDARD LVCMOS25 [get_ports o_emdc]
81 
set_property PACKAGE_PIN N30 [get_ports i_emdint]
82 
set_property IOSTANDARD LVCMOS25 [get_ports i_emdint]
83 
set_property PACKAGE_PIN L20 [get_ports o_erstn]
84 
set_property IOSTANDARD LVCMOS25 [get_ports o_erstn]
85 
set_property PACKAGE_PIN R30 [get_ports i_erx_crs]
86 
set_property IOSTANDARD LVCMOS25 [get_ports i_erx_crs]
87 
set_property PACKAGE_PIN W19 [get_ports i_erx_col]
88 
set_property IOSTANDARD LVCMOS25 [get_ports i_erx_col]
89 
set_property PACKAGE_PIN U27 [get_ports i_erx_clk]
90 
set_property IOSTANDARD LVCMOS25 [get_ports i_erx_clk]
91 
set_property PACKAGE_PIN V26 [get_ports i_erx_er]
92 
set_property IOSTANDARD LVCMOS25 [get_ports i_erx_er]
93 
set_property PACKAGE_PIN R28 [get_ports i_erx_dv]
94 
set_property IOSTANDARD LVCMOS25 [get_ports i_erx_dv]
95 
set_property PACKAGE_PIN U30 [get_ports {i_erxd[0]}]
96 
set_property IOSTANDARD LVCMOS25 [get_ports {i_erxd[0]}]
97 
set_property PACKAGE_PIN U25 [get_ports {i_erxd[1]}]
98 
set_property IOSTANDARD LVCMOS25 [get_ports {i_erxd[1]}]
99 
set_property PACKAGE_PIN T25 [get_ports {i_erxd[2]}]
100 
set_property IOSTANDARD LVCMOS25 [get_ports {i_erxd[2]}]
101 
set_property PACKAGE_PIN U28 [get_ports {i_erxd[3]}]
102 
set_property IOSTANDARD LVCMOS25 [get_ports {i_erxd[3]}]
103 
set_property PACKAGE_PIN K30 [get_ports o_egtx_clk]
104 
set_property IOSTANDARD LVCMOS25 [get_ports o_egtx_clk]
105 
set_property PACKAGE_PIN M28 [get_ports i_etx_clk]
106 
set_property IOSTANDARD LVCMOS25 [get_ports i_etx_clk]
107 
set_property PACKAGE_PIN N29 [get_ports o_etx_er]
108 
set_property IOSTANDARD LVCMOS25 [get_ports o_etx_er]
109 
set_property PACKAGE_PIN M27 [get_ports o_etx_en]
110 
set_property IOSTANDARD LVCMOS25 [get_ports o_etx_en]
111 
set_property PACKAGE_PIN N27 [get_ports {o_etxd[0]}]
112 
set_property IOSTANDARD LVCMOS25 [get_ports {o_etxd[0]}]
113 
set_property PACKAGE_PIN N25 [get_ports {o_etxd[1]}]
114 
set_property IOSTANDARD LVCMOS25 [get_ports {o_etxd[1]}]
115 
set_property PACKAGE_PIN M29 [get_ports {o_etxd[2]}]
116 
set_property IOSTANDARD LVCMOS25 [get_ports {o_etxd[2]}]
117 
set_property PACKAGE_PIN L28 [get_ports {o_etxd[3]}]
118 
set_property IOSTANDARD LVCMOS25 [get_ports {o_etxd[3]}]
119 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.