URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [prj/] [ml605/] [_postsim.prj] - Blame information for rev 5

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vhdl commonlib "..\..\commonlib\types_common.vhd"
vhdl commonlib "..\..\commonlib\types_util.vhd"
vhdl techmap "..\..\techmap\gencomp\gencomp.vhd"
vhdl ambalib "..\..\ambalib\types_amba4.vhd"
vhdl rocketlib "..\..\rocketlib\eth\greth_pkg.vhd"
vhdl rocketlib "..\..\rocketlib\types_rocket.vhd"
vhdl work "netgen\synthesis\rocket_soc_synthesis.vhd"
vhdl work "..\..\work\tb\rocket_soc_tb.vhd"

Line No.	Rev	Author	Line
1	5	sergeykhbr	`vhdl commonlib "..\..\commonlib\types_common.vhd"`
2			`vhdl commonlib "..\..\commonlib\types_util.vhd"`
3			`vhdl techmap "..\..\techmap\gencomp\gencomp.vhd"`
4			`vhdl ambalib "..\..\ambalib\types_amba4.vhd"`
5			`vhdl rocketlib "..\..\rocketlib\eth\greth_pkg.vhd"`
6			`vhdl rocketlib "..\..\rocketlib\types_rocket.vhd"`
7			`vhdl work "netgen\synthesis\rocket_soc_synthesis.vhd"`
8			`vhdl work "..\..\work\tb\rocket_soc_tb.vhd"`

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Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [prj/] [ml605/] [_postsim.prj] - Blame information for rev 5