URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [prj/] [ml605/] [_postsim_run.bat] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	sergeykhbr	`fuse -intstyle ise -incremental -lib unisim -lib unimacro -lib xilinxcorelib -lib secureip -o -x_synthesis.exe -prj _postsim.prj work.rocket_soc_tb`
2			`--x_synthesis.exe -gui`