OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [prj/] [ml605/] [riscv_soc_v6.ucf] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 sergeykhbr
###############################################################################
2
# Define Device, Package And Speed Grade
3
###############################################################################
4
CONFIG PART = XC6VLX240T-FF1156-1;
5
 
6
NET "i_sclk_p" TNM_NET = TNM_SysClk;
7
TIMESPEC "TS_SysClk" = PERIOD "TNM_SysClk" 5 ns ;
8
NET  "i_sclk_p"   LOC = "J9";
9
NET  "i_sclk_p"   IOSTANDARD = LVDS_25;
10
NET  "i_sclk_n"   LOC = "H9";
11
NET  "i_sclk_n"   IOSTANDARD = LVDS_25;
12
 
13
# button "Center"
14
NET "i_rst" LOC = G26;
15
NET "i_rst" CLOCK_DEDICATED_ROUTE = "FALSE";
16
# jumpers
17
 
18
 
19
# UART1 interface
20
NET "i_uart1_ctsn" LOC = T23 | PULLDOWN;
21
NET "i_uart1_rd"   LOC = J24;
22
NET "o_uart1_rtsn" LOC = T24;
23
NET "o_uart1_td"   LOC = J25;
24
 
25
# UART2 interface (debug port).
26
# Assign to HPC:
27
#NET "i_uart2_ctsn" LOC = AL23 | PULLDOWN; # HPC H20
28
#NET "i_uart2_rd"   LOC = AM23; # HPC H19
29
#NET "o_uart2_rtsn" LOC = AN23; # HPC G19
30
#NET "o_uart2_td"   LOC = AP22; # HPC G18
31
# Assign to LPC:
32
NET "i_uart2_ctsn" LOC = C33 | PULLDOWN; # LPC C18
33
NET "i_uart2_rd"   LOC = B34; # LPC C19
34
NET "o_uart2_rtsn" LOC = F30; # LPC C14
35
NET "o_uart2_td"   LOC = G30; # LPC C15
36
 
37
#JTAG
38
NET "i_jtag_tck" CLOCK_DEDICATED_ROUTE = "FALSE";
39
 
40
NET "o_jtag_vref" LOC = C34;
41
NET "i_jtag_ntrst" LOC = D34;
42
NET "i_jtag_tdi" LOC = L26;
43
NET "i_jtag_tms" LOC = L25;
44
NET "i_jtag_tck" LOC = H34;
45
NET "o_jtag_tdo" LOC = K33;
46
 
47
 
48
# GPIO
49
NET "i_dip[0]"  LOC = D22 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;   # DIP-0.
50
NET "i_dip[1]"  LOC = C22 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;   # DIP-1
51
NET "i_dip[2]"  LOC = L21 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;   # DIP-2
52
NET "i_dip[3]"  LOC = L20 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;   # DIP-3
53
#NET "i_dip[4]"  LOC = C18;   # DIP-4
54
#NET "i_dip[5]"  LOC = B18;   # DIP-5
55
#NET "i_dip[6]"  LOC = K22;   # DIP-6
56
#NET "i_dip[7]"  LOC = K21;   # DIP-7
57
 
58
 
59
# User's LEDs:
60
NET "o_led[0]" LOC = AC22;
61
NET "o_led[1]" LOC = AC24;
62
NET "o_led[2]" LOC = AE22;
63
NET "o_led[3]" LOC = AE23;
64
NET "o_led[4]" LOC = AB23;
65
NET "o_led[5]" LOC = AG23;
66
NET "o_led[6]" LOC = AE24;
67
NET "o_led[7]" LOC = AD24;
68
 
69
# Ethernet signals
70
NET "i_gmiiclk_p"             LOC = "H6";
71
NET "i_gmiiclk_n"             LOC = "H5";
72
NET "o_egtx_clk"              LOC = "AH12";   ## 14  on U80
73
NET "i_etx_clk"               LOC = "AD12";   ## 10  on U80
74
NET "i_erx_clk"               LOC = "AP11";   ## 7   on U80
75
NET "i_erxd(0)"               LOC = "AN13";   ## 3   on U80
76
NET "i_erxd(1)"               LOC = "AF14";   ## 128 on U80
77
NET "i_erxd(2)"               LOC = "AE14";   ## 126 on U80
78
NET "i_erxd(3)"               LOC = "AN12";   ## 125 on U80
79
NET "i_erx_dv"                LOC = "AM13";   ## 4   on U80
80
NET "i_erx_er"                LOC = "AG12";   ## 9   on U80
81
NET "i_erx_col"               LOC = "AK13";   ## 114 on U80
82
NET "i_erx_crs"               LOC = "AL13";   ## 115 on U80
83
NET "i_emdint"                LOC = "AH14";   ## 32  on U80
84
NET "o_etxd(0)"               LOC = "AM11";   ## 18  on U80
85
NET "o_etxd(1)"               LOC = "AL11";   ## 19  on U80
86
NET "o_etxd(2)"               LOC = "AG10";   ## 20  on U80
87
NET "o_etxd(3)"               LOC = "AG11";   ## 24  on U80
88
NET "o_etx_en"                LOC = "AJ10";   ## 16  on U80
89
NET "o_etx_er"                LOC = "AH10";   ## 13  on U80
90
NET "o_emdc"                  LOC = "AP14";   ## 35  on U80
91
NET "io_emdio"                LOC = "AN14";   ## 33  on U80
92
NET "o_erstn"                 LOC = "AH13";   ## 36  on U80
93
 
94
NET "i_gmiiclk_p"            TNM_NET = "clk_gtx";
95
TIMESPEC "TS_gtx_clk"      = PERIOD "clk_gtx" 8000 ps HIGH 50 %;
96
 
97
NET "i_erx_clk"              TNM_NET  = "clk_rx";
98
TIMESPEC "TS_rx_clk"       = PERIOD "clk_rx" 40000 ps HIGH 50 %;
99
 
100
NET "i_etx_clk"              TNM_NET  = "clk_tx_mac";
101
TIMESPEC "TS_tx_clk_mii"   = PERIOD "clk_tx_mac" 40000 ps HIGH 50 %;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.