URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [prj/] [modelsim/] [.gitignore] - Blame information for rev 5

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*.wlf
*.mti
*.do
ambalib/*
!ambalib/_info
commonlib/*
!commonlib/_info
gnsslib/*
!gnsslib/_info
rocketlib/*
!rocketlib/_info
riverlib/*
!riverlib/_info
techmap/*
!techmap/_info
ethlib/*
!ethlib/_info
misclib/*
!misclib/_info
work/*
!work/_info

Line No.	Rev	Author	Line
1	5	sergeykhbr	`*.wlf`
2			`*.mti`
3			`*.do`
4			`ambalib/*`
5			`!ambalib/_info`
6			`commonlib/*`
7			`!commonlib/_info`
8			`gnsslib/*`
9			`!gnsslib/_info`
10			`rocketlib/*`
11			`!rocketlib/_info`
12			`riverlib/*`
13			`!riverlib/_info`
14			`techmap/*`
15			`!techmap/_info`
16			`ethlib/*`
17			`!ethlib/_info`
18			`misclib/*`
19			`!misclib/_info`
20			`work/*`
21			`!work/_info`

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Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [prj/] [modelsim/] [.gitignore] - Blame information for rev 5