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sergeykhbr |
-----------------------------------------------------------------------------
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--! @file
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--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
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--! @author Sergey Khabarov - sergeykhbr@gmail.com
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--! @brief Debug Support Unit (DSU) with AXI4 interface.
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--! @details DSU provides access to the internal CPU registers via
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--! 'Debug port' bus interface available only on <b>RIVER</b> CPU.
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--! It is also implements a set of registers collecting bus
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--! utilization statistic and additional debug information.
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-----------------------------------------------------------------------------
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--! VHDL base library.
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library ieee;
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--! VHDL base types import
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use ieee.std_logic_1164.all;
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--! VHDL base numeric import
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use ieee.numeric_std.all;
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--! SoC common functionality library.
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library commonlib;
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--! SoC common types import
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use commonlib.types_common.all;
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--! AMBA system bus specific library.
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library ambalib;
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--! AXI4 configuration constants.
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use ambalib.types_amba4.all;
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--! RIVER CPU specific library.
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library riverlib;
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--! RIVER CPU configuration constants.
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use riverlib.river_cfg.all;
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--! River top level with AMBA interface module declaration
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use riverlib.types_river.all;
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entity axi_dsu is
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generic (
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xaddr : integer := 0;
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xmask : integer := 16#fffff#
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);
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port
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(
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clk : in std_logic;
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nrst : in std_logic;
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o_cfg : out nasti_slave_config_type;
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i_axi : in nasti_slave_in_type;
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o_axi : out nasti_slave_out_type;
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o_dporti : out dport_in_type;
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i_dporto : in dport_out_type;
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--! reset CPU and interrupt controller
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o_soft_rst : out std_logic;
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-- Platfrom run-time statistic
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i_miss_irq : in std_logic;
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i_miss_addr : in std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
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i_bus_util_w : in std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0);
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i_bus_util_r : in std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0)
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);
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end;
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architecture arch_axi_dsu of axi_dsu is
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constant xconfig : nasti_slave_config_type := (
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descrtype => PNP_CFG_TYPE_SLAVE,
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descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
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irq_idx => 0,
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xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
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xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
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vid => VENDOR_GNSSSENSOR,
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did => GNSSSENSOR_DSU
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);
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type state_type is (reading, writting, dport_response, ready);
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type mst_utilization_type is array (0 to CFG_NASTI_MASTER_TOTAL-1)
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of std_logic_vector(63 downto 0);
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type mst_utilization_map_type is array (0 to 2*CFG_NASTI_MASTER_TOTAL-1)
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of std_logic_vector(63 downto 0);
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type registers is record
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bank_axi : nasti_slave_bank_type;
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--! Message multiplexer to form 32->64 request message
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state : state_type;
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waddr : std_logic_vector(13 downto 0);
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wdata : std_logic_vector(63 downto 0);
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rdata : std_logic_vector(63 downto 0);
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soft_rst : std_logic;
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-- Platform statistic:
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clk_cnt : std_logic_vector(63 downto 0);
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miss_access_cnt : std_logic_vector(63 downto 0);
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miss_access_addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
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util_w_cnt : mst_utilization_type;
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util_r_cnt : mst_utilization_type;
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end record;
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signal r, rin: registers;
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begin
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comblogic : process(nrst, i_axi, i_dporto, i_miss_irq, i_miss_addr,
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i_bus_util_w, i_bus_util_r, r)
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variable v : registers;
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variable mux_rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
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variable vdporti : dport_in_type;
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variable iraddr : integer;
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variable wb_bus_util_map : mst_utilization_map_type;
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begin
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v := r;
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v.rdata := (others => '0');
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vdporti.valid := '0';
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vdporti.write := '0';
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vdporti.region := (others => '0');
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vdporti.addr := (others => '0');
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vdporti.wdata := (others => '0');
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-- Update statistic:
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v.clk_cnt := r.clk_cnt + 1;
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if i_miss_irq = '1' then
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v.miss_access_addr := i_miss_addr;
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v.miss_access_cnt := r.miss_access_cnt + 1;
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end if;
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for n in 0 to CFG_NASTI_MASTER_TOTAL-1 loop
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if i_bus_util_w(n) = '1' then
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v.util_w_cnt(n) := r.util_w_cnt(n) + 1;
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end if;
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if i_bus_util_r(n) = '1' then
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v.util_r_cnt(n) := r.util_r_cnt(n) + 1;
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end if;
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end loop;
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for n in 0 to CFG_NASTI_MASTER_TOTAL-1 loop
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wb_bus_util_map(2*n) := r.util_w_cnt(n);
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wb_bus_util_map(2*n+1) := r.util_r_cnt(n);
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end loop;
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procedureAxi4(i_axi, xconfig, r.bank_axi, v.bank_axi);
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--! redefine value 'always ready' inserting waiting states.
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v.bank_axi.rwaitready := '0';
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if r.bank_axi.wstate = wtrans then
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-- 32-bits burst transaction
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v.waddr := r.bank_axi.waddr(0)(16 downto 3);
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if r.bank_axi.wburst = NASTI_BURST_INCR and r.bank_axi.wsize = 4 then
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if r.bank_axi.waddr(0)(2) = '1' then
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v.state := writting;
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v.wdata(63 downto 32) := i_axi.w_data(31 downto 0);
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else
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v.wdata(31 downto 0) := i_axi.w_data(31 downto 0);
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end if;
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else
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-- Write data on next clock.
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if i_axi.w_strb /= X"00" then
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v.wdata := i_axi.w_data;
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end if;
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v.state := writting;
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end if;
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end if;
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case r.state is
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when reading =>
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if r.bank_axi.rstate = rtrans then
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if r.bank_axi.raddr(0)(16 downto 15) = "11" then
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--! local region
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v.bank_axi.rwaitready := '1';
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iraddr := conv_integer(r.bank_axi.raddr(0)(14 downto 3));
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case iraddr is
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when 0 =>
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v.rdata(0) := r.soft_rst;
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when 1 =>
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v.rdata := r.miss_access_cnt;
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when 2 =>
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v.rdata(CFG_NASTI_ADDR_BITS-1 downto 0) := r.miss_access_addr;
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when others =>
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if (iraddr >= 8) and (iraddr < (8 + 2*CFG_NASTI_MASTER_TOTAL)) then
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v.rdata := wb_bus_util_map(iraddr - 8);
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end if;
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end case;
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v.state := ready;
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else
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--! debug port regions: 0 to 2
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vdporti.valid := '1';
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vdporti.write := '0';
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vdporti.region := r.bank_axi.raddr(0)(16 downto 15);
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vdporti.addr := r.bank_axi.raddr(0)(14 downto 3);
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vdporti.wdata := (others => '0');
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v.state := dport_response;
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end if;
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end if;
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when writting =>
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v.state := reading;
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if r.waddr(13 downto 12) = "11" then
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--! local region
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case conv_integer(r.waddr(11 downto 0)) is
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when 0 =>
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v.soft_rst := r.wdata(0);
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when others =>
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end case;
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else
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--! debug port regions: 0 to 2
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vdporti.valid := '1';
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vdporti.write := '1';
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vdporti.region := r.waddr(13 downto 12);
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vdporti.addr := r.waddr(11 downto 0);
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vdporti.wdata := r.wdata;
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end if;
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when dport_response =>
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v.state := ready;
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v.bank_axi.rwaitready := '1';
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v.rdata := i_dporto.rdata;
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when ready =>
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v.state := reading;
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when others =>
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end case;
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if r.bank_axi.raddr(0)(2) = '0' then
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mux_rdata(31 downto 0) := r.rdata(31 downto 0);
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else
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-- 32-bits aligned access (can be generated by MAC)
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mux_rdata(31 downto 0) := r.rdata(63 downto 32);
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end if;
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mux_rdata(63 downto 32) := r.rdata(63 downto 32);
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o_axi <= functionAxi4Output(r.bank_axi, mux_rdata);
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if nrst = '0' then
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v.bank_axi := NASTI_SLAVE_BANK_RESET;
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v.state := reading;
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v.waddr := (others => '0');
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v.wdata := (others => '0');
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v.rdata := (others => '0');
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v.soft_rst := '0';
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v.clk_cnt := (others => '0');
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v.miss_access_cnt := (others => '0');
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v.miss_access_addr := (others => '0');
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v.util_w_cnt := (others => (others => '0'));
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v.util_r_cnt := (others => (others => '0'));
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end if;
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rin <= v;
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o_dporti <= vdporti;
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end process;
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o_cfg <= xconfig;
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o_soft_rst <= r.soft_rst;
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-- registers:
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regs : process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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end;
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