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[/] [riscv_vhdl/] [trunk/] [rtl/] [rocketlib/] [behav_srams.v] - Blame information for rev 5

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Line No. Rev Author Line
1 5 sergeykhbr 
 
2 
module _T_146_ext(
3 
  input W0_clk,
4 
  input [5:0] W0_addr,
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  input W0_en,
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  input [87:0] W0_data,
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  input [3:0] W0_mask,
8 
  input R0_clk,
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  input [5:0] R0_addr,
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  input R0_en,
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  output [87:0] R0_data
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);
13 
 
14 
  reg [5:0] reg_R0_addr;
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  reg [87:0] ram [63:0];
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  `ifdef RANDOMIZE
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    integer initvar;
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    initial begin
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      #0.002 begin end
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      for (initvar = 0; initvar < 64; initvar = initvar+1)
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        ram[initvar] = {3 {$random}};
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      reg_R0_addr = {1 {$random}};
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    end
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  `endif
25 
  integer i;
26 
  always @(posedge R0_clk)
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    if (R0_en) reg_R0_addr <= R0_addr;
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  always @(posedge W0_clk)
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    if (W0_en) begin
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      if (W0_mask[0]) ram[W0_addr][21:0] <= W0_data[21:0];
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      if (W0_mask[1]) ram[W0_addr][43:22] <= W0_data[43:22];
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      if (W0_mask[2]) ram[W0_addr][65:44] <= W0_data[65:44];
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      if (W0_mask[3]) ram[W0_addr][87:66] <= W0_data[87:66];
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    end
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  assign R0_data = ram[reg_R0_addr];
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37 
endmodule
38 
 
39 
module _T_80_ext(
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  input W0_clk,
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  input [8:0] W0_addr,
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  input W0_en,
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  input [63:0] W0_data,
44 
  input [0:0] W0_mask,
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  input R0_clk,
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  input [8:0] R0_addr,
47 
  input R0_en,
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  output [63:0] R0_data
49 
);
50 
 
51 
  reg [8:0] reg_R0_addr;
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  reg [63:0] ram [511:0];
53 
  `ifdef RANDOMIZE
54 
    integer initvar;
55 
    initial begin
56 
      #0.002 begin end
57 
      for (initvar = 0; initvar < 512; initvar = initvar+1)
58 
        ram[initvar] = {2 {$random}};
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      reg_R0_addr = {1 {$random}};
60 
    end
61 
  `endif
62 
  integer i;
63 
  always @(posedge R0_clk)
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    if (R0_en) reg_R0_addr <= R0_addr;
65 
  always @(posedge W0_clk)
66 
    if (W0_en) begin
67 
      if (W0_mask[0]) ram[W0_addr][63:0] <= W0_data[63:0];
68 
    end
69 
  assign R0_data = ram[reg_R0_addr];
70 
 
71 
endmodule
72 
 
73 
module tag_array_ext(
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  input RW0_clk,
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  input [5:0] RW0_addr,
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  input RW0_en,
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  input RW0_wmode,
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  input [3:0] RW0_wmask,
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  input [79:0] RW0_wdata,
80 
  output [79:0] RW0_rdata
81 
);
82 
 
83 
  reg [5:0] reg_RW0_addr;
84 
  reg [79:0] ram [63:0];
85 
  `ifdef RANDOMIZE
86 
    integer initvar;
87 
    initial begin
88 
      #0.002 begin end
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      for (initvar = 0; initvar < 64; initvar = initvar+1)
90 
        ram[initvar] = {3 {$random}};
91 
      reg_RW0_addr = {1 {$random}};
92 
    end
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  `endif
94 
  integer i;
95 
  always @(posedge RW0_clk)
96 
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
97 
  always @(posedge RW0_clk)
98 
    if (RW0_en && RW0_wmode) begin
99 
      if (RW0_wmask[0]) ram[RW0_addr][19:0] <= RW0_wdata[19:0];
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      if (RW0_wmask[1]) ram[RW0_addr][39:20] <= RW0_wdata[39:20];
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      if (RW0_wmask[2]) ram[RW0_addr][59:40] <= RW0_wdata[59:40];
102 
      if (RW0_wmask[3]) ram[RW0_addr][79:60] <= RW0_wdata[79:60];
103 
    end
104 
  assign RW0_rdata = ram[reg_RW0_addr];
105 
 
106 
endmodule
107 
 
108 
module _T_850_ext(
109 
  input RW0_clk,
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  input [8:0] RW0_addr,
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  input RW0_en,
112 
  input RW0_wmode,
113 
  input [63:0] RW0_wdata,
114 
  output [63:0] RW0_rdata
115 
);
116 
 
117 
  reg [8:0] reg_RW0_addr;
118 
  reg [63:0] ram [511:0];
119 
  `ifdef RANDOMIZE
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    integer initvar;
121 
    initial begin
122 
      #0.002 begin end
123 
      for (initvar = 0; initvar < 512; initvar = initvar+1)
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        ram[initvar] = {2 {$random}};
125 
      reg_RW0_addr = {1 {$random}};
126 
    end
127 
  `endif
128 
  integer i;
129 
  always @(posedge RW0_clk)
130 
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
131 
  always @(posedge RW0_clk)
132 
    if (RW0_en && RW0_wmode) begin
133 
      ram[RW0_addr][63:0] <= RW0_wdata[63:0];
134 
    end
135 
  assign RW0_rdata = ram[reg_RW0_addr];
136 
 
137 
endmodule
138 
 
139 
module mem_ext(
140 
  input W0_clk,
141 
  input [24:0] W0_addr,
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  input W0_en,
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  input [63:0] W0_data,
144 
  input [7:0] W0_mask,
145 
  input R0_clk,
146 
  input [24:0] R0_addr,
147 
  input R0_en,
148 
  output [63:0] R0_data
149 
);
150 
 
151 
  reg [24:0] reg_R0_addr;
152 
  reg [63:0] ram [33554431:0];
153 
  `ifdef RANDOMIZE
154 
    integer initvar;
155 
    initial begin
156 
      #0.002 begin end
157 
      for (initvar = 0; initvar < 33554432; initvar = initvar+1)
158 
        ram[initvar] = {2 {$random}};
159 
      reg_R0_addr = {1 {$random}};
160 
    end
161 
  `endif
162 
  integer i;
163 
  always @(posedge R0_clk)
164 
    if (R0_en) reg_R0_addr <= R0_addr;
165 
  always @(posedge W0_clk)
166 
    if (W0_en) begin
167 
      if (W0_mask[0]) ram[W0_addr][7:0] <= W0_data[7:0];
168 
      if (W0_mask[1]) ram[W0_addr][15:8] <= W0_data[15:8];
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      if (W0_mask[2]) ram[W0_addr][23:16] <= W0_data[23:16];
170 
      if (W0_mask[3]) ram[W0_addr][31:24] <= W0_data[31:24];
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      if (W0_mask[4]) ram[W0_addr][39:32] <= W0_data[39:32];
172 
      if (W0_mask[5]) ram[W0_addr][47:40] <= W0_data[47:40];
173 
      if (W0_mask[6]) ram[W0_addr][55:48] <= W0_data[55:48];
174 
      if (W0_mask[7]) ram[W0_addr][63:56] <= W0_data[63:56];
175 
    end
176 
  assign R0_data = ram[reg_R0_addr];
177 
 
178 
endmodule
179 
 
180 
module mem_0_ext(
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  input W0_clk,
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  input [8:0] W0_addr,
183 
  input W0_en,
184 
  input [63:0] W0_data,
185 
  input [7:0] W0_mask,
186 
  input R0_clk,
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  input [8:0] R0_addr,
188 
  input R0_en,
189 
  output [63:0] R0_data
190 
);
191 
 
192 
  reg [8:0] reg_R0_addr;
193 
  reg [63:0] ram [511:0];
194 
  `ifdef RANDOMIZE
195 
    integer initvar;
196 
    initial begin
197 
      #0.002 begin end
198 
      for (initvar = 0; initvar < 512; initvar = initvar+1)
199 
        ram[initvar] = {2 {$random}};
200 
      reg_R0_addr = {1 {$random}};
201 
    end
202 
  `endif
203 
  integer i;
204 
  always @(posedge R0_clk)
205 
    if (R0_en) reg_R0_addr <= R0_addr;
206 
  always @(posedge W0_clk)
207 
    if (W0_en) begin
208 
      if (W0_mask[0]) ram[W0_addr][7:0] <= W0_data[7:0];
209 
      if (W0_mask[1]) ram[W0_addr][15:8] <= W0_data[15:8];
210 
      if (W0_mask[2]) ram[W0_addr][23:16] <= W0_data[23:16];
211 
      if (W0_mask[3]) ram[W0_addr][31:24] <= W0_data[31:24];
212 
      if (W0_mask[4]) ram[W0_addr][39:32] <= W0_data[39:32];
213 
      if (W0_mask[5]) ram[W0_addr][47:40] <= W0_data[47:40];
214 
      if (W0_mask[6]) ram[W0_addr][55:48] <= W0_data[55:48];
215 
      if (W0_mask[7]) ram[W0_addr][63:56] <= W0_data[63:56];
216 
    end
217 
  assign R0_data = ram[reg_R0_addr];
218 
 
219 
endmodule

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