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[/] [riscv_vhdl/] [trunk/] [rtl/] [techmap/] [bufg/] [idsbuf_tech.vhd] - Blame information for rev 5

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1 5 sergeykhbr
----------------------------------------------------------------------------
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--! @file
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--! @copyright  Copyright 2015 GNSS Sensor Ltd. All right reserved.
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--! @author     Sergey Khabarov
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--! @brief      Virtual input buffer with the differential signals.
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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entity idsbuf_tech is
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  generic (
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    generic_tech : integer := 0
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  );
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  port (
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    clk_p : in std_logic;
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    clk_n : in std_logic;
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    o_clk  : out std_logic
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  );
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end;
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architecture rtl of idsbuf_tech is
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  component idsbuf_xilinx is
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  port (
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    clk_p : in std_logic;
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    clk_n : in std_logic;
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    o_clk  : out std_logic
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  );
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  end component;
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begin
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  infer : if generic_tech = inferred generate
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      o_clk <= clk_p;
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  end generate;
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  xil0 : if generic_tech = virtex6 or generic_tech = kintex7 generate
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      x1 : idsbuf_xilinx port map (
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         clk_p => clk_p,
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         clk_n => clk_n,
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         o_clk  => o_clk
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      );
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  end generate;
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end;

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