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[/] [riscv_vhdl/] [trunk/] [rtl/] [techmap/] [bufg/] [igdsbuf_tech.vhd] - Blame information for rev 5

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1 5 sergeykhbr
----------------------------------------------------------------------------
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--! @file
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--! @copyright  Copyright 2015 GNSS Sensor Ltd. All right reserved.
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--! @author     Sergey Khabarov
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--! @brief      Virtual Gigabits buffer with the differential signals.
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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entity igdsbuf_tech is
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  generic (
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    generic_tech : integer := 0
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  );
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  port (
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    gclk_p : in std_logic;
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    gclk_n : in std_logic;
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    o_clk  : out std_logic
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  );
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end;
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architecture rtl of igdsbuf_tech is
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  component igdsbuf_kintex7 is
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  generic (
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    generic_tech : integer := 0
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  );
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  port (
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    gclk_p : in std_logic;
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    gclk_n : in std_logic;
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    o_clk  : out std_logic
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  );
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  end component;
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  component igdsbuf_virtex6 is
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  generic (
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    generic_tech : integer := 0
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  );
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  port (
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    gclk_p : in std_logic;
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    gclk_n : in std_logic;
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    o_clk  : out std_logic
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  );
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  end component;
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begin
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  infer : if generic_tech = inferred generate
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      o_clk <= gclk_p;
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  end generate;
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  xv6 : if generic_tech = virtex6 generate
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      x1 : igdsbuf_virtex6 port map (
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         gclk_p => gclk_p,
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         gclk_n => gclk_n,
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         o_clk  => o_clk
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      );
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  end generate;
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  xk7 : if generic_tech = kintex7 generate
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      x1 : igdsbuf_kintex7 port map (
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         gclk_p => gclk_p,
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         gclk_n => gclk_n,
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         o_clk  => o_clk
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      );
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  end generate;
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end;

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