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1 2 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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OUTFILE PREFIX_dec.v
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INCLUDE def_ahb_matrix.txt
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ITER MX
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ITER SX
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module PREFIX_dec (PORTS);
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   input [ADDR_BITS-1:0]                       MMX_HADDR;
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   output [SLV_BITS-1:0]                       MMX_slv;
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   parameter                                  DEC_MSB =  ADDR_BITS - 1;
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   parameter                                  DEC_LSB =  ADDR_BITS - SLV_BITS;
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   reg [SLV_BITS-1:0]                          MMX_slv;
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   LOOP MX
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     always @(*)
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       begin
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          case (MMX_HADDR[DEC_MSB:DEC_LSB])
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            BIN(SX SLV_BITS) : MMX_slv = 'dSX;
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            default : MMX_slv = 'dSERR;
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          endcase
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       end
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   ENDLOOP MX
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     endmodule
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